Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Andry et al. (US 2009/0032951 A1) in view of Wang et al. (US 2015/0235899 A1) and Lee et al. (US 2013/0285257 A1).
Regarding independent claim 16: Andry teaches (e.g., Figs. 2 and 13-14) a through-silicon-via (TSV) structure, comprising:
a silicon-based substrate ([0031], [0043] and [0048]: silicon based substrate);
wherein an initial through hole is formed running through the silicon-based substrate (the manufacturing steps are not subject to patentability in a "product claim", only the final structure must be claimed);
a TSV ([0043]: TSV) running through the silicon-based substrate ([0043]: step 1310; Fig. 2 initial through hole 202), and the TSV being vertical ([0043]: step 1310; 202); and an inner wall of the TSV being smooth ([0043] and [0047]);
Andry does not expressly teach that the inner wall is free of a silicon oxide film; the TSV being free of a notch and free of an undercut at ends of the TSV.
However, Wang teaches (e.g., Figs. 1A-1D) a method comprising forming an initial through hole ([0015]: 3) and oxidizing an inner wall of the initial through hole to form a silicon oxide film on the inner wall ([0015]: 3a) of the initial through hole ([0015]);
Wang further teaches removing all of the silicon oxide film on the inner wall ([0015]: 3a) of the initial through hole ([0015]: 3) to obtain a smooth inner wall and a TSV structure with a TSV ([0015]).
Therefore, Andry teaches that the inner wall is free of a silicon oxide film ([0015]).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Andry, the TSV, wherein the inner wall is free of a silicon oxide film, as taught by Wang, for the benefits of cleaning the trench from debris, humidity and native oxide layer detrimental to the device interconnect and thus improving device interconnect reliability.
Lee teaches (e.g., Figs. 1-21) a through-silicon-via (TSV) comprising a through hole ([0026]: 132) and a TSV ([0017]-[0018]: 142);
Lee further teaches that the TSV ([0017]-[0018]: 142) is free of a notch and free of an undercut at ends of the TSV (Fig. 17; [0028]; the end of the TSV reaches underlayer 113 without a notch or an undercut at its ends within the substrate 100).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Andry as modified by Wang, the structure, wherein the TSV is free of a notch and free of an undercut at ends of the TSV, as taught by Lee, for the benefits of controlling the precise dimensions of the TSV structure by avoiding over-etching the via hole, which can cause interconnection reliability issues.
Regarding claim 17: Andry teaches the claim limitation of the TSV structure according to claim 16, on which this claim depends,
wherein the silicon-based substrate has a polished surface ([0043] and [0047]: step 1310 and 1410 results in a polished surface; Fig. 2: the through hole 202 does not include a wavy surface).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Andry et al. (US 2009/0032951 A1) in view of Miyakawa et al. (US 2009/0160050 A1), Wang et al. (US 2015/0235899 A1) and Lee et al. (US 2013/0285257 A1).
Regarding independent claim 18: Andry teaches (e.g., Figs. 2 and 13-14) an electronic device, comprising:
a through-silicon-via (TSV) interconnection structure ([0035]),
the TSV interconnection structure comprises:
a silicon-based substrate ([0031], [0043] and [0048]: silicon-based substrate),
wherein an initial through hole is formed running through the silicon-based substrate (the manufacturing steps are not subject to patentability in a "product claim", only the final structure must be claimed);
a TSV running through the silicon-based substrate ([0043], [0045] and [0047]-[0050]: Fig. 12), and the TSV being vertical, and an inner wall of the TSV being smooth ([0043], [0045] and [0047]-[0050]: step 1310 and 1410 results in a polished surface; Fig. 2: the through hole 202 does not include a wavy surface; final device structure 12, shows TSV being vertical, and an inner wall of the TSV being smooth);
Andy does not expressly teach a first chip; a second chip; and
wherein: the first chip, the TSV interconnection structure and the second chip are stacked in sequence,
the first chip and the second chip are interconnected through the TSV interconnection structure; the inner wall is free of a silicon oxide film;
the TSV being free of a notch and free of an undercut at ends of the TSV.
Miyakawa teaches (e.g., Figs. 17-20) an electronic device, comprising an interconnection structure ([0071]-[0077]: interconnection structure in 1WC;)
a first chip ([0067]: 1WB);
a second chip ([0067]: 1WA);
wherein the first chip (1WB), the TSV interconnection structure and the second chip (1WA) are stacked in sequence ([0071]-[0077]: interconnection structure in 1WC),
the first chip and the second chip are interconnected through the TSV interconnection structure ([0071]-[0077]).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the method of Andy, the first chip; the second chip; and wherein the first chip, the TSV interconnection structure and the second chip are stacked in sequence, the first chip and the second chip are interconnected through the TSV interconnection structure, as taught by Miyakawa, for the benefits on increasing the device density, which in turn increases the integrated circuit functionality and capacity.
However, Wang teaches (e.g., Figs. 1A-1D) a method comprising forming an initial through hole ([0015]: 3) and oxidizing an inner wall of the initial through hole to form a silicon oxide film on the inner wall ([0015]: 3a) of the initial through hole ([0015]);
Wang further teaches removing all of the silicon oxide film on the inner wall ([0015]: 3a) of the initial through hole ([0015]: 3) to obtain a smooth inner wall and a TSV structure with a TSV ([0015]).
Therefore, Andry teaches that the inner wall is free of a silicon oxide film ([0015]).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Andry as modified by Miyakawa, the TSV, wherein the inner wall is free of a silicon oxide film, as taught by Wang, for the benefits of cleaning the trench from debris, humidity and native oxide layer detrimental to the device interconnect and thus improving device interconnect reliability.
Lee teaches (e.g., Figs. 1-21) a through-silicon-via (TSV) comprising a through hole ([0026]: 132) and a TSV ([0017]-[0018]: 142);
Lee further teaches that the TSV ([0017]-[0018]: 142) is free of a notch and free of an undercut at ends of the TSV (Fig. 17; [0028]; the end of the TSV reaches underlayer 113 without a notch or an undercut at its ends within the substrate 100).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Andry as modified by Wang, the structure, wherein the TSV is free of a notch and free of an undercut at ends of the TSV, as taught by Lee, for the benefits of controlling the precise dimensions of the TSV structure by avoiding over-etching the via hole, which can cause interconnection reliability issues.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-18 have been considered but are moot because the new ground of rejection does not rely on the same combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument or for newly included limitation.
Allowable Subject Matter
Claims 1-15 are allowable.
The following is an examiner’s statement of reasons for allowability:
Regarding claim 1: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a method for manufacturing a through-silicon-via (TSV) structure, the method comprising:
“wherein forming the initial through hole comprises placing the silicon-based substrate on a supporting substrate and etching the silicon-based substrate, the silicon-based substrate being in direct contact with the supporting substrate, an etching depth of the etching being greater than a thickness of the silicon-based substrate, and the supporting substrate being slightly etched as part of the through hole”.
Claims 2-15 depend from claim 1, and therefore, are allowable for the same reason as claim 1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
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/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812
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