Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. Pub. No. 20180180665 to Delacruz et al. (Delacruz) in view of U.S. Pat. Pub. No. 20190181063 to Liao et al. (Liao).
Regarding Claim 1, Delacruz teaches a semiconductor wafer comprising:
a first die 304 including a first integrated circuit having at least one trimmable or programmable component [0099], the at least one trimmable or programmable component being configured to be trimmed or permanently altered in response to an electrical signal; and
a second die 302 arranged adjacent to the first die, the second die including a second integrated circuit, and at least one contact pad arranged to allow an electrical connection to be made to the second integrated circuit, the at least one contact pad being additionally electrically connected to the at least one trimmable or programmable component of the first die such that the at least one contact pad of the second die is configured to act as a probe pad (see Fig 4A, [0040, 0099], test IC 302 is probed and electrical connections to the circuit die 304 perform testing and/or trimming; although no contact pad is shown in Fig. 4A, they are implicit as the electrical connections between the die must terminate at some sort of contact on both 302 and 304).
Delacruz does not explicitly teach first and second angled fingers. However, in analogous art, Liao teaches in Fig. 6 at least first 325 and second 330 angled fingers that overlap (see Figs. 2 and 3 showing connections in cross section) in an area between first and second dies. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Liao to form complex interconnections between die in a testing/ trimming context.
Regarding Claim 2, Delacruz and Liao teach the semiconductor wafer of claim 1 wherein the at least one contact pad of the second die is electrically connected to the at least one trimmable or programmable component of the first die by a conductor extending from the at least one contact pad to the at least one trimmable or programmable component (see Fig. 4A).
Regarding Claim 3, Delacruz and Liao teach the semiconductor wafer of claim 2 wherein the at least one contact pad of the second die is directly electrically connected to the at least one trimmable or programmable component of the first die by the conductor (see Fig. 4A).
Regarding Claim 4, Delacruz and Liao teach the semiconductor wafer of claim 2 wherein the at least one contact pad of the second die is electrically connected to the at least one trimmable or programmable component of the first die via trimming control circuitry (since the test/trim die 302 tests or trims the ICs 304, it is implicit that the trim circuitry on 302 is electrically connected to the ICs 304).
Regarding Claim 5, Delacruz and Liao teach the semiconductor wafer of claim 1 wherein the at least one trimmable or programmable component is a fuse or a one-time programmable device [0099].
Regarding Claim 6, Delacruz and Liao teach the semiconductor wafer of claim 1 wherein the at least one trimmable or programmable component is a memory [0099].
Regarding Claim 7, Delacruz and Liao teach the semiconductor wafer of claim 1 but does not explicitly teach that the first integrated circuit further includes a plurality of trimmable or programmable components and the second die further includes a plurality of contacts pads, each contact pad of the second die being electrically connected to a respective trimmable or programmable component of the first die such that each contact pad of the second die is configured to act as a probe pad for its respective trimmable component. However, mere duplication of parts has no patentable significance unless a new and unexpected result is produced (MPEP 2144.04(VI)(B)). In this case, the person of ordinary skill having the benefit of Delacruz can readily add additional pads and additional trim circuitry without altering the mode of operation of Delacruz.
Regarding Claim 10, Delacruz and Liao teach the semiconductor wafer of claim 1 further comprising a third die arranged adjacent to the first die on an opposing side of the first die to the second die, the third die including a third integrated circuit, and at least one contact pad arranged to allow an electrical connection to be made to the third integrated circuit, the at least one contact pad of the third die being additionally electrically connected to the at least one trimmable or programmable component of the first die such that the at least one contact pad of either the second die or the third die can be configured to act as at least one probe pad (see Fig. 4A, test circuit 302 is surrounded by multiple product IC 304).
Regarding Claim 11, Delacruz and Liao teach the semiconductor wafer of claim 1 wherein the first die further includes a supply voltage contact pad for providing a supply voltage to the first integrated circuit and a ground contact pad for providing an electrical ground for the first integrated circuit (power and ground busses necessitate the existence of power and ground pads, [0041]).
Regarding Claim 12, Delacruz and Liao teach the semiconductor wafer of claim 1 wherein the first die further includes a control contact pad for providing at least one control signal to the first integrated circuit (control busses 332 in Fig. 3J at least provide signals to control logic 350, although shown in schmematic, necessitate control contact pads).
Regarding Claim 13, Delacruz and Liao teach the semiconductor wafer of claim 1 comprising a first plurality of dies arranged in a first reticle field area and a second plurality of dies arranged in a second reticle field area, the first reticle field area being electrically connected to the second reticle field area by a conductive section (each IC is a reticle field and they are all interconnected by conductive sections therebetween, see again Fig. 4A).
Regarding Claim 14, Delacruz and Liao teach the semiconductor wafer of claim 13 wherein the conductive section is arranged in a saw street between adjacent dies (see Fig. 4A, conductive members extend between die on saw streets).
Regarding Claim 15, Delacruz and Liao teach the semiconductor wafer of claim 13 wherein the conductive section includes a metal or metal alloy (conductive wiring on a semiconductor substrate is well known to be metal, see also Claim 9).
Regarding Claim 16, Delacruz and Liao teach the semiconductor wafer of claim 13 wherein each die in each of the first and second reticle field areas is connected to an adjacent die by a conductive section (see Fig. 4A).
Regarding Claim 17, Delacruz and Liao teach the semiconductor wafer of claim 1 comprising a plurality of dies configured to be tested in pairs, each pair of dies including a first paired die and a second paired die, the first paired die being configured to be tested from the second paired die and the second paired die being configured to be tested from a first pair die (see Figs. 3A-3G, for example; the die 304 are programmable through logic blocks and therefore are configurable accordingly).
Regarding Claim 18, Delacruz and Liao teach a method of testing or trimming or programming a semiconductor wafer including a first die including a first integrated circuit having at least one trimmable or programmable component, the method comprising: making an electrical connection to at least one probe pad, the at least one probe pad including a contact pad of a second die arranged adjacent to the first die, the contact pad of the second die being electrically connected to the at least one trimmable or programmable component of the first die; and applying an electrical signal to the contact pad of the second die to trim or permanently alter an electrical characteristic of the at least one trimmable or programmable component (structure described in the rejection of Claim 1 above implies this method).
Regarding Claim 20, Delacruz and Liao teach the method of claim 18 wherein making an electrical connection to the at least one probe pad includes making an electrical connection to a contact pad of either a second die or a third die arranged adjacent to the first die and on opposing sides of the first die, the contact pad of the second die and third die being configured to act as the at least one probe pad and being electrically connected to the at least one trimmable or programmable component of the first die (one single test chip 302 tests and trims multiple product ICs 304, any of which can be a second or third die).
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Delacruz and Liao as applied to Claim 1 and further in view of Applicant’s Admitted Prior Art.
Regarding Claim 8, Delacruz and Liao teach the semiconductor wafer of claim 1 but does not explicitly teach that the first and second dies have a rectangular shape, a long side of the second die being arranged adjacent and parallel to a long edge of the first die and at least one contact pad arranged parallel to a long edge of the second die is used to electrically connect to the at least one trimmable or programmable component of the first die. However, applicants admit as prior art in the instant specification that “it is common for dies and their associated semiconductor devices to have a rectangular aspect ratio and therefore the benefits of the arrangement 301 of FIG. 4A would generally be realized [0070].” It would have been obvious to the person of ordinary skill in the art before the time of filing to include the known prior art as described to realize the benefits described in the quoted section.
Regarding Claim 9, Delacruz and Liao teach the semiconductor wafer of claim 1 further comprising a plurality of dies arranged in a matrix or grid (see Fig. 4A), but does not explicitly teach that plurality of dies having a rectangular shape and each including a trimmable or programmable component, wherein contact pads arranged adjacent to long sides of the plurality of dies are electrically connected to a trimmable or programmable component in adjacent dies. However, see above rejection of Claim 8.
Regarding Claim 9, Delacruz and Liao teach the method of claim 18 but does not explicitly teach determining an electrical characteristic of the at least one trimmable or programmable component prior to the step of applying an electrical signal to the at least one probe pad. However, Delacruz teaches both testing and trimming. It would have been obvious to the person of ordinary skill in the art before the time of filing to test a parameter before trimming it because it follows naturally that the state of an element should be determined to know whether or not, or to what degree or how it should be adjusted or trimmed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/EVREN SEVEN/Primary Examiner, Art Unit 2812