Prosecution Insights
Last updated: August 06, 2026
Application No. 18/105,045

LIGHT-EMITTING STRUCTURE

Non-Final OA §112
Filed
Feb 02, 2023
Priority
Sep 13, 2010 — provisional 61/382,451 +5 more
Examiner
CHI, SUBERR L
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Epistar Corporation
OA Round
5 (Non-Final)
84%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
550 granted / 652 resolved
+16.4% vs TC avg
Minimal +3% lift
Without
With
+2.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
22 currently pending
Career history
669
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
44.6%
+4.6% vs TC avg
§102
23.8%
-16.2% vs TC avg
§112
28.3%
-11.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 652 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA Status The present application is being examined under the pre-AIA first to invent provisions. Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 24, 2026 has been entered. Drawing Objection The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “second isolation layer forms a flat plane across the first light-emitting structure unit and the second light-emitting structure unit” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. pre-AIA 35 U.S.C. § 112, 2nd ¶ The following is a quotation of pre-AIA 35 U.S.C. § 112, second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 26 is rejected under 35 U.S.C. § 112(b) or pre-AIA 35 U.S.C. § 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant, regards as the invention. As to claim 26, it is unclear how “second isolation layer forms a flat plane across the first light-emitting structure unit and the second light-emitting structure unit” because the second isolation layer 17 instead forms a variety of angled surfaces, not merely a flat plane, across the first light-emitting structure unit 10A and the second light-emitting structure unit 10B in instant FIG. 1. Indication of Allowable Subject Matter The following is a statement of reasons for the indication of allowable subject matter: claims 1-7, 11, 13-16, 21, 22, 24, 25, and 27-29 are indicated as being allowable because prior art fails to teach “an isolation layer formed on the first sidewall and the second sidewall, comprising a first end on the first light-emitting structure unit and wherein an acute angle is formed between two connected surfaces of the first end in a cross-sectional view” (claim 1) and “the mesa area surrounding the upper semiconductor layer of the second light-emitting structure unit” (claim 13) and “a first isolation layer, formed in the trench” (claim 21). As to claims 1 and 13, the limitations have not changed and the Examiner maintains the same reasons for allowance as delineated in the Notice of Allowability issued on January 26, 2026. As to claim 21, Seo et al. (U.S. Patent Publication No. 2010/0163900 A1), as cited in the IDS and hereafter “Seo”, teaches in FIG. 20 a first light-emitting structure unit LS1 and a second light-emitting structure unit LS2; a trench (FIG. 2, FIG. 7, part of 21a), formed between the first and second light-emitting structure units; a first isolation layer 51; a second isolation layer 63, formed on the first isolation layer; and an electrical connection 65, formed on the second isolation layer and electrically connecting the first light-emitting structure unit and the second light-emitting structure unit. However, Seo does not teach the first isolation layer 51 formed in the trench. Claim 21 was also evaluated for double patenting against U.S. Patent No. 10,062,730 B2 and U.S. Patent No. 11,942,509 B2. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUBERR CHI whose telephone number is (571)270-3955. The examiner can normally be reached 10am to 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SUBERR L CHI/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Show 6 earlier events
Mar 20, 2025
Non-Final Rejection mailed — §112
Jun 20, 2025
Response Filed
Sep 04, 2025
Final Rejection mailed — §112
Dec 04, 2025
Request for Continued Examination
Dec 16, 2025
Response after Non-Final Action
Apr 24, 2026
Request for Continued Examination
Apr 28, 2026
Response after Non-Final Action
Apr 30, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12696569
SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS
3y 11m to grant Granted Jul 28, 2026
Patent 12685150
EXTENDED VIA CONNECT FOR PIXEL ARRAY
3y 6m to grant Granted Jul 14, 2026
Patent 12672380
PHOTODIODE WITH ORTHOGONAL LAYER STRUCTURE
2y 11m to grant Granted Jun 30, 2026
Patent 12666659
SEMICONDUCTOR MEMORY STRUCTURE HAVING DRAIN STRESSOR, SOURCE STRESSOR AND BURIED GATE AND METHOD OF MANUFACTURING THE SAME
2y 11m to grant Granted Jun 23, 2026
Patent 12666884
SiC SEMICONDUCTOR SUBSTRATE AND FABRICATION METHOD OF THE SiC SEMICONDUCTOR SUBSTRATE
3y 0m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

5-6
Expected OA Rounds
84%
Grant Probability
87%
With Interview (+2.8%)
2y 9m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 652 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month