DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment dated 01/20/2026, in which claims 11, 15, 16, 21were amended, claims 1-10, 24, 29-30 were cancelled, claims 31-33 were added, has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-23, 25-28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 16, claim 16 recites the limitation “wherein a remaining portion of the fin is formed and protrudes from the dummy gate spacers into the recess along a fin extending direction beyond a sidewall surface of the dummy spacer spacers facing the recess in plan view.” There is insufficient antecedent basis for the limitation “the dummy spacer spacers” in the claim.
For the purpose of this Action, the above limitation will be interpreted and examined as --the dummy gate spacers--.
Regarding claim 21, claim 21 recites “performing an etching process on the dummy gate structure to form a recess in and through the dummy gate structure and to remove a portion of an upper region of the fin underlying the dummy gate structure by using the gate dielectric layer as a stop layer.” It is unclear how the gate dielectric layer is used as a stop layer to remove a portion of an upper region of the fin underlying the dummy gate structure when the portion of the upper region of the fin is underlying the gate dielectric layer, and the gate dielectric layer must be removed before removing the portion of the upper region of the fin.
For the purpose of this Action, the above limitation of claim 21 will be interpreted and examined as --performing an etching process on the dummy gate structure to form a recess in and through the dummy gate structure and to remove a portion of an upper region of the fin underlying the dummy gate structure.--
Claims depending from the rejected claims noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-23, 25-28, 31-33 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US Pub. 20210057545), hereafter Lin545 and Shi et al. (Us Pub. 20190148373).
Regarding claim 11, Lin545 discloses in Fig. 5-Fig. 13D a method of forming a semiconductor device, the method comprising:
forming a fin [52] on a substrate [50];
forming a first isolation region [56] surrounding the fin [52], wherein an upper region of the fin [52] protrudes above the first isolation region [56] and forms a channel region;
forming a dummy gate structure [74, 72, 60] extending over the first isolation region [56] and the upper region;
forming a spacer [80 and 86] on sidewalls of the dummy gate structure [74, 72, 60] and the upper region;
epitaxially growing a source/drain region [82] adjacent the upper region;
performing an etching process on the dummy gate structure [74, 72, 60] to form a recess [90] in and through the dummy gate structure [74, 72, 60], wherein after performing the etching process, portions of the dummy gate structure [85] remain in corner regions defined by the spacer [80 and 86] and the upper region.
Lin545 fails to disclose
performing the etching process to remove the upper region underlying the dummy gate structure, wherein after performing the etching process, a remaining portion of the upper region is formed and protrudes from the spacer into the recess along a fin extending direction beyond a sidewall surface of the spacer facing the recess in plan view; and
portions of the dummy gate structure remain in corner regions defined by the spacer and the remaining portion of the upper region;
forming a separation structure in the recess, wherein the remaining portions of the dummy gate structure separate portions of the separation structure from the source/drain region.
Shi et al. discloses in Figs. 12-16, paragraph [0033]-[0034], [0045]-[0046]
performing an etching process on the dummy gate structure [120] to form a recess [R1] in and through the dummy gate structure [120] and to remove the upper region underlying the dummy gate structure [120], wherein after performing the etching process, a remaining portion of the upper region is formed protrudes from the spacer [190] into the recess [R1] along a fin extending direction beyond a sidewall surface of the spacer [190] facing the recess [R1] in plan view [Fig. 12];
forming a separation structure [252] in the recess [R1][Fig. 14, Fig. 16];
wherein portions of the separation structure [252] separate from the source/drain region [170][Fig. 14, Fig. 16].
Extending recess [90] disclosed by Lin545 to remove the upper region of fin [52] underlying the dummy gate structure and forming separation structure as required by Shi et al. would result to “after performing the etching process, a fin end of the upper region is formed and protrudes from the spacer into the recess along a fin extending direction in plan view; and portions of the dummy gate structure remain in corner regions defined by the spacer and the fin end of the upper region; wherein the remaining portions of the dummy gate structure separate portions of the separation structure from the source/drain region.”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Shi et al. into the method of Lin545 to include performing the etching process to remove the upper region underlying the dummy gate structure, wherein after performing the etching process, a remaining portion of the upper region is formed and protrudes from the spacer into the recess along a fin extending direction beyond a sidewall surface of the spacer facing the recess in plan view; and portions of the dummy gate structure remain in corner regions defined by the spacer and the remaining portion of the upper region; forming a separation structure in the recess, wherein the remaining portions of the dummy gate structure separate portions of the separation structure from the source/drain region. The ordinary artisan would have been motivated to modify Lin545 in the above manner for the purpose of providing method for forming a single diffusion break (SDB) structure to electrically separate two semiconductor regions of one fin from each other [paragraph [0046] of Shi et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Alternatively,
Regarding claim 11, Shi et al. discloses in Fig. 2-Fig. 8, Fig. 12, Fig. 14, Fig. 16, paragraph [0033]-[0034], [0045]-[0046] a method of forming a semiconductor device, the method comprising:
forming a fin [110] on a substrate [130];
forming a first isolation region [140] surrounding the fin [110], wherein an upper region of the fin [110] protrudes above the first isolation region [140] and forms a channel region;
forming a dummy gate structure [120] extending over the first isolation region [140] and the upper region;
forming a spacer [150/190] on sidewalls of the dummy gate structure [120] and the upper region;
epitaxially growing a source/drain region [170] adjacent the upper region;
performing an etching process on the dummy gate structure [120] to form a recess [R1] in and through the dummy gate structure [120] and to remove the upper region underlying the dummy gate structure [120], wherein after performing the etching process, a remaining portion of the upper region is formed protrudes from the spacer [190] into the recess [R1] along a fin extending direction beyond a sidewall surface of the spacer [190] facing the recess [R1] in plan view [Fig. 12];
forming a separation structure [252] in the recess [R1][Fig. 14, Fig. 16],
wherein portions of the separation structure [252] separate from the source/drain region [170].
Shi et al. fails to disclose
portions of the dummy gate structure remain in corner regions defined by the spacer and the remaining portion of the upper region,
wherein the remaining portions of the dummy gate structure separate portions of the separation structure from the source/drain region.
Lin545 discloses in Fig. 13B-13C, paragraph [0041]-[0045]
portions of the dummy gate structure [85] remain in corner regions defined by the spacer and the remaining portion of the upper region.
Incorporating the teaching of Lin545 to form the recess in and through the dummy gate structure of Shi et al., then extending the recess to remove the upper region of fin underlying the dummy gate structure and forming separation structure as required by Shi et al. would result to portions of the dummy gate structure remain in corner regions defined by the spacer and the remaining portion of the upper region, and wherein the remaining portions of the dummy gate structure separate portions of the separation structure from the source/drain region.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lin545 into the method of Shi et al. to include portions of the dummy gate structure remain in corner regions defined by the spacer and the fin end of the upper region, wherein the remaining portions of the dummy gate structure separate portions of the separation structure from the source/drain region. The ordinary artisan would have been motivated to modify Shi et al. in the above manner for the purpose of providing method for removing dummy gate stack to improve the yield with respect to process variation [paragraph [0008], [0050] of Lin545].
Regarding claims 12 and 26, Lin545 discloses in Fig. 13C, paragraph [0043]-[0044]
wherein the remaining portions [85] of the dummy gate structure are triangle shaped.
Regarding claim 13, Shi et al. discloses in Fig. 12, paragraph [0042]-[0044]
wherein the etching process stops after at least a portion of the fin [110] under the dummy gate structure [120] is removed.
Regarding claims 14 and 25, Lin545 discloses in Fig. 13C, paragraph [0042]-[0043]
wherein the recess [90] formed in the dummy gate structure has a round-cornered rectangular shape in plan view.
Regarding claim 15, Shi et al. discloses in Figs. 14, Fig. 16 [0045]-[0046]
wherein forming the separation structure [252] comprises forming a dielectric plug [240] into the substrate [130], the dielectric plug [240] separating the remaining portion of the fin from an adjacent remaining portion of another fin.
Regarding claim 16, Lin545 discloses in Fig. 3-Fig. 13D, paragraph [0013]-[0045] a method of forming a semiconductor device, the method comprising:
forming a fin [52] protruding from a semiconductor substrate [50];
forming a dummy gate [74, 72, 60] over the fin [52];
forming dummy gate spacers [80 and 86] on sidewalls of the dummy gate [74, 72, 60];
forming a source/drain region [82] in the fin [52];
performing an etching process on the dummy gate structure [74, 72, 60] to form a recess [90], wherein the etching process comprises:
simultaneously etching first portions [portions adjacent to spacer] of the dummy gate [74, 72, 60] at a first etching rate and etching second portions [middle/bulk regions] of the dummy gate [74, 72, 60] at a second etching rate that is greater than the first etching rate, wherein each first portion [portions adjacent to spacer] of the dummy gate [74, 72, 60] comprises a first surface over a sidewall of the dummy gate spacers [80 and 86] and a second surface over a sidewall of the fin [52], wherein the second portions [middle/bulk regions] of the dummy gate [74, 72, 60] are adjacent the first portions; and
stopping the etching process after the second portions [middle/bulk regions] of the dummy gate [74, 72, 60] is removed, and the first portions [85] of the dummy gate remain after stopping the etching process; and
wherein the remaining first portions [85] of the dummy gate [74, 72, 60] protrude from the dummy gate spacers [80 and 86] into the recess [90] with a distance [D1] in plan view in a range from 1 nm to 100 nm [2 nm and about 30 nm][paragraph [0043]].
Lin545 fails to disclose
stopping the etching process after the second portions of the dummy gate and at least a portion of the fin under the second portions of the dummy gate are removed;
wherein a remaining portion of the fin is formed and protrudes from the dummy gate spacers into the recess along a fin extending direction beyond a sidewall surface of the dummy spacer spacers facing the recess in plan view,
forming a separation structure in the recess, wherein the remaining first portions of the dummy gate structure separate portions of the separation structure from the source/drain region, and
wherein the remaining first portions of the dummy gate protrude from the dummy gate spacers into the separation structure with a distance in plan view in a range from 1 nm to 100 nm.
Shi et al. discloses in Figs. 12-16, paragraph [0033]-[0034], [0045]-[0046]
stopping the etching process after the second portions of the dummy gate [120] and at least a portion of the fin [110] under the second portions of the dummy gate [120] are removed [Fig. 12];
wherein a remaining portion of the fin [110] is formed and protrudes from the dummy gate spacers [190] into the recess [R1] along a fin extending direction beyond a sidewall surface of the dummy gate spacers [190] facing the recess in plan view [Fig. 12];
forming a separation structure [252] in the recess [R1][Fig. 14, Fig. 16];
wherein portions of the separation structure [252] separate from the source/drain region [170][Fig. 14, Fig. 16].
Extending recess [90] disclosed by Lin545 to remove the upper region of fin [52] underlying the dummy gate structure and forming separation structure as suggested by Shi et al. would result to “wherein the remaining first portions of the dummy gate structure separate portions of the separation structure from the source/drain region, and wherein the remaining first portions of the dummy gate protrude from the dummy gate spacers into the separation structure with a distance in plan view in a range from 1 nm to 100 nm.”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Shi et al. into the method of Lin545 to include stopping the etching process after the second portions of the dummy gate and at least a portion of the fin under the second portions of the dummy gate are removed; wherein a remaining portion of the fin is formed and protrudes from the dummy gate spacers into the recess along a fin extending direction beyond a sidewall surface of the dummy spacer spacers facing the recess in plan view, forming a separation structure in the recess, wherein the remaining first portions of the dummy gate structure separate portions of the separation structure from the source/drain region, and wherein the remaining first portions of the dummy gate protrude from the dummy gate spacers into the separation structure with a distance in plan view in a range from 1 nm to 100 nm. The ordinary artisan would have been motivated to modify Lin545 in the above manner for the purpose of providing method for forming a single diffusion break (SDB) structure to electrically separate two semiconductor regions of one fin from each other [paragraph [0046] of Shi et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
In addition, Applicant has not provided any criticality of the claimed range. It would have been obvious to modify Lin 545 and Shi et al. to provide the claimed range for at least the purpose of optimization and routine experimentation. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Alternatively,
Regarding claim 16, Shi et al. discloses in Fig. 2-Fig. 8, Fig. 12, Fig. 14, Fig. 16, paragraph [0033]-[0034], [0045]-[0046] a method of forming a semiconductor device, the method comprising:
forming a fin [110] protruding from a semiconductor substrate [130];
forming a dummy gate [120] over the fin [110];
forming dummy gate spacers [150/190] on sidewalls of the dummy gate [120];
forming a source/drain region [170] in the fin [110];
performing an etching process on the dummy gate [120] to form a recess [R1], wherein the etching process comprises:
simultaneously etching first portions [portions adjacent to spacer] of the dummy gate [120] at a first etching rate and etching second portions [middle portion] of the dummy gate [120] at a second etching rate, wherein each first portion of the dummy gate [120] comprises a first surface over a sidewall of the dummy gate spacers [190] and a second surface over a sidewall of the fin [110], wherein the second portions [middle portion] of the dummy gate [120] are adjacent the first portions [portions adjacent to spacer]; and
stopping the etching process after the second portions [middle portion] of the dummy gate [120] and at least a portion of the fin [110] under the second portions of the dummy gate [120] are removed, wherein a remaining portion of the fin [110] is formed protrudes from the dummy gate spacer [190] into the recess [R1] along a fin extending direction beyond a sidewall surface of the dummy gate spacers [190] facing the recess [R1] in plan view [Fig. 12];
forming a separation structure [252] in the recess [R1][Fig. 14, Fig. 16],
wherein portions of the separation structure [252] separate from the source/drain region [170][Fig. 14, Fig. 16].
Shi et al. fails to disclose
the second etching rate that is greater than the first etching rate;
wherein the first portions of the dummy gate remain after stopping the etching process,
wherein the remaining first portions of the dummy gate structure separate portions of the separation structure from the source/drain region, and wherein the remaining first portions of the dummy gate protrude from the dummy gate spacers into the separation structure with a distance in plan view in a range from 1 nm to 100 nm.
Lin545 discloses in Fig. 13B-13C, paragraph [0041]-[0045]
the second etching rate that is greater than the first etching rate,
wherein the first portions [85] of the dummy gate remain after stopping the etching process;
wherein the remaining first portions [85] of the dummy gate [74, 72, 60] protrude from the dummy gate spacers [80 and 86] into the recess [90] with a distance [D1] in plan view in a range from 1 nm to 100 nm [2 nm and about 30 nm][paragraph [0043]].
Incorporating the teaching of Lin545 to form the recess in and through the dummy gate structure, then extending the recess to remove the upper region of fin underlying the dummy gate structure and forming separation structure as required by Shi et al. would result to “the first portions of the dummy gate remain after stopping the etching process, wherein the remaining first portions of the dummy gate structure separate portions of the separation structure from the source/drain region, and wherein the remaining first portions of the dummy gate protrude from the dummy gate spacers into the separation structure with a distance in plan view in a range from 1 nm to 100 nm”.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lin545 into the method of Shi et al. to include the second etching rate that is greater than the first etching rate; wherein the first portions of the dummy gate remain after stopping the etching process, wherein the remaining first portions of the dummy gate structure separate portions of the separation structure from the source/drain region, and wherein the remaining first portions of the dummy gate protrude from the dummy gate spacers into the separation structure with a distance in plan view in a range from 1 nm to 100 nm. The ordinary artisan would have been motivated to modify Shi et al. in the above manner for the purpose of providing method for removing dummy gate stack to improve the yield with respect to process variation [paragraph [0008], [0050] of Lin545].
In addition, Applicant has not provided any criticality of the claimed range. It would have been obvious to modify Lin 545 and Shi et al. to provide the claimed range for at least the purpose of optimization and routine experimentation. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Regarding claim 17, Lin545 discloses in Fig. 11A-11B
forming a dummy gate dielectric [60] over the fin [52]
Regarding claims 18-19, Lin545 discloses in Fig. 13C, paragraph [0043]
wherein the remaining first portions [85] of the dummy gate [72] comprise silicon, silicon oxide, silicon nitride, or a combination thereof;
Regarding claims 19-20, Lin545 discloses in Fig. 13C, paragraph [0043]-[0044]
wherein the remaining first portions [85] of the dummy gate [72] are triangle shaped;
wherein a ratio of a width of the recess [90] to a base width [D1] of the triangle shaped remaining first portion [85] of the dummy gate structure is in a range from 0.03 to 600.
Shi et al. discloses forming the separation structure in the recess. Thus, the combination of Lin545 and Shi et al. would result to “wherein a ratio of a width of the separation structure to a base width of the triangle shaped remaining first portion of the dummy gate structure is in a range from 0.03 to 600.”
In addition, Applicant has not provided any criticality of the claimed range. It would have been obvious to modify Lin 545 and Shi et al. to provide the claimed range for at least the purpose of optimization and routine experimentation. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Regarding claim 21, Lin545 discloses in Fig. 5-Fig. 13D a method of forming a semiconductor device, the method comprising:
forming a fin [52] protruding from a semiconductor substrate [50];
forming a gate dielectric layer [60] over a top surface of the fin [52] and sidewalls of the fin [52];
forming a dummy gate structure [74, 72, 60] over the gate dielectric layer [60];
forming a spacer [80 and 86] on sidewalls of the dummy gate structure [74, 72, 60];
performing an etching process on the dummy gate structure [74, 72, 60] to form a recess [90] in and through the dummy gate structure [74, 72, 60] by using the gate dielectric layer [60] as a stop layer, wherein after performing the etching process, portions of the dummy gate structure [85] remain in corner regions defined by the spacer [80 and 86] and an upper region of the fin [52].
Lin545 fails to disclose
performing the etching process to remove the upper region underlying the dummy gate structure, wherein after performing the etching process, portions of the dummy gate structure remain in corner regions defined by the spacer and a remaining portion of the upper region of the fin;
forming a separation structure in the recess, wherein the remaining portions of the dummy gate structure and the remaining portions of the upper region of the fin protrude from the spacer into the separation structure along a fin extending direction beyond a sidewall surface of the spacer facing the recess in plan view.
Shi et al. discloses in Figs. 12-16, paragraph [0033]-[0034], [0045]-[0046]
performing the etching process on the dummy gate structure [120] to form a recess [R1] in and through the dummy gate structure [120] and to remove a portion of an upper region of the fin [110] underlying the dummy gate structure [120], wherein after performing the etching process, a portion of the upper region of the fin [110] remains;
forming a separation structure [252] in the recess [R1], wherein the remaining portions of the upper region of the fin [110] protrude from the spacer [190] into the separation structure [252] along a fin extending direction beyond a sidewall surface of the spacer [190] facing the recess [R1] in plan view.
Extending recess [90] disclosed by Lin545 to remove the upper region of fin underlying the dummy gate structure and forming separation structure as required by Shi et al. would result to “wherein after performing the etching process, portions of the dummy gate structure remain in corner regions defined by the spacer and a remaining portion of the upper region of the fin; wherein the remaining portions of the dummy gate structure and the remaining portion of the upper region of the fin protrude from the spacer into the separation structure along a fin extending direction beyond a sidewall surface of the spacer facing the recess in plan view.”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Shi et al. into the method of Lin545 to include performing the etching process to remove the upper region underlying the dummy gate structure, wherein after performing the etching process, portions of the dummy gate structure remain in corner regions defined by the spacer and a remaining portion of the upper region of the fin; forming a separation structure in the recess, wherein the remaining portions of the dummy gate structure and the remaining portions of the upper region of the fin protrude from the spacer into the separation structure along a fin extending direction beyond a sidewall surface of the spacer facing the recess in plan view. The ordinary artisan would have been motivated to modify Lin545 in the above manner for the purpose of providing method for forming a single diffusion break (SDB) structure to electrically separate two semiconductor regions of one fin from each other [paragraph [0046] of Shi et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Alternatively,
Regarding claim 21, Shi et al. discloses in Fig. 2-Fig. 8, Fig. 12, Fig. 14, Fig. 16, paragraph [0033]-[0034], [0045]-[0046] a method of forming a semiconductor device, the method comprising:
forming a fin [110] protruding from a semiconductor substrate [130];
forming a dummy gate structure [120];
forming a spacer [150/190] on sidewalls of the dummy gate structure [120];
performing an etching process on the dummy gate structure [120] to form a recess [R1] in and through the dummy gate structure [120] and to remove an upper region of the fin [110] underlying the dummy gate structure [120], wherein after performing the etching process, a portion of the upper region of the fin [110] remains;
forming a separation structure [252] in the recess [R1], wherein the remaining portions of the upper region of the fin [110] protrude from the spacer [190] into the separation structure [252] along a fin extending direction beyond a sidewall surface of the spacer [190] facing the recess [R1] in plan view.
Shi et al. fails to disclose
forming a gate dielectric layer over a top surface of the fin and sidewalls of the fin;
forming the dummy gate structure over the gate dielectric layer
wherein after performing the etching process, portions of the dummy gate structure remain in corner regions defined by the spacer and the remaining portion of the upper region of the fin; and
wherein the remaining portions of the dummy gate structure protrude from the spacer into the separation structure along a fin extending direction beyond the sidewall surface of the spacer facing the recess in plan view.
Lin545 discloses in Fig. 8A, Fig. 13B-13C, paragraph [0041]-[0045]
forming a gate dielectric layer [60] over a top surface of the fin [52]and sidewalls of the fin [52];
forming the dummy gate structure [72 and 74] over the gate dielectric layer [60];
wherein after performing the etching process, portions [85] of the dummy gate structure [72 and 74] remain in corner regions defined by the spacer [80] and the upper region of the fin [52]; and
wherein the remaining portions [85] of the dummy gate structure protrude from the spacer [80 and 86] into the recess [90] along a fin extending direction beyond the sidewall surface of the spacer [80 and 86] facing the recess [90] in plan view.
Incorporating the teaching of Lin545 to form the recess in and through the dummy gate structure, then extending the recess to remove the upper region of fin underlying the dummy gate structure and forming separation structure as required by Shi et al. would result to “after performing the etching process, portions of the dummy gate structure remain in corner regions defined by the spacer and a remaining portion of the upper region of the fin; and wherein the remaining portions of the dummy gate structure protrude from the spacer into the separation structure along a fin extending direction beyond the sidewall surface of the spacer facing the recess in plan view”.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lin545 into the method of Shi et al. to include performing the etching process on the dummy gate structure to form the recess by using the gate dielectric layer as a stop layer, wherein after performing the etching process, portions of the dummy gate structure remain in corner regions defined by the spacer and a remaining portion of the upper region of the fin; and wherein the remaining portions of the dummy gate structure protrude from the spacer into the separation structure along a fin extending direction in plan view. The ordinary artisan would have been motivated to modify Shi et al. in the above manner for the purpose of providing method for removing dummy gate stack to improve the yield with respect to process variation [paragraph [0008], [0050] of Lin545].
Regarding claim 22, Lin545 discloses in Fig. 10A-10B, paragraph [0036]-[0038]
epitaxially growing a source/drain region [82] adjacent the upper region of the fin [52].
Shi et al. discloses in Fig. 2, paragraph [0034]
epitaxially growing a source/drain region [170] adjacent the upper region of the fin [110].
Regarding claim 23, incorporating the teaching of Lin545 to form the recess in and through the dummy gate structure, then extending the recess to remove the upper region of fin underlying the dummy gate structure and forming separation structure as required by Shi et al. would result to “the remaining portions of the dummy gate structure separate portions of the separation structure from the source/drain region.”
Regarding claim 27, Lin545 discloses in paragraph [0043] wherein a base width [D1] of the triangle shaped remaining portions [85] of the dummy gate structure is in a range from 1 nm to 100 nm [2nm-30nm], and a height [thickness] of the triangle shaped remaining portions [85] of the dummy gate structure is in a range from 1 nm to 100 nm [2nm to 20nm].
Regarding claim 28, Lin545 discloses in Fig. 13C, paragraph [0043]-[0044]
wherein a ratio of a width of the recess [90] to a base width [D1] of the triangle shaped remaining first portion [85] of the dummy gate structure is in a range from 0.03 to 600.
Shi et al. discloses forming the separation structure in the recess. Thus, the combination of Lin545 and Shi et al. would result to “wherein a ratio of a width of the separation structure to a base width of the triangle shaped remaining first portion of the dummy gate structure is in a range from 0.03 to 600.”
In addition, Applicant has not provided any criticality of the claimed range. It would have been obvious to modify Lin 545 and Shi et al. to provide the claimed range for at least the purpose of optimization and routine experimentation. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Regarding claim 31, Lin545 discloses in paragraph [0043]
wherein the remaining portions [85] of the dummy gate structure [74, 72, 60] protrude from the spacer [80 and 86] into the recess [90] with a distance [D1] in plan view in a range from 1 nm to 100 nm [2 nm and about 30 nm].
Shi et al. suggests forming separation structure in the recess.
Thus, the combination of Lin545 and Shi et al. would result to “wherein the remaining portions of the dummy gate structure protrude from the spacer into the separation structure with a distance in plan view in a range from 1 nm to 100 nm.”
In addition, Applicant has not provided any criticality of the claimed range. It would have been obvious to modify Lin 545 and Shi et al. to provide the claimed range for at least the purpose of optimization and routine experimentation. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Regarding claim 32, Shi et al. discloses in Fig. 16
wherein the separation structure [252] is in contact with the sidewall surface of the spacer [190] facing the recess [R1].
Regarding claim 33, Lin545 discloses in Fig. 13C
wherein the portions [85] of the dummy gate structure in the corner regions are surrounded by the recess [90], the spacer [80], and the remaining portion of the upper region from three sides in plan view.
Shi et al. suggests forming separation structure in the recess.
Thus, the combination of Lin545 and Shi et al. would result to “wherein the portions of the dummy gate structure in the corner regions are surrounded by the separation structure, the spacer, and the remaining portion of the upper region from three sides in plan view.”
Response to Arguments
Applicant’s arguments with respect to claim(s) 11-23, 25-28, 31-33 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893