DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ogata et al. (US PGPub 2020/0082760) in view of Cho et al. (US PGPub 2023/0306890), Hatayama et al. (US PGPub 2023/0306913) and Park et al. (US PGPub 2017/0061878).
Regarding claim 1, Ogata discloses a display device (fig. 1A, display device 100) comprising:
a display panel (fig. 1A, display panel 1) including pixels (fig. 1A, pixels 4); and
a display panel driver (fig. 1A, display driver 2) which starts a scan operation in synchronization with an input timing of input image data ([0033], “vertical sync periods in the display driver 2 are defined by the internal vertical sync signal VSYNC, and various timing controls in the display driver 2 are performed using the internal vertical sync signal VSYNC as a timing reference”), performs the scan operation every a scan cycle in one frame [0044], “the timing generator 16 asserts the internal vertical sync signal VSYNC upon the start of the reception of image data #1. In one or more embodiments, the assertion of the internal vertical sync signal VSYNC initiates vertical sync period #1 in the display driver 2. In one or more embodiments, image data #1 transmitted from the host 3 to the display driver 2 may contain a predetermined command. In this case, the data interface 11 of the display driver 2 may detect the start of the reception of image data #1 from the host 3 based on the predetermined command. The predetermined command may be disposed at the head of the image data #1”), and delays a start of the scan operation ([0053], “when the display driver 2 does not detect the start of reception of image data #3 until a predetermined period of time has elapsed after the transmission of the TE packet to the host 3, the display driver 2 changes or extends the length of vertical sync period #2 by extending the front porch period and waits for the host 3 to start transmitting image data #3. In The extended part of the front porch period is indicated as “extended FP” in FIG. 3. In one or more embodiments, the emission control signal continues to control the light emission of the pixels 4 by the emission control signal is continued in the extended FP. The extended FP may correspond to one or more control cycles of the emission control signal. In such embodiments with the extended FP, the timing at which the internal vertical sync signal VSYNC is next asserted is delayed from the default timing”).
While Ogata teaches delaying or extending the length of a vertical sync period from the default timing, it has been known to perform delay until the data is input thereto during the scan operation. In a similar field of endeavor display devices, Cho discloses delays a start of the scan operation of an (N+1)-th frame by delaying a generation of a data signal for the input image data of the (N+1)-th frame until the scan operation of an N-th frame ends when the input image data of the (N+1)-th frame is input thereto during the scan operation of the N-th frame, wherein N is a positive integer ([0105], “Also, in the case in which the point in time at which rendering processing of the next frame is completed occurs during a vertical active period of the current frame during which a data enable signal and image data are being output as the point in time at which the vertical active period is commenced is delayed, a first′ vertical blank period Vblank1′ occurring immediately after completion of the current frame may be shorter than one sensing period TCMP. However, in this case, which is the case in which the frequency of the next frame approximates to the maximum frame frequency, the second′ vertical blank period Vblank2′ extended in the current frame does not exceed a maximum of one sensing period TCMP, compared to the second vertical blank period Vblank2, and therefore the vertical blank period Vblank of the next frame maintains a second time interval ITV2 (see FIG. 10), which is time from which a maximum of one sensing period TCMP is removed, or more, compared to an original first vertical blank period Vblank1”).
In view of the teachings of Ogata and Cho, it would have been obvious to one of ordinary skill in the art to perform the delay as taught by Cho, in the system of Ogata, for the purpose of solving a problem of a compensation cycle for a pixel is changed when a frame frequency is abruptly changed, whereby image spots or afterimage due to compensation delay may be incurred. In addition, abrupt fluctuation of luminance at the point in time of compensation update may be visible as flicker (Cho: [0004]).
While the combination of Ogata and Cho teaches a display driver and timing controller, it has been known that a display driver can receive signals from a host processor. In a similar field of endeavor of display devices, Hatayama further discloses the display panel driver which receives input image data and an input control signal from a host processor ([0002], “A display driver that drives a display panel may be configured to receive image data from an external source (e.g., a host, a controller, a processor, or other devices configured to provide the image data)… The display driver may be further configured to, in a synchronous mode, receive image data and external synchronization (sync) control inputs (e.g., vertical sync packets and an external vertical sync signal) from the external source, generate the vertical sync signal based on the external sync control inputs, and update the display panel based on the received image data in synchronization with the generated vertical sync signal”).
In view of the teachings of Ogata, Cho and Hatayama it would have been obvious to one of ordinary skill in the art to include the external source of Hatayama to provide signals to the display driver of Ogata and Cho, for the purpose of using a known centralized external host to provide signals to a display driver to achieve consistent synchronization.
While the combination of Ogata, Cho and Hatayama discloses a timing generator which delays timing of the vertical sync signal, however it has been known to include a timing controller, a data driver, a gate driver and an emission driver. In a similar field of endeavor of display devices, Park discloses a display panel driver including a timing controller (fig. 1, timing controller 110), a gate driver (fig. 1, gate driver 104), a data driver (fig. 1, data driver 102) and an emission driver (fig. 1, em driver 106), wherein the timing controller receives input image data and an input control signal from a host processor ([0012], “a timing controller configured to receive an input image data and timing signals from a host system, and to output a data timing control signal, a gate timing control signal, and a plurality of duty timing control signals”).
In view of the teachings of Ogata, Cho, Hatayama and Park, it would have been obvious to include a timing controller, a data driver, a gate driver and an emission driver, of Park, within the system of Ogata, Cho, and Hatayama, for the purpose of providing known structure within a display panel which has known advantages such as providing a fast response speed with high light-emitting efficiency and luminance (Park: [0005]).
Regarding claim 2, Ogata further discloses wherein the display panel driver delays a start of the scan operation of an (N+2)-th frame until a frame time of the (N+1)-th frame ends when the input image data of the (N+2)-th frame is input in the (N+1)-th frame in which the start of the scan operation is delayed (Ogata: [0053], “when the display driver 2 does not detect the start of reception of image data #3 until a predetermined period of time has elapsed after the transmission of the TE packet to the host 3, the display driver 2 changes or extends the length of vertical sync period #2 by extending the front porch period and waits for the host 3 to start transmitting image data #3. In The extended part of the front porch period is indicated as “extended FP” in FIG. 3. In one or more embodiments, the emission control signal continues to control the light emission of the pixels 4 by the emission control signal is continued in the extended FP. The extended FP may correspond to one or more control cycles of the emission control signal. In such embodiments with the extended FP, the timing at which the internal vertical sync signal VSYNC is next asserted is delayed from the default timing”, where the N+2 frame is any following frame where fig. 10 shows multiple extended FP sections).
Regarding claim 3, Ogata further discloses wherein the display panel driver performs the scan operation and a light emission operation to drive the display panel in the one frame (Ogata, [0024], “when a write operation is performed to program a drive voltage corresponding to a grayscale value into the pixel 4, the emission line EM[i] is deasserted, and the scan lines S[i-2], S[i-1] and S[i] are operated in a predetermined sequence with the data line D[j] supplied with the drive voltage, to write the drive voltage into the hold capacitor Cst. In one or more embodiments, the hold capacitor Cst is configured to hold a hold voltage corresponding to the drive voltage written into the pixel 4. In one or more embodiments, when the emission line EM[i] is deasserted, the PMOS transistors M1 and M6 are turned off and the light emitting element 6 stops emitting light. In one or more embodiments, when the emission line EM[i] is asserted after the write operation is completed, the PMOS transistors M1 and M6 are turned on and the light emitting element 6 emits light with the brightness level corresponding to the hold voltage held across the hold capacitor Cst”).
Regarding claim 4, Ogata further discloses wherein the scan cycle is a period obtained by dividing a period of a frame driven at a maximum driving frequency by M, wherein M is a positive integer (fig. 11 and 12 and [0083], multiple vertical sync periods are used for dimming in switching the frame rate).
Regarding claim 5, Ogata further discloses wherein the scan cycle when an input frequency of the input image data is a first frequency is shorter than the scan cycle when the input frequency is a second frequency different from the first frequency (Ogata: [0068], “the frame rate during vertical sync period #1 is a first frame rate, and the frame rate is switched to a second frame rate lower than the first frame rate by extending the lengths of vertical sync period #2 and the following vertical sync periods”).
Regarding claim 6, Ogata further discloses wherein the first frequency is greater than a first reference frequency and less than or equal to a second reference frequency, which is greater than the first reference frequency, and
wherein the second frequency is less than or equal to the first reference frequency, or greater than the second reference frequency (Ogata: [0068], “the frame rate during vertical sync period #1 is a first frame rate, and the frame rate is switched to a second frame rate lower than the first frame rate by extending the lengths of vertical sync period #2 and the following vertical sync periods”, where a first and second reference frequency could be any frequencies which meet the criteria).
Regarding claim 20, Ogata discloses a method of driving a display device (fig. 3), the method comprising:
starting a scan operation in synchronization with an input timing of input image data ([0033], “vertical sync periods in the display driver 2 are defined by the internal vertical sync signal VSYNC, and various timing controls in the display driver 2 are performed using the internal vertical sync signal VSYNC as a timing reference”);
performing the scan operation every a scan cycle in one frame ([0044], “the timing generator 16 asserts the internal vertical sync signal VSYNC upon the start of the reception of image data #1. In one or more embodiments, the assertion of the internal vertical sync signal VSYNC initiates vertical sync period #1 in the display driver 2. In one or more embodiments, image data #1 transmitted from the host 3 to the display driver 2 may contain a predetermined command. In this case, the data interface 11 of the display driver 2 may detect the start of the reception of image data #1 from the host 3 based on the predetermined command. The predetermined command may be disposed at the head of the image data #1”);
delaying a start of the scan operation of an (N+1)-th frame ([0053], “when the display driver 2 does not detect the start of reception of image data #3 until a predetermined period of time has elapsed after the transmission of the TE packet to the host 3, the display driver 2 changes or extends the length of vertical sync period #2 by extending the front porch period and waits for the host 3 to start transmitting image data #3. In The extended part of the front porch period is indicated as “extended FP” in FIG. 3. In one or more embodiments, the emission control signal continues to control the light emission of the pixels 4 by the emission control signal is continued in the extended FP. The extended FP may correspond to one or more control cycles of the emission control signal. In such embodiments with the extended FP, the timing at which the internal vertical sync signal VSYNC is next asserted is delayed from the default timing”).
While Ogata teaches delaying or extending the length of a vertical sync period from the default timing, it has been known to perform delay until the data is input thereto during the scan operation. In a similar field of endeavor display devices, Cho discloses delaying a start of the scan operation of an (N+1)-th frame until the scan operation of an N-th frame ends when the input image data of the (N+1)-th frame is input to a display panel driver of the display device during the scan operation of the N-th frame, wherein N is a positive integer ([0105], “Also, in the case in which the point in time at which rendering processing of the next frame is completed occurs during a vertical active period of the current frame during which a data enable signal and image data are being output as the point in time at which the vertical active period is commenced is delayed, a first′ vertical blank period Vblank1′ occurring immediately after completion of the current frame may be shorter than one sensing period TCMP. However, in this case, which is the case in which the frequency of the next frame approximates to the maximum frame frequency, the second′ vertical blank period Vblank2′ extended in the current frame does not exceed a maximum of one sensing period TCMP, compared to the second vertical blank period Vblank2, and therefore the vertical blank period Vblank of the next frame maintains a second time interval ITV2 (see FIG. 10), which is time from which a maximum of one sensing period TCMP is removed, or more, compared to an original first vertical blank period Vblank1”).
In view of the teachings of Ogata and Cho, it would have been obvious to one of ordinary skill in the art to perform the delay as taught by Cho, in the system of Ogata, for the purpose of solving a problem of a compensation cycle for a pixel is changed when a frame frequency is abruptly changed, whereby image spots or afterimage due to compensation delay may be incurred. In addition, abrupt fluctuation of luminance at the point in time of compensation update may be visible as flicker (Cho: [0004]).
While the combination of Ogata and Cho teaches a display driver and timing controller, it is known that a display driver can receive signals from a host processor. In a similar field of endeavor of display devices, Hatayama further discloses receiving input image data and an input control signal from a host processor ([0002], “A display driver that drives a display panel may be configured to receive image data from an external source (e.g., a host, a controller, a processor, or other devices configured to provide the image data)… The display driver may be further configured to, in a synchronous mode, receive image data and external synchronization (sync) control inputs (e.g., vertical sync packets and an external vertical sync signal) from the external source, generate the vertical sync signal based on the external sync control inputs, and update the display panel based on the received image data in synchronization with the generated vertical sync signal”).
In view of the teachings of Ogata, Cho and Hatayama it would have been obvious to one of ordinary skill in the art to include the external source of Hatayama to provide signals to the display driver of Ogata and Cho, for the purpose of using a known centralized external host to provide signals to a display driver to achieve consistent synchronization.
While the combination of Ogata, Cho and Hatayama discloses a timing generator which delays timing of the vertical sync signal, however it has been known to include a timing controller, a data driver, a gate driver and an emission driver. In a similar field of endeavor of display devices, Park discloses receiving input image data and an input control signal by a timing controller of a display panel driver of the display device from a host processor ([0012], “a timing controller configured to receive an input image data and timing signals from a host system, and to output a data timing control signal, a gate timing control signal, and a plurality of duty timing control signals”); a data signal by a data driver of the display panel driver of the display device ([0012], “a data driver configured to provide a data voltage corresponding to the input image data to one of the data lines connected to the pixel based on the data timing control signal”).
In view of the teachings of Ogata, Cho, Hatayama and Park, it would have been obvious to include a timing controller, a data driver, of Park, within the system of Ogata, Cho, and Hatayama, for the purpose of providing known structure within a display panel which has known advantages such as providing a fast response speed with high light-emitting efficiency and luminance (Park: [0005]).
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Ogata in view of Cheon et al. (US PGPub 2022/0051631) further in view of Hatayama and Park.
Regarding claim 11, Ogata discloses a display device (fig. 1A, display device 100) comprising:
a display panel (fig. 1A, display panel 1) including pixels (fig. 1A, pixels 4); and
a display panel driver (fig. 1A, display driver 2) which starts a scan operation in synchronization with an input timing of input image data ([0033], “vertical sync periods in the display driver 2 are defined by the internal vertical sync signal VSYNC, and various timing controls in the display driver 2 are performed using the internal vertical sync signal VSYNC as a timing reference”), performs the scan operation every a scan cycle in one frame ([0044], “the timing generator 16 asserts the internal vertical sync signal VSYNC upon the start of the reception of image data #1. In one or more embodiments, the assertion of the internal vertical sync signal VSYNC initiates vertical sync period #1 in the display driver 2. In one or more embodiments, image data #1 transmitted from the host 3 to the display driver 2 may contain a predetermined command. In this case, the data interface 11 of the display driver 2 may detect the start of the reception of image data #1 from the host 3 based on the predetermined command. The predetermined command may be disposed at the head of the image data #1”), and starts the scan operation of an (N+1)-th frame, wherein N is a positive integer ([0053], “when the display driver 2 does not detect the start of reception of image data #3 until a predetermined period of time has elapsed after the transmission of the TE packet to the host 3, the display driver 2 changes or extends the length of vertical sync period #2 by extending the front porch period and waits for the host 3 to start transmitting image data #3. In The extended part of the front porch period is indicated as “extended FP” in FIG. 3. In one or more embodiments, the emission control signal continues to control the light emission of the pixels 4 by the emission control signal is continued in the extended FP. The extended FP may correspond to one or more control cycles of the emission control signal. In such embodiments with the extended FP, the timing at which the internal vertical sync signal VSYNC is next asserted is delayed from the default timing”).
While Ogata teaches delaying the scanning WHEN there’s no image data signal received, it would have been obvious to one of ordinary skill in the art to include the limitation starts the scan operation of an (N+1)-th frame, when the input image data of the (N+1)-th frame is input during the scan operation of an N-th frame (Ogata infers/suggests that when there is image data signal promptly received, there would be NO delaying in the scanning operation in sync with the image data signal reception).
While Ogata suggests that there is no delaying in a scanning operation when an image signal is promptly received, it has been known to start the generating of a data signal when there is no delay. In a similar field of endeavor of display devices, Cheon discloses starts the operation by generating a data signal for the input image data of the (N+1_-th frame) ([0063], “a timing when the second frame data DD2 are input to the DDI may be delayed with respect to the seventh time t7 (i.e., a time when the vertical synchronization signal Vsync is generated). In this case, at the eighth time t8, because the second frame data DD2 are not input to a frame buffer, the DDI may output the previous first frame data DD1 during the second frame period FR2. Afterwards, the second frame data DD2 may be output during a period from the tenth time t10 to an eleventh time t11. Afterwards, at a twelfth time t12, the vertical synchronization signal Vsync may be generated. The remaining reference signs and times are described with reference to FIG. 3A, and thus, additional description will be omitted to avoid redundancy”).
In view of the teachings of Ogata and Cheon, it would have been obvious to one of ordinary skill in the art to include the operation of Cheon, in the system of Ogata, for the purpose of for the purpose of preventing the decrease of the image quality by providing an adaptive frame rate (Cheon: [0003]).
While the combination of Ogata and Cheon teaches a display driver and timing controller, it is known that a display driver can receive signals from a host processor. In a similar field of endeavor of display devices, Hatayama further discloses the display panel driver which receives input image data and an input control signal from a host processor ([0002], “A display driver that drives a display panel may be configured to receive image data from an external source (e.g., a host, a controller, a processor, or other devices configured to provide the image data)… The display driver may be further configured to, in a synchronous mode, receive image data and external synchronization (sync) control inputs (e.g., vertical sync packets and an external vertical sync signal) from the external source, generate the vertical sync signal based on the external sync control inputs, and update the display panel based on the received image data in synchronization with the generated vertical sync signal”).
In view of the teachings of Ogata, Cheon and Hatayama it would have been obvious to one of ordinary skill in the art to include the external source of Hatayama to provide signals to the display driver of Ogata and Cheon, for the purpose of using a known centralized external host to provide signals to a display driver to achieve consistent synchronization.
While the combination of Ogata, Cho and Hatayama discloses a timing generator which delays timing of the vertical sync signal, however it has been known to include a timing controller, a data driver, a gate driver and an emission driver. In a similar field of endeavor of display devices, Park discloses a display panel driver including a timing controller (fig. 1, timing controller 110), a gate driver (fig. 1, gate driver 104), a data driver (fig. 1, data driver 102) and an emission driver (fig. 1, em driver 106), an input timing of the input image data to the timing controller ([0012], “a timing controller configured to receive an input image data and timing signals from a host system, and to output a data timing control signal, a gate timing control signal, and a plurality of duty timing control signals”).
In view of the teachings of Ogata, Cho, Hatayama and Park, it would have been obvious to include a timing controller, a data driver, a gate driver and an emission driver, of Park, within the system of Ogata, Cho, and Hatayama, for the purpose of providing known structure within a display panel which has known advantages such as providing a fast response speed with high light-emitting efficiency and luminance (Park: [0005]).
Claims 12-15 are within the scope of claims 3-6 and are therefore interpreted and rejected based on similar reasoning.
Claims 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Ogata, Cho, Hatayama, and Park in view of Hussain et al. (US PGPub 2012/0147020)
Regarding claim 7, while the combination of Ogata, Cho, Hatayama and Park teaches a display scan operation, it has been known to perform both a display scan operation and a self-scan operation. In a similar field of endeavor of display devices, Hussain discloses wherein the scan operation first performed in the one frame is a display scan operation in which data voltages are written to the pixels, and
wherein the scan operation in the one frame excluding the display scan operation is a self-scan operation in which the data voltages are not written to the pixels ([0030], “The display data receiver 104 may include a static frame buffer 120 and a multiplexer (MUX) 122. The static frame buffer 120 is operatively coupled to the interface 116 and the MUX 122. In this example, the static frame buffer 120 is operative to store the static frame in the self-refresh mode. The MUX 122 is operative to switch between directly outputting dynamic frames received by the interface 116 in the normal mode and outputting the static frame stored in the static frame buffer 120 in the self-refresh mode”).
In view of the teachings of Ogata, Cho, Hatayama, Park and Hussain, it would have been obvious to one of ordinary skill in the art to include the self-scan of Hussain in the scanning operation of Ogata, Cho, Hatayama and Park, for the purpose of displaying a static image using a simple technique (Hussain: [0055]).
Regarding claim 8, the combination of Ogata, Cho, Hatayama, Park and Hussain further discloses wherein each of the pixels includes:
a first transistor (Ogata: fig. 1B, transistor M4) including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node (Ogata: fig. 1B, nodes surrounding transistor M4 which are not labeled in the figure);
a second transistor (Ogata: fig. 1B, transistor M2) including a control electrode which receives a write gate signal (Ogata: fig. 1B, scan line S[i-1]), a first electrode which receives the data voltages (Ogata: fig. 1B, data line D[j]), and a second electrode connected to the second node (Ogata: fig. 1B, node connecting M2 and M4 which is not labeled in the figure);
a third transistor (Ogata: fig. 1B, transistor M5) including a control electrode which receives the write gate signal (Ogata: fig. 1B, scan line S[i-1]), a first electrode connected to the third node (Ogata: fig. 1B, transistor M5 connected to M4 at a node that is not labeled in the figure), and a second electrode connected to the first node (Ogata: fig. 1B, connection between M5 and the gate of M4 which is not labeled in the figure);
a fourth transistor (Ogata: fig. 1B, transistor M3) including a control electrode which receives an initialization gate signal (Ogata: fig. 1B, scan line S[i-2]), a first electrode which receives an initialization voltage (Ogata: fig. 1B, INIT), and a second electrode connected to the first node (Ogata: fig. 1B, electrode connected to gate of M4 transistor, not labeled in the figure);
a fifth transistor (Ogata: fig. 1B, transistor M1) including a control electrode which receives an emission signal (Ogata: fig. 1B, EM[i]), a first electrode which receives a first power voltage (Ogata: fig. 1B, ELVDD), and a second electrode connected to the second node (Ogata: fig. 1B, transistor M1 connected to transistor M4 at a node which is not labeled in the figure);
a sixth transistor (Ogata: fig. 1B, transistor M6) including a control electrode which receives the emission signal (Ogata: fig. 1B, EM[i]), a first electrode connected to the third node (Ogata: fig. 1B, transistor M6 connected to transistor M4 at a node which is not labeled in the figure), and a second electrode connected to a fourth node (Ogata: fig. 1B, transistor M6 at a fourth node);
a seventh transistor (Ogata: fig. 1B, transistor M7) including a control electrode which receives a bias gate signal (Ogata: fig. 1B, scan line S[i]), a first electrode which receives the initialization voltage (Ogata: fig. 1B, INIT), and a second electrode connected to the fourth node (Ogata: fig. 1B, transistor M7 connected to transistor M6 at a node which is not labeled in the figure);
a storage capacitor (Ogata: fig. 1B, capacitor Cst) including a first electrode which receives the first power voltage (Ogata: fig. 1B, ELVDD) and a second electrode connected to the first node (Ogata: fig. 1B, capacitor Cst is connected to gate of transistor M4 at a node which is not labeled in the figure); and
a light emitting element (Ogata: fig. 1B, light emitting element 6) including a first electrode connected to the fourth node (Ogata: fig. 1B, light emitting element 6 connected to transistor M6 at a node which is not labeled in the figure) and a second electrode which receives a second power voltage (Ogata: fig. 1B, ELVSS).
Regarding claim 9, the combination of Ogata, Cho, Hatayama, Park and Hussain further discloses wherein the emission signal has an inactivation level in the scan operation and an activation level in a light emission operation (Ogata, [0024], “when a write operation is performed to program a drive voltage corresponding to a grayscale value into the pixel 4, the emission line EM[i] is deasserted, and the scan lines S[i-2], S[i-1] and S[i] are operated in a predetermined sequence with the data line D[j] supplied with the drive voltage, to write the drive voltage into the hold capacitor Cst. In one or more embodiments, the hold capacitor Cst is configured to hold a hold voltage corresponding to the drive voltage written into the pixel 4. In one or more embodiments, when the emission line EM[i] is deasserted, the PMOS transistors M1 and M6 are turned off and the light emitting element 6 stops emitting light. In one or more embodiments, when the emission line EM[i] is asserted after the write operation is completed, the PMOS transistors M1 and M6 are turned on and the light emitting element 6 emits light with the brightness level corresponding to the hold voltage held across the hold capacitor Cst”).
Regarding claim 10, the combination of Ogata, Cho, Hatayama, Park and Hussain further discloses wherein the write gate signal and the initialization gate signal have an activation level period in the display scan operation and an inactivation level in the self-scan operation, and
wherein the bias gate signal has an activation level period in the display scan operation and the self-scan operation (Ogata: [0025], “the scan driver circuitry 5 is configured to deassert the emission line EM[i] and operate the scan lines S[i-2], S[i-1] and S[i] in a predetermined sequence when a write operation is performed for pixels 4 in the ith row” and [0026], “the scan driver circuitry 5 is further configured to control light emission from rows of pixels 4 for which a write operation is not being performed, based on an emission control signal received from the display driver 2”).
Claims 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Ogata, Cheon, Hatayama and Park in view of Hussain et al. (US PGPub 2012/0147020).
Regarding claim 16, while Ogata, Cheon, Hatayama and Park teaches a display scan operation, it has been known to perform both a display scan operation and a self-scan operation. In a similar field of endeavor of display devices, Hussain discloses wherein the scan operation first performed in the one frame is a display scan operation in which data voltages are written to the pixels, and
wherein the scan operation in the one frame excluding the display scan operation is a self-scan operation in which the data voltages are not written to the pixels ([0030], “The display data receiver 104 may include a static frame buffer 120 and a multiplexer (MUX) 122. The static frame buffer 120 is operatively coupled to the interface 116 and the MUX 122. In this example, the static frame buffer 120 is operative to store the static frame in the self-refresh mode. The MUX 122 is operative to switch between directly outputting dynamic frames received by the interface 116 in the normal mode and outputting the static frame stored in the static frame buffer 120 in the self-refresh mode”).
In view of the teachings of Ogata, Cheon Hatayama, Park and Hussain, it would have been obvious to one of ordinary skill in the art to include the self-scan of Hussain in the scanning operation of Ogata, Cheon, Hatayama and Park, for the purpose of displaying a static image using a simple technique (Hussain: [0055]).
Regarding claim 17, the combination of Ogata, Cheon, Hatayama, Park and Hussain further discloses wherein each of the pixels includes:
a first transistor (Ogata: fig. 1B, transistor M4) including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node (Ogata: fig. 1B, nodes surrounding transistor M4 which are not labeled in the figure);
a second transistor (Ogata: fig. 1B, transistor M2) including a control electrode which receives a write gate signal (Ogata: fig. 1B, scan line S[i-1]), a first electrode which receives the data voltages (Ogata: fig. 1B, data line D[j]), and a second electrode connected to the second node (Ogata: fig. 1B, node connecting M2 and M4 which is not labeled in the figure);
a third transistor (Ogata: fig. 1B, transistor M5) including a control electrode which receives the write gate signal (Ogata: fig. 1B, scan line S[i-1]), a first electrode connected to the third node (Ogata: fig. 1B, transistor M5 connected to M4 at a node that is not labeled in the figure), and a second electrode connected to the first node (Ogata: fig. 1B, connection between M5 and the gate of M4 which is not labeled in the figure);
a fourth transistor (Ogata: fig. 1B, transistor M3) including a control electrode which receives an initialization gate signal (Ogata: fig. 1B, scan line S[i-2]), a first electrode which receives an initialization voltage (Ogata: fig. 1B, INIT), and a second electrode connected to the first node (Ogata: fig. 1B, electrode connected to gate of M4 transistor, not labeled in the figure);
a fifth transistor (Ogata: fig. 1B, transistor M1) including a control electrode which receives an emission signal (Ogata: fig. 1B, EM[i]), a first electrode which receives a first power voltage (Ogata: fig. 1B, ELVDD), and a second electrode connected to the second node (Ogata: fig. 1B, transistor M1 connected to transistor M4 at a node which is not labeled in the figure);
a sixth transistor (Ogata: fig. 1B, transistor M6) including a control electrode which receives the emission signal (Ogata: fig. 1B, EM[i]), a first electrode connected to the third node (Ogata: fig. 1B, transistor M6 connected to transistor M4 at a node which is not labeled in the figure), and a second electrode connected to a fourth node (Ogata: fig. 1B, transistor M6 at a fourth node);
a seventh transistor (Ogata: fig. 1B, transistor M7) including a control electrode which receives a bias gate signal (Ogata: fig. 1B, scan line S[i]), a first electrode which receives the initialization voltage (Ogata: fig. 1B, INIT), and a second electrode connected to the fourth node (Ogata: fig. 1B, transistor M7 connected to transistor M6 at a node which is not labeled in the figure);
a storage capacitor (Ogata: fig. 1B, capacitor Cst) including a first electrode which receives the first power voltage (Ogata: fig. 1B, ELVDD) and a second electrode connected to the first node (Ogata: fig. 1B, capacitor Cst is connected to gate of transistor M4 at a node which is not labeled in the figure); and
a light emitting element (Ogata: fig. 1B, light emitting element 6) including a first electrode connected to the fourth node (Ogata: fig. 1B, light emitting element 6 connected to transistor M6 at a node which is not labeled in the figure) and a second electrode which receives a second power voltage (Ogata: fig. 1B, ELVSS).
Regarding claim 18, the combination of Ogata, Cheon, Hatayama, Park and Hussain further discloses wherein the emission signal has an inactivation level in the scan operation and an activation level in a light emission operation (Ogata, [0024], “when a write operation is performed to program a drive voltage corresponding to a grayscale value into the pixel 4, the emission line EM[i] is deasserted, and the scan lines S[i-2], S[i-1] and S[i] are operated in a predetermined sequence with the data line D[j] supplied with the drive voltage, to write the drive voltage into the hold capacitor Cst. In one or more embodiments, the hold capacitor Cst is configured to hold a hold voltage corresponding to the drive voltage written into the pixel 4. In one or more embodiments, when the emission line EM[i] is deasserted, the PMOS transistors M1 and M6 are turned off and the light emitting element 6 stops emitting light. In one or more embodiments, when the emission line EM[i] is asserted after the write operation is completed, the PMOS transistors M1 and M6 are turned on and the light emitting element 6 emits light with the brightness level corresponding to the hold voltage held across the hold capacitor Cst”).
Regarding claim 19, the combination of Ogata, Cheon, Hatayama, Park and Hussain further discloses wherein the write gate signal and the initialization gate signal have an activation level period in the display scan operation and an inactivation level in the self-scan operation, and
wherein the bias gate signal has an activation level period in the display scan operation and the self-scan operation (Ogata: [0025], “the scan driver circuitry 5 is configured to deassert the emission line EM[i] and operate the scan lines S[i-2], S[i-1] and S[i] in a predetermined sequence when a write operation is performed for pixels 4 in the ith row” and [0026], “the scan driver circuitry 5 is further configured to control light emission from rows of pixels 4 for which a write operation is not being performed, based on an emission control signal received from the display driver 2”).
Response to Arguments
Applicant’s arguments with respect to claims 1, 11 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY J FRANK whose telephone number is (571)270-7255. The examiner can normally be reached Monday-Thursday 8AM-6PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin C Lee can be reached at (571)272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EJF/
/BENJAMIN C LEE/Supervisory Patent Examiner, Art Unit 2629