DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
The Amendments filed January 15th, 2026 in response to the Non-Final Office Action mailed 10/17/2025 are noted.
Applicant’s amendments to the claims are noted.
3. Claims 16-17 are newly-added; Claims 1-17 remain pending in the application.
4. Claims 1-17 have been fully considered in examination.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kato (U.S. PG Pub No US2015/0279872A1) (of record).
Regarding claim 1, Kato teaches a semiconductor element (100) fig. 9 [0162, 0213] comprising at least (refer to fig. 9):
a semiconductor layer (33) fig. 9 [0156] including a crystalline oxide semiconductor [0156] as a major component;
an electrode layer (38) [0151, 0160] laminated on the semiconductor layer (33); and
a conductive substrate (comprising 31 in 32 with 11 dielectric material and 34 and 36) [0153-0155, 0157] laminated on the electrode layer (38) with a conductive bonding layer (35S) fig. 9 [0158] (formed of bonded stack of metal positioned on 33) [0158] in between, the conductive substrate (comprising 31 in 32 with 11 dielectric material and 34 and 36) containing at least a first metal (Cu lower layer of 31 [0154]) selected from metals in group 11 in the periodic table (copper [0154]) and a second metal (Mo of upper layer of 31 [0154]) different from the first metal in coefficient of liner thermal expansion (different elements have inherent unique coefficients of thermal expansion),
wherein warpages of the semiconductor layer (33) and the electrode layer (38) are (assumed to be) equal to or less than 2 mm (because Kato does not disclose any warpage in any layers, Kato essentially discloses no warpage; warpage is assumed to be essentially 0mm, which reads on warpages less than 2mm --- see further discussion in Response-to-Arguments section).
With respect to the underlined “laminated” limitation(s) above, the term ‘laminated’ is considered as a product-by-process phrase which does not impart any significant structural difference to the finished product. Therefore, for the purposes of Examination, the limitation(s) “laminated” has been considered to mean that the final structure of any lamination step only requires the layers or structures to be “stacked on” or “on.” As such, the structure required by this claim language is the electrode layer stacked on the semiconductor layer, as disclosed in Kato. (See MPEP 2113, I.)
Regarding claims 2-4, Kato teaches a semiconductor element (100) fig. 9 [0162, 0213] according to claim 1. Kato also teaches wherein the first, group 11 metal (Cu lower layer of 31 [0154]) is copper [0154] and the second, group 6 metal (Mo of upper layer of 31 [0154]) is molybdenum [0154].
Regarding claim 5, Kato teaches a semiconductor element (100) fig. 9 [0162, 0213] according to claim 1. Kato also teaches wherein the (comprising 31 in 32 with 11 dielectric material and 34 and 36) [0153-0155, 0157] has a multilayer structure (comprises multilayer 31 [0154]) in which at least one layer including the first metal (Cu lower layer of 31 [0154]) and at least one layer including the second metal a second metal (Mo of upper layer of 31 [0154]) arestacked).
Regarding claim 6, Kato teaches a semiconductor element (100) fig. 9 [0162, 0213] according to claim 5. Kato also teaches wherein a bottom layer (Cu lower layer of 31 [0154]) of the multilayer structure (11) includes the first metal (copper) [0154].
Regarding claim 7, Kato teaches a semiconductor element (100) fig. 9 [0162, 0213] according to claim 1. Kato also teaches wherein the crystalline oxide semiconductor (33) fig. 9 [0156] includes at least one metal selected from aluminum, indium, and gallium [0156] (IGZO).
Regarding claim 8, Kato teaches a semiconductor element (100) fig. 9 [0162, 0213] according to claim 1. Kato also teaches wherein the crystalline oxide semiconductor (33) fig. 9 [0156] includes at least gallium [0156] (IGZO).
Regarding claim 9, Kato teaches a semiconductor element (100) fig. 9 [0162, 0213] according to claim 1. Kato also teaches further comprising another electrode layer (CAN) fig. 8 [0151] on a surface facing a surface of the semiconductor layer (33) fig. 9 [0156] on (atop) which the electrode layer is stacked).
Regarding claim 10, Kato teaches a semiconductor element (100) fig. 9 [0162, 0213] according to claim 1. Kato also teaches wherein the semiconductor element is (comprises) a power device (gate, light emission layer(s) powered by applied voltage [0154, 0180]).
Regarding claim 16, Kato teaches a semiconductor element (100) fig. 9 [0162, 0213] according to claim 1. Kato also teaches wherein the conductive substrate (comprising 31 in 32 with 11 dielectric material and 34 and 36) [0153-0155, 0157] is laminated (stacked) on the (bottom of) electrode layer (38) [0151, 0160] directly (36 in direct contact with 38).
With respect to the underlined “laminated” limitation(s) above, the term ‘laminated’ is considered as a product-by-process phrase which does not impart any significant structural difference to the finished product. Therefore, for the purposes of Examination, the limitation(s) “laminated” has been considered to mean that the final structure of any lamination step only requires the layers or structures to be “stacked on” or “on.” As such, the structure required by this claim language is the electrode layer stacked on the semiconductor layer, as disclosed in Kato. (See MPEP 2113, I.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kato (U.S. PG Pub No US2015/0279872A1) (of record), as applied in claim 1 above, in view of Joshi (U.S. PG Pub No US2019/0287885A1) (of record).
Regarding claim 11, Kato teaches a semiconductor device (comprising 100) fig. 9 [0162, 0213], wherein the semiconductor element (100) is the semiconductor element (100) according to claim 1.
However, Kato does not explicitly disclose a semiconductor device comprising at least a semiconductor element joined to a lead frame, a circuit board, or a heat dissipation substrate by means of a joint member.
Joshi teaches a semiconductor device (100) figs. 1-2 [0021] comprising at least a semiconductor element (131/132/150) fig. 1 [0026-0028] joined to a heat dissipation substrate (ceramic 120) [0019, -0021] by a joint member (122 adjoining 120 with overlying layers / semiconductor components [0022, 0025]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor element of Kato to be incorporated with / within the power converter configuration [0019-0026] of Joshi in order to improve in order to enable use of the semiconductor element with high frequency power supplies [0021] as well as improve heat dissipation [0019] through use of a thermally conductive [0021] ceramic substrate [0019-0021], as taught by Joshi.
Regarding claim 12, Kato in view of Joshi (with reference to Joshi) teaches a power converter (100) fig. 1 [0021, 0025-0026] comprising the semiconductor device (131/132) fig. 1 [0026-0028] according to claim 11.
Regarding claim 13, Kato in view of Joshi (with reference to Joshi) teaches a control system (control transistor of power module 100) [0025] comprising the semiconductor device (131) fig. 1 [0026-0028] according to claim 11.
Claims 14-15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kato (U.S. PG Pub No US2015/0279872A1) (of record) in view of Ohtani (U.S. Patent No 6,259,138) (of record).
Regarding claim 14, Kato teaches a semiconductor element (100) fig. 9 [0162, 0213] comprising at least (refer to fig. 9):
a semiconductor layer (33) fig. 9 [0156] including a crystalline oxide semiconductor [0156] as a major component;
an electrode layer (38) [0151, 0160] laminated on the semiconductor layer (33); and
a conductive substrate (comprising 31 in 32 with 11 dielectric material and 34 and 36) [0153-0155, 0157] laminated on the electrode layer (38) with a conductive bonding layer (35S) fig. 9 [0158] (formed of bonded stack of metal positioned on 33) [0158] in between, the conductive substrate (comprising 31 in 32 with 11 dielectric material and 34 and 36) [0153-0155, 0157] containing at least a first metal (Cu lower layer of 31 [0154]) selected from metals in group 11 in the periodic table (copper [0154]) and a second metal (Mo of upper layer of 31 [0154]) different from the first metal in coefficient of liner thermal expansion (different elements have inherent unique coefficients of thermal expansion).
With respect to the underlined “laminated” limitation(s) above, the term ‘laminated’ is considered as a product-by-process phrase which does not impart any significant structural difference to the finished product. Therefore, for the purposes of Examination, the limitation(s) “laminated” has been considered to mean that the final structure of any lamination step only requires the layers or structures to be “stacked on” or “on.” As such, the structure required by this claim language is the electrode layer stacked on the semiconductor layer, as disclosed in Kato. (See MPEP 2113, I.)
However, Kato does not explicitly depict wherein the first metal and the second metal are in direct contact with each other (distinct first and second metals of 31 not explicitly shown).
Ohtani teaches a semiconductor element [see fig. 1, title] wherein the first metal (105b/205b) fig. 1D [col 5, line 57 - col 6, line 30] and the second metal (105a/205a or 105c/205c) fig. 1D [col 5, line 57 - col 6, line 30] are in direct contact with each other (distinct first and second metal layers among 105a-c explicitly shown for gate electrode [col 5, line 57 - col 6, line 30]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor structure of Ohtani such that the gate electrode is explicitly composed of at least two distinct and vertically-stacked metal layers [col 5, line 57 - col 6, line 30] in order to improve the heat resistance, diffusion-blocking, and short-circuiting resistance [col 6, lines 15-25] of the multilayered gate electrode [col 5, line 57 - col 6, line 30], as taught by Ohtani.
Regarding claim 15, Kato teaches the semiconductor element (comprising 100) fig. 9 [0162, 0213] according to claim 1.
However, Kato does not explicitly depict wherein the first metal and the second metal are in direct contact with each other (distinct first and second metals of 31 not explicitly shown).
Ohtani teaches a semiconductor element [see fig. 1, title] wherein the first metal (105b/205b) fig. 1D [col 5, line 57 - col 6, line 30] and the second metal (105a/205a or 105c/205c) fig. 1D [col 5, line 57 - col 6, line 30] are in direct contact with each other (distinct first and second metal layers among 105a-c explicitly shown for gate electrode [col 5, line 57 - col 6, line 30]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor structure of Ohtani such that the gate electrode is explicitly composed of at least two distinct and vertically-stacked metal layers [col 5, line 57 - col 6, line 30] in order to improve the heat resistance, diffusion-blocking, and short-circuiting resistance [col 6, lines 15-25] of the multilayered gate electrode [col 5, line 57 - col 6, line 30], as taught by Ohtani.
Regarding claim 17, Kato teaches a semiconductor element (100) fig. 9 [0162, 0213] according to claim 14. Kato also teaches wherein the conductive substrate (comprising 31 in 32 with 11 dielectric material and 34 and 36) [0153-0155, 0157] is laminated on the (bottom of) electrode layer (38) [0151, 0160] directly (36 in direct contact with 38).
With respect to the underlined “laminated” limitation(s) above, the term ‘laminated’ is considered as a product-by-process phrase which does not impart any significant structural difference to the finished product. Therefore, for the purposes of Examination, the limitation(s) “laminated” has been considered to mean that the final structure of any lamination step only requires the layers or structures to be “stacked on” or “on.” As such, the structure required by this claim language is the electrode layer stacked on the semiconductor layer, as disclosed in Kato. (See MPEP 2113, I.)
Response to Arguments
Applicant’s arguments filed 01/15/2026 have been fully considered but they are not persuasive.
Applicant’s arguments with respect to claims 1 and 14 have been fully considered but are rendered largely moot by a reinterpretation of the “another layer” amended to be a “conductive bonding layer” to be element (35S) fig. 9 [0158 Kato] of Kato, which more closely aligns with amended requirements of said layer. 35S is a stack of bonded-low-resistance-metals bound to the upper surface of channel 33 [0157-0158]. It is noted that element 35S is not used elsewhere in the rejection, hence this raises no contradiction with the rejection of record.
Further, the conductive substrate (comprising 31 in 32 with 11 dielectric material and 34 and 36) [0153-0155, 0157] has been reinterpreted to further comprise element 36 of Kato. The conductive bonding layer 35S of Kato is therefore positioned between portions of the conductive substrate (comprising 31 in 32 with 11 dielectric material and 34 and 36) [0153-0155, 0157] and the electrode layer 38 of Kato (see fig. 9 of Kato). Further, with respect to newly-added claims 16 and 17, the conductive substrate (comprising 36) [0153-0155, 0157] is directly on the bottom of electrode 38.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Remaining references made of record on the PTO-892 form are considered relevant to the present disclosure because they all feature semiconductor devices with at least some of the claimed features.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 01/26/2026
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892