DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/19/2026 has been entered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-10, 16, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kato (U.S. PG Pub No US2015/0279872A1) (of record) modified by Ikeda (U.S. PG Pub No US2020/0185420A1).
Regarding claim 1, Kato teaches a semiconductor element (100) fig. 9 [0162, 0213] comprising at least (refer to fig. 9):
a semiconductor layer (33) fig. 9 [0156] including a crystalline oxide semiconductor [0156] as a major component;
an electrode layer (upper IGZO layer of trilayer 31) [0151, 0154] (electrode layer 31 may represent a trilayer stack consisting of Cu/Mo/IGZO layers stacked from bottom to top [0154]) laminated on (stacked on the bottom of) the semiconductor layer (33); and
a conductive substrate (comprising 31 in 32 with 11 dielectric material and 34 and 36) [0153-0155, 0157] including a first metal (Cu lower layer of 31 [0154]) selected from metals in group 11 in the periodic table (copper [0154]) and a second metal (Mo of middle barrier layer of 31 [0154]) having a coefficient of linear thermal expansion different from that of the first metal (different elements have inherent unique coefficients of thermal expansion),
the second metal (Mo of middle barrier layer of 31 [0154]) is laminated on (stacked on) the electrode layer (upper IGZO layer of trilayer 31) [0151, 0154] directly (Mo middle layer of trilayer 31 stacked directly on bottom of upper IGZO layer of 31) [0154],
the first metal (lower Cu layer [0154]) is laminated on (stacked directly on the bottom of) the second metal (Mo middle layer of trilayer 31) [0154], and
the second metal (Mo middle layer of trilayer 31) is/are positioned closer to (because no intervening layers are disclosed, assumed to be separated by 0nm from) the electrode layer (upper IGZO layer of trilayer 31) [0151, 0154] than to the semiconductor layer (33) (33 is vertically separated by at least a non-zero thickness [0155, 0195] of gate insulating film 32 from middle layer of 31).
With respect to the underlined “laminated” limitation(s) above, the term ‘laminated’ is considered as a product-by-process phrase which does not impart any significant structural difference to the finished product. Therefore, for the purposes of Examination, the limitation(s) “laminated” has been considered to mean that the final structure of any lamination step only requires the layers or structures to be “stacked on” or “on.” As such, the structure required by this claim language is the electrode layer stacked on the semiconductor layer, as disclosed in Kato. (See MPEP 2113, I.)
However, Kato does not explicitly disclose both the first metal (lower Cu layer of 31) [0154] and the second metal (middle Mo layer of 31) [0154] are positioned to the electrode layer (upper IGZO layer of 31) [0154] than to the semiconductor layer (33) fig. 9 [0156] (insufficient size information about individual layers of 31 [0154], particularly the middle metal barrier layer [0154], to conclude that lower metal layer of 31 is vertically closer to upper conductive oxide layer of 31 than IGZO semiconductor layer 33 [0155], which is separated from electrode layer 31 by at least a thickness of gate insulating film 32 [0155, 0195] therebetween).
Ikeda teaches a semiconductor element [see fig. 35A2, 0473-0474] comprising both the first metal (upper metal layer of 802) fig. 35A2 [0480] and the second metal (middle metal layer of 802) fig. 35A2 [0480] are positioned to the electrode layer (lower IGZO layer of 802) fig. 35A2 [0480] (upper metal layer of 802 is separated by a thickness of middle metal layer = 15 nm [0480] from lower IGZO layer of trilayer stack defining gate electrode 802; middle metal layer assumed to have 0 nm separation with lower IGZO layer of trilayer 802 stack [0480] since intervening layers not disclosed) than to the semiconductor layer (IGZO semiconductor layer 801) fig. 35A2 [0156] (801 separated from 802 by at least a thickness of gate insulating film 804 = 150 nm [0479], which is greater than a separation of 15 nm [0480] between the upper metal layer of trilayer 802 [0480] and the lower IGZO layer of 802 [0480]; therefore, the first metal and second metal layer of the trilayer gate electrode 802 [0480] are at least 150 – 15 = 135 nm closer to the IGZO electrode layer of trilayer gate electrode 802 than to IGZO semiconductor layer 801 [0480] in a vertical, thickness direction [0479-0480 Ikeda]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the thicknesses of the trilayer, IGZO/metal/metal gate electrode of Kato according to the thicknesses prescribed by [0480] of Ikeda, such that a thickness of the middle barrier metal layer [0480] is less than a thickness of the gate insulating film [0479] – and the electrode layers are closer to each other than to the IGZO semiconductor channel layer [0478-0480] – in order to optimize the size and resultant current-voltage performance characteristics [0473, 0484] of the trilayer gate electrode [0480] and gate insulating film [0479] of the transistor [0473-0474, 0484] according to art recognized parameters [0478-0480], as taught by Ikeda.
Regarding claims 2-4, Kato in view of Ikeda teaches the semiconductor element (100) fig. 9 [0162, 0213] according to claim 1. Kato also teaches wherein the first, group 11 metal (Cu lower layer of 31 [0154]) is copper [0154] and the second, group 6 metal (Mo of upper layer of 31 [0154]) is molybdenum [0154].
Regarding claim 5, Kato in view of Ikeda teaches the semiconductor element (100) fig. 9 [0162, 0213] according to claim 1. Kato also teaches wherein the (comprising 31 in 32 with 11 dielectric material and 34 and 36) [0153-0155, 0157] has a multilayer structure (comprises multilayer 31 [0154]) in which at least one layer including the first metal (Cu lower layer of 31 [0154]) and at least one layer including the second metal a second metal (Mo of upper layer of 31 [0154]) arestacked).
Regarding claim 6 Kato in view of Ikeda teaches the semiconductor element (100) fig. 9 [0162, 0213] according to claim 5. Kato also teaches wherein a bottom layer (Cu lower layer of 31 [0154]) of the multilayer structure (31) includes the first metal (copper) [0154].
Regarding claim 7, Kato in view of Ikeda teaches the semiconductor element (100) fig. 9 [0162, 0213] according to claim 1. Kato also teaches wherein the crystalline oxide semiconductor (33) fig. 9 [0156] includes at least one metal selected from aluminum, indium, and gallium [0156] (IGZO).
Regarding claim 8, Kato in view of Ikeda teaches the semiconductor element (100) fig. 9 [0162, 0213] according to claim 1. Kato also teaches wherein the crystalline oxide semiconductor (33) fig. 9 [0156] includes at least gallium [0156] (IGZO).
Regarding claim 9, Kato in view of Ikeda teaches the semiconductor element (100) fig. 9 [0162, 0213] according to claim 1. Kato also teaches further comprising another electrode layer (BE1) fig. 9 [0151] on a surface facing a (facing toward a bottom) surface of the semiconductor layer (33) fig. 9 [0156] on which the electrode layer (uppermost, IGZO layer of 31 trilayer) fig. 9 [0154] is stacked) (31 stacked on / supported by bottom surface of 33).
Regarding claim 10, Kato in view of Ikeda teaches the semiconductor element (100) fig. 9 [0162, 0213] according to claim 1. Kato also teaches wherein the semiconductor element is (comprises) a power device (gate, light emission layer(s) powered by applied voltage [0154, 0180]).
Regarding claim 16, Kato in view of Ikeda teaches the semiconductor element (100) fig. 9 [0162, 0213] according to claim 1. Kato also teaches wherein the conductive substrate (comprising 32 with 11 dielectric material and 34 and 36) [0153-0155, 0157] is laminated (stacked) on the (top of) electrode layer (uppermost layer of trilayer gate electrode 31) fig. 9 [0154] directly (32 directly stacked on top of uppermost layer of 31).
Regarding claim 18, Kato in view of Ikeda teaches the semiconductor element (100) fig. 9 [0162, 0213] according to claim 1. Kato also teaches wherein warpages of the semiconductor layer (33) and the electrode layer (uppermost, IGZO layer of 31 trilayer) fig. 9 [0154] are (assumed to be) equal to or less than 2 mm (because Kato does not disclose any warpage in any layers, Kato essentially discloses no warpage; warpage is assumed to be essentially 0mm, which reads on warpages less than 2mm).
Regarding claim 19, Kato in view of Ikeda teaches the semiconductor element (100) fig. 9 [0162, 0213] according to claim 1. Kato also teaches wherein the semiconductor layer (33) fig. 9 [0156], the electrode layer (upper IGZO layer of trilayer 31) fig. 9 [0151, 0154] (electrode layer 31 may represent a trilayer stack consisting of IGZO/Mo/Cu layers stacked from top to bottom [0154]), the one of the second metal (Mo layer of trilayer 31) fig. 9 [0154], and the another of the first metal (Cu layer of trilayer 31) fig. 9 [0154] are arranged in this order in a laminating (stacking) direction thereof (stacking direction defined as a vertical, downward direction – from top to bottom, semiconductor layer 33 overlaps IGZO, electrode layer of 31 overlaps Mo barrier layer of 31 overlaps Cu metal layer of 31 [0154]).
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kato (U.S. PG Pub No US2015/0279872A1) (of record) modified by Ikeda (U.S. PG Pub No US2020/0185420A1), as applied in claim 1 above, and further in view of Joshi (U.S. PG Pub No US2019/0287885A1) (of record).
Regarding claim 11, Kato in view of Ikeda teaches the semiconductor device (comprising 100) fig. 9 [0162, 0213], wherein the semiconductor element (100) is the semiconductor element (100) according to claim 1.
However, Kato does not explicitly disclose a semiconductor device comprising at least a semiconductor element joined to a lead frame, a circuit board, or a heat dissipation substrate by means of a joint member.
Joshi teaches a semiconductor device (100) figs. 1-2 [0021] comprising at least a semiconductor element (131/132/150) fig. 1 [0026-0028] joined to a heat dissipation substrate (ceramic 120) [0019, -0021] by a joint member (122 adjoining 120 with overlying layers / semiconductor components [0022, 0025]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor element of Kato to be incorporated with / within the power converter configuration [0019-0026] of Joshi in order to improve in order to enable use of the semiconductor element with high frequency power supplies [0021] as well as improve heat dissipation [0019] through use of a thermally conductive [0021] ceramic substrate [0019-0021], as taught by Joshi.
Regarding claim 12, Kato in view of Ikeda and Joshi (with reference to Joshi) teaches a power converter (100) fig. 1 [0021, 0025-0026] comprising the semiconductor device (131/132) fig. 1 [0026-0028] according to claim 11.
Regarding claim 13, Kato in view of Ikeda and Joshi (with reference to Joshi) teaches a control system (control transistor of power module 100) [0025] comprising the semiconductor device (131) fig. 1 [0026-0028] according to claim 11.
Claims 14-15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kato (U.S. PG Pub No US2015/0279872A1) (of record) modified by Ikeda (U.S. PG Pub No US2020/0185420A1), as applied in claim 1 above, and further in view of Ohtani (U.S. Patent No 6,259,138) (of record).
Regarding claim 14, Kato in view of Ikeda teaches the semiconductor element (100) fig. 9 [0162, 0213] according to claim 1. However, Kato does not explicitly depict the first metal (lower Cu layer of 31 trilayer) fig. 9 [0154] and the second metal (middle, Mo barrier layer of 31 trilayer) fig. 9 [0154] are in direct contact with each other (distinct first and second metals of 31 not explicitly shown).
Ohtani teaches a semiconductor element [see fig. 1, title] wherein the first metal (105b/205b) fig. 1D [col 5, line 57 - col 6, line 30] and the second metal (105a/205a or 105c/205c) fig. 1D [col 5, line 57 - col 6, line 30] are in direct contact with each other (distinct first and second metal layers among 105a-c explicitly shown for gate electrode [col 5, line 57 - col 6, line 30]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor structure of Ohtani such that the gate electrode is explicitly composed of at least two distinct and vertically-stacked metal layers [col 5, line 57 - col 6, line 30] in order to improve the heat resistance, diffusion-blocking, and short-circuiting resistance [col 6, lines 15-25] of the multilayered gate electrode [col 5, line 57 - col 6, line 30], as taught by Ohtani.
Regarding claim 15, Kato in view of Ikeda teaches the semiconductor element (100) fig. 9 [0162, 0213] according to claim 1. However, Kato does not explicitly depict wherein the first metal (lower Cu layer of 31 trilayer) fig. 9 [0154] and the second metal (middle, Mo barrier layer of 31 trilayer) fig. 9 [0154] are in direct contact with each other (distinct first and second metals of 31 not explicitly shown).
Ohtani teaches a semiconductor element [see fig. 1, title] wherein the first metal (105b/205b) fig. 1D [col 5, line 57 - col 6, line 30] and the second metal (105a/205a or 105c/205c) fig. 1D [col 5, line 57 - col 6, line 30] are in direct contact with each other (distinct first and second metal layers among 105a-c explicitly shown for gate electrode [col 5, line 57 - col 6, line 30]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor structure of Ohtani such that the gate electrode is explicitly composed of at least two distinct and vertically-stacked metal layers [col 5, line 57 - col 6, line 30] in order to improve the heat resistance, diffusion-blocking, and short-circuiting resistance [col 6, lines 15-25] of the multilayered gate electrode [col 5, line 57 - col 6, line 30], as taught by Ohtani.
Regarding claim 17, Kato in view of Ikeda and Ohtani teaches the semiconductor element (100) fig. 9 [0162, 0213] according to claim 14. Kato also teaches wherein the conductive substrate (comprising 32 with 11 dielectric material and 34 and 36) [0153-0155, 0157] is laminated (stacked) on the (top of) electrode layer (uppermost layer of trilayer gate electrode 31) fig. 9 [0154] directly (32 directly stacked on top of uppermost layer of 31).
With respect to the underlined “laminated” limitation(s) above, the term ‘laminated’ is considered as a product-by-process phrase which does not impart any significant structural difference to the finished product. Therefore, for the purposes of Examination, the limitation(s) “laminated” has been considered to mean that the final structure of any lamination step only requires the layers or structures to be “stacked on” or “on.” As such, the structure required by this claim language is the electrode layer stacked on the semiconductor layer, as disclosed in Kato. (See MPEP 2113, I.)
With respect to the underlined “laminated” limitation(s) above, the term ‘laminated’ is considered as a product-by-process phrase which does not impart any significant structural difference to the finished product. Therefore, for the purposes of Examination, the limitation(s) “laminated” has been considered to mean that the final structure of any lamination step only requires the layers or structures to be “stacked on” or “on.” As such, the structure required by this claim language is the electrode layer stacked on the semiconductor layer, as disclosed in Kato. (See MPEP 2113, I.)
Response to Arguments
Applicant’s arguments, see pages 1-2, filed 05/19/2026, with respect to the rejection(s) of claim(s) 1 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Ikeda (U.S. PG Pub No US2020/0185420A1) under 35 U.S.C. 103.
Further, it is emphasized that specific arguments with respect to the claimed “electrode layer” are rendered largely moot by a reinterpretation of the “electrode layer” to be “IGZO layer of trilayer gate electrode 31” [see fig. 9, 0151, 0154 Kato]. [0154] of Kato establishes, with sufficient detail for one of ordinary skill in the art, that element 31 in fig. 9 of Kato may represent a trilayer gate electrode stack consisting of Cu/Mo/IGZO layers stacked [0154], with the lower Cu layer of 31 corresponding to the presently claimed “first metal”, the middle Mo “interposed” barrier layer of 31 corresponding to the claimed “second metal”, and the upper IGZO layer of 31 corresponding to the claimed “electrode layer”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Newly-added Yamazaki (U.S. PG Pub No US2019/0035936A1) teaches another example of a transistor structure, comprising an IGZO channel layer, shown to scale with pertinent size information disclosed. See, for example, fig. 40 of Yamazaki reproduced below.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 05/22/2026
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