Prosecution Insights
Last updated: April 19, 2026
Application No. 18/106,209

CMOS Image Sensor and Method for Forming the Same

Final Rejection §112
Filed
Feb 06, 2023
Examiner
PARENDO, KEVIN A
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hua Hong Semiconductor (Wuxi) Limited
OA Round
2 (Final)
72%
Grant Probability
Favorable
3-4
OA Rounds
2y 11m
To Grant
84%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allow Rate
532 granted / 742 resolved
+3.7% vs TC avg
Moderate +12% lift
Without
With
+12.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
43 currently pending
Career history
785
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
47.6%
+7.6% vs TC avg
§102
20.9%
-19.1% vs TC avg
§112
27.0%
-13.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 742 resolved cases

Office Action

§112
DETAILED ACTION Election/Restrictions A restriction requirement was mailed on 7/17/25. Applicant's election with traverse of Group II in the reply filed on 9/15/25 was previously acknowledged in the 11/18/25 office action, and the restriction requirement was made final. Claim 7 has been amended by Applicant on 2/18/26 to require specific method limitations, instead of merely requiring “forming…” elements. Specifically, claim 7 requires methods such as “etching… until the one of the plurality of photosensitive doped layers is exposed…”, “the active areas and one of the plurality of isolation structures are exposed by the gate trench”, “wherein the opening exposes a part of the top surface of the active areas, and implanting first ions into the opening to form the source/drain layer”. Thus, claim 1, which is a product-by-process claim (see analysis below), is a device that results in distinctive structural characteristics, such that claims 1-6 are not currently linking claims. Claims 1-6 are thus hereby withdrawn. Because the restriction requirement was traversed, claims 1-6 will be rejected under 35 USC 112 for compact prosecution. Claim Interpretation The applicant is hereby notified that the examiner is treating claims 1-6 as "product-by-process” claims. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” (See In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), and also see MPEP 2113). The structure implied by the process steps should be considered when assessing the patentability of product-by-process claims over the prior art, especially where the product can only be defined by the process steps by which the product is made, or where the manufacturing process steps would be expected to impart distinctive structural characteristics to the final product. (See, e.g., In re Garnero, 412 F.2d 276, 279, 162 USPQ 221, 223 (CCPA 1979) and also see MPEP 2113). Claim 1 recites: “A CMOS image sensor formed by the method for forming a CMOS image sensor according to claim 7, comprising: a substrate, comprising a plurality of pixel regions which are mutually discrete; a photosensitive doped layer which is disposed in one of the plurality of pixel regions; and a switching device which is disposed on the photosensitive doped layer.” The device of claim 1 requires the distinct structural characteristics resultant from the process “formed by the method for forming a CMOS image sensor according to claim 7”. As such, claim 1 requires every one of the following distinct structural characteristics: “A CMOS image sensor, comprising: a substrate structure and a plurality of photosensitive doped layers, wherein the substrate structure comprises a plurality of pixel regions which are mutually discrete, and one of the plurality of photosensitive doped layers is disposed in one of the plurality of pixel regions; and a switching device on the one of the plurality of photosensitive doped layers; wherein the substrate structure comprises: a substrate, an initial photosensitive doped layer disposed on the substrate, and an initial well doped layer disposed on the initial photosensitive doped layer; wherein a plurality of isolation structures are in the substrate structure, each of the plurality of isolation structures penetrates the initial photosensitive doped layer and is respectively disposed between adjacent pixel regions to form the plurality of mutually discrete photosensitive doped layers, and each of the plurality of isolation structures penetrates the initial well doped layer to form a plurality of well doped layers which are mutually discrete; wherein the switching device comprises an active area disposed on a part of the photosensitive doped layer and a gate disposed above and surrounding the active area and above a part of the photosensitive doped layer, a source/drain layer is formed at the top of the active area, and the gate is provided with an opening which exposes a part of the source/drain layer. wherein: one of the plurality of well doped layers formed on the one of the plurality of photosensitive doped layers is processed by processes such as etching or equivalent methods, such that the one of the plurality of photosensitive doped layers is exposed, thus forming a gate trench, wherein a part of the well doped layer constitutes the active area, and the active area and one of the plurality of isolation structures are exposed by the gate trench; the gate is in the gate trench and above the active area and has an opening in the gate, wherein the opening exposes a part of the top surface of the active area; and the source/drain layer exposed by the opening comprise first ions. Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. (See In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983)). Also note the use of 102/103 rejections for product-by-process claims has been approved by the courts. (See In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972), and also see MPEP 2113). Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim(s) 1-6 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant) regards as the invention. Claim 1 recites: “A CMOS image sensor formed by the method for forming a CMOS image sensor according to claim 7, comprising: a substrate, comprising a plurality of pixel regions which are mutually discrete; a photosensitive doped layer which is disposed in one of the plurality of pixel regions; and a switching device which is disposed on the photosensitive doped layer.” The metes and bounds of the claimed limitation can not be determined for the following reasons: After the product-by-process evaluation (see above), the scope of claim 1 is: “A CMOS image sensor comprising: a substrate structure and a plurality of photosensitive doped layers, wherein the substrate structure comprises a plurality of pixel regions which are mutually discrete, and one of the plurality of photosensitive doped layers is disposed in one of the plurality of pixel regions; and a switching device on the one of the plurality of photosensitive doped layers; wherein the substrate structure comprises: a substrate, an initial photosensitive doped layer disposed on the substrate, and an initial well doped layer disposed on the initial photosensitive doped layer; wherein a plurality of isolation structures are in the substrate structure, each of the plurality of isolation structures penetrates the initial photosensitive doped layer and is respectively disposed between adjacent pixel regions to form the plurality of mutually discrete photosensitive doped layers, and each of the plurality of isolation structures penetrates the initial well doped layer to form a plurality of well doped layers which are mutually discrete; wherein the switching device comprises an active area disposed on a part of the photosensitive doped layer and a gate disposed above and surrounding the active area and above a part of the photosensitive doped layer, a source/drain layer is formed at the top of the active area, and the gate is provided with an opening which exposes a part of the source/drain layer. wherein: one of the plurality of well doped layers formed on the one of the plurality of photosensitive doped layers is processed by processes such as etching or equivalent methods, such that the one of the plurality of photosensitive doped layers is exposed, thus forming a gate trench, wherein a part of the well doped layer constitutes the active area, and the active area and one of the plurality of isolation structures are exposed by the gate trench; the gate is in the gate trench and above the active area and has an opening in the gate, wherein the opening exposes a part of the top surface of the active area; and the source/drain layer exposed by the opening comprise first ions. comprising: a substrate, comprising a plurality of pixel regions which are mutually discrete; a photosensitive doped layer which is disposed in one of the plurality of pixel regions; and a switching device which is disposed on the photosensitive doped layer.” The limitations of the body of claim 1, i.e. “a substrate”, “a plurality of pixel regions…”, “a photosensistive doped layer…”, and “a switching device…”, all lack proper antecedent basis. Each has already been recited in claim 7, and thus since each refers back to claim 7 with “a” instead of “the”, each lacks proper antecedent basis. For each, it thus raises the issue as whether the instance recited in claim 1 refers to the same element as is recited in claim 7, or if it could be a different (e.g. “second”) such element. Furthermore, because the limitations of the body of claim 1 are inherent due to the resultant distinctive structural characteristics of the “method of claim 7”, it raises the issue as why the claim recites “comprising a substrate…, a photosensitive doped layer…”, and a “switching device…”. Even if the claim changed each “a” to “the” to provide proper antecedent basis, it is unclear why the claim would recite “comprising the substrate…, the plurality of pixel regions…, the photosensitive layer…, and the switching device…” because the claim already requires these. Claims 2-6 depend from claim 1 and inherit its deficiencies. Furthermore, claim 2 recites: “The CMOS image sensor according to claim 1, wherein the switching device comprises an active area disposed on a part of the photosensitive doped layer and a gate disposed above and surrounding the active area and above a part of the photosensitive doped layer, a source/drain layer is formed at the top of the active area, and the gate is provided with an opening which exposes a part of the source/drain layer.“ The limitations of the body of claim 2, i.e. “an active area…”, a gate…”, “a source/drain layer…” all lack proper antecedent basis. Each has already been recited in claim 7, and thus since each refers back to claim 7 with “a” instead of “the”, each lacks proper antecedent basis. For each, it thus raises the issue as whether the instance recited in claim 2 refers to the same element as is recited in claim 7, or if it could be a different (e.g. “second”) such element. Furthermore, because the limitations of the body of claim 2 are inherent due to the resultant distinctive structural characteristics of the “method of claim 7”, it raises the issue as why the claim recites the body of the claim, because the claim already requires these elements. Furthermore, claim 5 recites: “The CMOS image sensor according to claim 1, further comprising an isolation structure which is disposed between adjacent pixel regions and between adjacent switching devices.” The limitations of the body of claim 5, i.e. “an isolation structure…” lacks proper antecedent basis. It has already been recited in claim 7, and thus since it refers back to claim 7 with “a” instead of “the”, it lacks proper antecedent basis. This thus raises the issue as whether the instance recited in claim 5 refers to the same element as is recited in claim 7, or if it could be a different (e.g. “second”) such element. Furthermore, because the limitations of the body of claim 5 are inherent due to the resultant distinctive structural characteristics of the “method of claim 7”, it raises the issue as why the claim recites the body of the claim, because the claim already requires these elements. Allowable Subject Matter Claim(s) 7, 11-12, and 14-20 is/are allowed. The following is an examiner’s statement of reasons for allowance: the prior art does not explicitly teach, or reasonably suggest as obvious to one of ordinary skill in the art, an invention having all of the limitations of claim 7, including: wherein a plurality of isolation structures are formed in the substrate structure, each of the plurality of isolation structures penetrates the initial photosensitive doped layer and is respectively disposed between adjacent pixel regions to form the plurality of mutually discrete photosensitive doped layers, and each of the plurality of isolation structures penetrates the initial well doped layer to form a plurality of well doped layers which are mutually discrete; wherein the switching device comprises an active area disposed on a part of the photosensitive doped layer and a gate disposed above and surrounding the active area and above a part of the photosensitive doped layer, a source/drain layer is formed at the top of the active area, and the gate is provided with an opening which exposes a part of the source/drain layer. wherein a method for forming the substrate structure comprises: etching one of the plurality of well doped layers formed on the one of the plurality of photosensitive doped layers until the one of the plurality of photosensitive doped layers is exposed, thus forming a gate trench, wherein a part of the well doped layer constitutes the active area, and the active area and one of the plurality of isolation structures are exposed by the gate trench; forming the gate in the gate trench and above the active area and forming an opening in the gate, wherein the opening exposes a part of the top surface of the active area; and implanting first ions into the opening to form the source/drain layer. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Response to Arguments Applicant's arguments with respect to the pending claims have been considered but are moot in view of the new ground(s) of rejection. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Conclusion / Finality Applicant's amendment changed the scope of the claims and necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Conclusion / Prior Art The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited. Conclusion / Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Kevin Parendo/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Feb 06, 2023
Application Filed
Nov 07, 2025
Non-Final Rejection — §112
Feb 18, 2026
Response Filed
Mar 09, 2026
Final Rejection — §112 (current)

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Prosecution Projections

3-4
Expected OA Rounds
72%
Grant Probability
84%
With Interview (+12.1%)
2y 11m
Median Time to Grant
Moderate
PTA Risk
Based on 742 resolved cases by this examiner. Grant probability derived from career allow rate.

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