DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a FINAL OFFICE ACTION in response to the amendment /remarks filed 07/24/2026. Claim 9 is cancelled. Claims 1-8 and 10-20 are pending in the Application, of which Claims 1, 11 and 14 are independent.
Response to Arguments
Applicant's arguments filed 07/24/2026, with respect to the rejection of claims 1-8 and 10-20 under 35 U.S.C. 102(a)(1) as being anticipated by Motika et al. (Pub. No. US 20140006889), have been fully considered but they are not persuasive, as set forth in the present office action.
Applicant argues that Motika fails to disclose the limitations, as amended in independent claim 1, to require that the first plurality of clock cycles comprises a first test run based on a pre-determined number of clock cycles to cause a 100% toggle of primary cryptographic circuitry of the cryptographic circuitry and that the control logic is to be spread the first test run across multiple fault tolerant test intervals (FTTIs) by pausing and resuming the test run.
In response to Applicant’s arguments, Motika discloses [0023] Referring to FIG. 1, an LFSR with an added "shadow" also referred to as a "save and restore" LFSR that stores an initial seed, consisting "0" and "1" bits. The seed can be reloaded into the LFSR at the start of each test interval. The MISR stores or saves the current signature at the end of a test interval and then unloads it and compares the current signature to the signature stored in the MISR shadow register that preferably employs an XOR circuit.
Furthermore, Motika discloses, [0052] Step 430, The BIST test sequence is then executed with sufficient cycles of system clocks and channel scan clocks generated to complete a test sequence of "n" user-specified test intervals. At the completion of the n-loops test 440, the MISR contents are stored in the MISR `shadow` register for comparison in subsequent executions of the n-loops test.
Applicant argues that the rejection of claim 9 seems to be based on Motika's mention of a serial signature comparator (see paragraph 0071), which may provide for comparing bits of the signatures serially rather than in parallel, not for spreading a test run across multiple FTTIs.
In response to Applicant’s arguments, the examiner notes that there is no support in Applicant’s specification for parallel comparison. For example, the specification describes “once the test run is completed, logic and/or features of control logic 310 such as signature feature 314 pulls the golden signature from signature register(s) 336 and compares the golden signature to MISR signature 421 that includes the values or data outputted by crypto engine 415 during the test run.
Clearly, there is no mention of parallel comparison in Applicant’s specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 and 10-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Motika et al. (Pub. No. US 20140006889) Pub. Date: 2014-01-02.
Regarding independent Claims 1, 11 and 14, Motika discloses a design-for-test that automatically detects multiple unstable signatures and associated instability in the source channels, comprising:
a linear-feedback shift register (LFSR); FIG. 1, [0027] Step 105 shows a diagram for LFSR 115 pseudo-random stimuli generator and associated shadow register 110. One or more LFSRs 110, 115 can be configured as inputs for the logic being tested.
a register “MISR” configured to store data generated by cryptographic circuitry on a die; [0028] Step 125 depicts a MISR similar to the LFSR with additional inputs to the XOR between the MISR latches. The associated `shadow` register is depicted in Step 110. This enables a response compression into a digital signature of length equal to the number of MISR latches.
cause the LFSR to generate, over a plurality of clock cycles, a random pattern that is to be inputted to the cryptographic circuitry; and provide, to the register, output data generated by the cryptographic circuitry during the plurality of clock cycles; FIG. 1, [0026] Step 100 represents the logic tested by the surrounding built-in test support with stimuli generated by the Pseudo-Random Pattern Generator 105 and the responses compressed into the Response Compression Signature Generator 107. The clocking to the logic is shown to be provided by the BIST sequencing engine 130. Input stimuli to the logic are advantageously generated by the LFSR 115, while the responses are compressed into the MISR 125.
compare the output data in the register to a signature that is based on expected data to be output from the cryptographic circuitry; [0032] Signature comparator 140 provides a serial comparison between the current MISR signature and the previous equivalent test interval signature stored in the MISR shadow register. Matching signatures indicate that the test interval produces a stable response.
provide an indication of whether the cryptographic circuitry passes or fails an infield test scan. FIG. 4, [0055] Step 460--A non-zero XOR result is indicative of signature instability and the need to determine a mask. A result of zero from the XOR operation indicates a repeated signature. The number of test executions is compared to the preset value "m".
Regarding Claims 2, 3, 12,13, 15, 16, Motika discloses the LFSR to generate the random pattern based on the control logic providing a seed value to initiate the random pattern, wherein the signature is determined based on the seed value, a number of clock cycles, and a cryptographic algorithm.
[0023] Referring to FIG. 1, an LFSR is provided with an added "shadow" also referred to as a "save and restore" LFSR that stores an initial seed, consisting "0" and "1" bits. The seed can be reloaded into the LFSR at the start of each test interval.
[0005] There are many compression and signature generation methods and algorithms. A common approach in communications and testing in generating signatures is the use of a Linear Feedback Shift Register (LFSR) with XOR inputs to alter the LFSR state machine sequence depending on the input data.
Regarding Claims 4, 17, Motika discloses the start indicator is received from a microcontroller of the die, to assert a bit in the second register to provide the start indicator. [0033] The BIST sequential engine 130 controls the setup and execution of one or more test intervals. It loads all the LFSR and MISR initial seeds and feedback configurations, sequences the number of test cycles for each test interval and compares the signatures at the end of the intervals. [0035] Both, the MISR and the shadow registers can also be individually loaded during initial setup and unloaded via the serial shift ports.
Regarding Claims 5, 6, 18-20, Motika discloses information to indicate whether the cryptographic circuitry passes or fails the infield test scan, and to provide the indication of whether the cryptographic circuitry passes or fails the infield test scan, via a message or interrupt to be sent to a microcontroller of the die. FIG. 4, illustrates an initial check for signature instability. [0054] Step 450--The XOR result is compared with zero. [0055] Step 460--A non-zero XOR result is indicative of signature instability “cryptographic circuitry fails” and the need to determine a mask. A result of zero from the XOR operation indicates a repeated signature “cryptographic circuitry passes”. The number of test executions is compared to the preset value "m".
[0056] Step 480--If the test has executed fewer than "m" times, it is run again for a stable signature check 470. [0057] Step 490--If after "m" user-specified iterations, the XOR result is always "0", it may be assumed that there is no instability, and hence no need for a MISR mask.
Regarding Claim 7, Motika discloses the register comprises a multiple input signature register (MISR). FIG. 1, MISR 125.
Regarding Claims 8, Motika discloses send a request to receive a clock signal from a phase-locked loop (PLL); and responsive to receipt of a grant to receive the clock signal, cause the LFSR to generate, over the plurality of clock cycles, the random pattern using the clock signal. [0071] Still referring to FIG. 6, the LBIST control or sequencing engine 614 with an associated Phase Lock Loop (PLL) 612 and On-Product-Clock-Generation (OPCG) 613 is illustrated. LBIST stimuli are provided by the LFSR 610 and `shadow` register 600, while the responses are compressed into the MISR 650, associated shadow register 645 and mask register 640. A serial signature comparator is shown by XOR Step 655.
Regarding Claim 10, Motika discloses the die is included in a multi-die system to be configured as a processor. [0012] A further embodiment provides a method of detecting unstable signatures when testing a Very-large-scale integration VLSI chip, corresponding to a processor.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: August 10, 2026
Final Rejection 20260810
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
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