DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chaudhuri et al (U.S PG-PUB No. 20190045168 A1), hereinafter Chaudhuri in view of Iqbal et al (U.S PG-PUB No. 20200061811 A1), hereinafter Iqbal,
-Regarding claim 1, Chaudhuri discloses that a processor (FIG. 9, CPU 901, graphic processing unit 902; FIG. 10; [0106], “GPU”; [0027], “image signal processor 101”; FIG. 1) uses a neural network to generate a first plurality of feature maps using one or more convolutional layers (FIG. 4, output at pooling layer 420, convolution layers 411, 413, 415, 417, 419; [0046]-[0048]), the first plurality of feature maps corresponding to an input image (FIG. 4, input 401); combine the first plurality of feature maps with a second plurality of feature maps to generate a plurality of combined feature maps (FIG. 4, connection 422, output of convolution layer 421; [0046], “The resultant feature maps are combined, at connection 422 with the output (e.g., feature maps) from pooling layer 420. Connections 422, 424, 426, 428, 430, 432 434, 436, 438, 440 combine the relevant feature maps using any suitable technique or techniques such as addition, concatenation, channel wise concatenation, or the like”; [0047]-[0048]), the second plurality of feature maps generated by weighting the first plurality of feature maps based on the input image (FIG. 4, output of convolution layer 421, input 401; [0046]-[0048]; Note: the feature maps at the output convolution layer 421 ( i.e., the second plurality of feature maps) are obtained based on the feature maps at the output of pooling layer 420 (i.e., the first plurality of feature maps) that are generated based on the input image through a plurality of convolution layers. The feature maps at the output convolution layer 421 can be considered as weighted feature maps at the output of pooling layer 420 as well. It is known that convolutional neural network is based on the shared-weight architecture of the convolutional kernels or filters that slide along input features and provide translation-equivalent response known as feature map. The convolutional layer is the core building block of a CNN. The layer's parameters consist of a set of learnable filters (or kernels), which have a small receptive field, but extend through the full depth of the input volume. During the forward pass, each filter is convolved across the width and height of the input volume, computing the dot product between the filter entries and the input, producing a 2-dimensional activation map of that filter. See Convolutional neural network - Wikipedia 2026); and upsample the plurality of combined feature maps to generate an output image ([0046], “the resultant feature maps from connection 422 are upsampled (e.g., 2×2 upsampled) at upsampling layer 423”; [0047]-[0048]).
Chaudhuri does disclose that the neural network that can be implemented on a graphics dedicated processor (e.g., a graphics processing unit (GPU) (Chaudhuri: [0106]; see also Park: [0114]; [0222]; [0227]; [0241]). Chaudhuri does not disclose a processor comprising a set of graphics cores to share a cache memory, wherein each of the graphics cores comprise: an instruction cache; a cache/shared memory; a texture unit; a set of registers; integer logic units; floating point logic units to perform 16-bit floating point operations; and matrix processing units (MPUs) to perform half-precision floating point and 8-bit integer operations; memory coupled with the sets of graphics cores, wherein the memory includes graphics double data rate (GDDR) memory; a memory controller; and a PCI Express host interface.
In the same field of endeavor, Iqbal teaches a processor including a set of graphics cores for a machine-learning system using neural networks (Iqbal: Abstract; FIGS. 3, 7-9b, 10, 12C-12D). Iqbal further teaches the processor comprising (Iqbal: FIGS. 20A-20B, GPGPU 2030): a set of graphics cores (Iqbal: FIG. 20B, clusters 2036A-2036H; [0293], “each include a set of graphics cores”) to share a cache memory (Iqbal: [0291], “share a cache memory 2038”), wherein each of the graphics cores comprise (Iqbal: FIG. 20A, graphics core 2000; [0288]): an instruction cache (Iqbal: FIG. 20A, cache 1902); a cache/shared memory (Iqbal: FIG. 20A, memory 1920); a texture unit (Iqbal: FIG. 20A, unit 1918); a set of registers (Iqbal: FIG. 20A, registers 2010A-2010N); integer logic units (Iqbal: FIG. 20A, units ALUs 2016-2016N); floating point logic units to perform 16-bit floating point operations (Iqbal: FIG. 20A, FPUs 2014A-2014N; [0289]); and matrix processing units (MPUs) to perform half-precision floating point and 8-bit integer operations (Iqbal: FIG. 20A, MPU 2017A-2017N; [0289]); memory coupled with the sets of graphics cores (Iqbal: FIG. 20B; [0292]), wherein the memory includes graphics double data rate (GDDR) memory (Iqbal: FIG. 20B; [0292], “graphics double data rate (GDDR) memory”); a memory controller (Iqbal: FIG. 20B, memory controllers 2042A-2042B); and a PCI Express host interface (Iqbal: FIG. 20B, interface 2032; [0291]).
Therefore, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine the teaching of Chaudhuri with the teaching of Iqbal by using the same or similar processor comprising a set of graphics cores that are optimized to perform any amount and type of operations associated with machine learning (Iqbal: [0233]; [0289]; [0293]) in order to achieve fast neural network training and best performance of the trained neural network (Please note: claim 1 recites a plurality of claim limitations related to a processor. However, these claim limitations are fully disclosed by Iqbal. Therefore, these claim limitations are not inventive concepts. Thus , claim 1 recites using a known hardware to implement a neural network to perform up-sampling.).
-Regarding claim 11 Chaudhuri discloses that a processor (FIG. 9, CPU 901, graphic processing unit 902; FIG. 10; [0106], “GPU”; [0027], “image signal processor 101”; FIG. 1) uses a neural network to generate a first plurality of feature maps using one or more convolutional layers (FIG. 4, output at pooling layer 420, convolution layers 411, 413, 415, 417, 419; [0046]-[0048]), the first plurality of feature maps corresponding to an input image (FIG. 4, input 401); combine the first plurality of feature maps with a second plurality of feature maps to generate a plurality of combined feature maps (FIG. 4, connection 422, output of convolution layer 421; [0046], “The resultant feature maps are combined, at connection 422 with the output (e.g., feature maps) from pooling layer 420. Connections 422, 424, 426, 428, 430, 432 434, 436, 438, 440 combine the relevant feature maps using any suitable technique or techniques such as addition, concatenation, channel wise concatenation, or the like”; [0047]-[0048]), the second plurality of feature maps generated by weighting the first plurality of feature maps based on the input image (FIG. 4, output of convolution layer 421, input 401; [0046]-[0048]; Note: the feature maps at the output convolution layer 421 ( i.e., the second plurality of feature maps) are obtained based on the feature maps at the output of pooling layer 420 (i.e., the first plurality of feature maps) that are generated based on the input image through a plurality of convolution layers. The feature maps at the output convolution layer 421 can be considered as weighted feature maps at the output of pooling layer 420 as well. It is known that convolutional neural network is based on the shared-weight architecture of the convolutional kernels or filters that slide along input features and provide translation-equivalent response known as feature map. The convolutional layer is the core building block of a CNN. The layer's parameters consist of a set of learnable filters (or kernels), which have a small receptive field, but extend through the full depth of the input volume. During the forward pass, each filter is convolved across the width and height of the input volume, computing the dot product between the filter entries and the input, producing a 2-dimensional activation map of that filter. See Convolutional neural network - Wikipedia 2026); and upsample the plurality of combined feature maps to generate an output image ([0046], “the resultant feature maps from connection 422 are upsampled (e.g., 2×2 upsampled) at upsampling layer 423”; [0047]-[0048]).
Chaudhuri does disclose that the neural network that can be implemented on a graphics dedicated processor (e.g., a graphics processing unit (GPU) (Chaudhuri: [0106]; see also Park: [0114]; [0222]; [0227]; [0241]). Chaudhuri does not disclose a system on chip (SoC) comprising: a set of graphics cores to share a cache memory, wherein each of the graphics cores comprise: an instruction cache; a cache/shared memory; a texture unit; a set of registers; integer logic units; floating point logic units to perform 16-bit floating point operations; and matrix processing units (MPUs) to perform half-precision floating point and 8-bit integer operations; memory coupled with the sets of graphics cores, wherein the memory includes graphics double data rate (GDDR) memory; a memory controller; and a PCI Express host interface.
In the same field of endeavor, Iqbal teaches a system on chip (SoC) (Iqbal: FIGS. 13-14, 18-19B; [0287]) for a machine-learning system using neural networks (Iqbal: Abstract; FIGS. 3, 7-8, 10; [0281]). Iqbal further teaches the processor comprising (Iqbal: FIGS. 20A-20B, GPGPU 2030): a set of graphics cores (Iqbal: FIG. 20B, clusters 2036A-2036H; [0293], “each include a set of graphics cores”) to share a cache memory (Iqbal: [0291], “share a cache memory 2038”), wherein each of the graphics cores comprise (Iqbal: FIG. 20A, graphics core 2000; [0288]): an instruction cache (Iqbal: FIG. 20A, cache 1902); a cache/shared memory (Iqbal: FIG. 20A, memory 1920); a texture unit (Iqbal: FIG. 20A, unit 1918); a set of registers (Iqbal: FIG. 20A, registers 2010A-2010N); integer logic units (Iqbal: FIG. 20A, units ALUs 2016-2016N); floating point logic units to perform 16-bit floating point operations (Iqbal: FIG. 20A, FPUs 2014A-2014N; [0289]); and matrix processing units (MPUs) to perform half-precision floating point and 8-bit integer operations (Iqbal: FIG. 20A, MPU 2017A-2017N; [0289]); memory coupled with the sets of graphics cores (Iqbal: FIG. 20B; [0292]), wherein the memory includes graphics double data rate (GDDR) memory (Iqbal: FIG. 20B; [0292], “graphics double data rate (GDDR) memory”); a memory controller (Iqbal: FIG. 20B, memory controllers 2042A-2042B); and a PCI Express host interface (Iqbal: FIG. 20B, interface 2032; [0291]).
Therefore, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine the teaching of Chaudhuri with the teaching of Iqbal by using a system on chip comprising a set of graphics cores that are optimized to perform any amount and type of operations associated with machine learning (Iqbal: [0233]; [0289]; [0293]) in order to achieve efficient and fast neural network training, and best performance of the trained neural network.
-Regarding claims 2 and 12, Chaudhuri in view of Iqbal teaches the processor of claim 1 and the SoC of claim 11.
Chaudhuri does not disclose wherein the memory controller is to provide access to a memory interface to access synchronous dynamic random-access memory (SDRAM) devices.
In the same field of endeavor, Iqbal teaches a system on chip (SoC) (Iqbal: FIGS. 13-14, 18-19B; [0287]) for a machine-learning system using neural networks (Iqbal: Abstract; FIGS. 3, 7-8, 10; [0281]). Iqbal further teaches wherein the memory controller is to provide access to a memory interface to access synchronous dynamic random-access memory (SDRAM) devices (Iqbal: [0279], “memory controller 1865 for access to SDRAM”).
Therefore, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine the teaching of Chaudhuri with the teaching of Iqbal by using a processor or system on chip comprising a set of graphics cores that are optimized to perform any amount and type of operations associated with machine learning in order to achieve efficient and fast neural network training, and best performance of the trained neural network.
-Regarding claims 3 and 13, Chaudhuri in view of Iqbal teaches the processor of claim 1 and the SoC of claim 11.
Chaudhuri does not disclose wherein each of the graphics cores further comprise a scheduler to schedule one or more threads to be performed.
In the same field of endeavor, Iqbal teaches a system on chip (SoC) (Iqbal: FIGS. 13-14, 18-19B; [0287]) for a machine-learning system using neural networks (Iqbal: Abstract; FIGS. 3, 7-8, 10; [0281]). Iqbal further teaches wherein each of the graphics cores further comprise a scheduler to schedule one or more threads to be performed (Iqbal: [0288], “a thread scheduler 2006A-2006N”; [0291], “execution threads”).
Therefore, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine the teaching of Chaudhuri with the teaching of Iqbal by using a processor or system on chip comprising a set of graphics cores that are optimized to perform any amount and type of operations associated with machine learning in order to achieve efficient and fast neural network training, and best performance of the trained neural network.
-Regarding claims 4 and 14, Chaudhuri in view of Iqbal teaches the processor of claim 1 and the SoC of claim 11.
Chaudhuri does not disclose further comprising an input/output hub to couple the processor or Soc to other processor instances.
In the same field of endeavor, Iqbal teaches a system on chip (SoC) (Iqbal: FIGS. 13-14, 18-19B; [0287]) for a machine-learning system using neural networks (Iqbal: Abstract; FIGS. 3, 7-8, 10; [0281]). Iqbal further teaches further comprising an input/output hub to couple the processor or Soc to other processor instances (Iqbal: FIGS. 20A-20B; [0294], “I/O hub 2039 that couples GPGPU 2030 with a GPU link 2040 that enables a direct connection to other instances”).
Therefore, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine the teaching of Chaudhuri with the teaching of Iqbal by using a processor or system on chip comprising a set of graphics cores that are optimized to perform any amount and type of operations associated with machine learning in order to achieve efficient and fast neural network training, and best performance of the trained neural network.
-Regarding claims 5 and 15, Chaudhuri in view of Iqbal teaches the processor of claim 1 and the SoC of claim 11.
Chaudhuri does not disclose further comprising a link to enable communication with other processor instances.
In the same field of endeavor, Iqbal teaches a system on chip (SoC) (Iqbal: FIGS. 13-14, 18-19B; [0287]) for a machine-learning system using neural networks (Iqbal: Abstract; FIGS. 3, 7-8, 10; [0281]). Iqbal further teaches further comprising a link to enable communication between with other processor instances (Iqbal: FIGS. 20A-20B; [0294], “GPU link 2040 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances”).
Therefore, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine the teaching of Chaudhuri with the teaching of Iqbal by using a processor or system on chip comprising a set of graphics cores that are optimized to perform any amount and type of operations associated with machine learning (Iqbal: [0233]; [0289]; [0293]) in order to achieve efficient and fast neural network training, and best performance of the trained neural network.
-Regarding claim 6, Chaudhuri in view of Iqbal teaches the processor of claim 1.
Chaudhuri does not disclose wherein the processor is to be included on a system on chip (SoC).
In the same field of endeavor, Iqbal teaches a system on chip (SoC) (Iqbal: FIGS. 13-14, 18-19B; [0287]) for a machine-learning system using neural networks (Iqbal: Abstract; FIGS. 3, 7-8, 10; [0281]). Iqbal further teaches wherein the processor is to be included on a system on chip (SoC) (Iqbal: FIG. 18B; [0278]).
Therefore, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine the teaching of Chaudhuri with the teaching of Iqbal by using a processor or system on chip comprising a set of graphics cores that are optimized to perform any amount and type of operations associated with machine learning in order to achieve efficient and fast neural network training, and best performance of the trained neural network.
-Regarding claims 7 and 17, Chaudhuri in view of Iqbal teaches the processor of claim 1 and the SoC of claim 11.
Chaudhuri does not disclose wherein each of the graphics cores further comprise a dispatcher to dispatch one or more threads to be performed.
In the same field of endeavor, Iqbal teaches a system on chip (SoC) (Iqbal: FIGS. 13-14, 18-19B; [0287]) for a machine-learning system using neural networks (Iqbal: Abstract; FIGS. 3, 7-8, 10; [0281]). Iqbal further teaches wherein each of the graphics cores further comprise a dispatcher to dispatch one or more threads to be performed (Iqbal: FIGS.20A-20B; [0288], “a thread dispatcher 2008A-2008N”; FIG. 19A, [0285], “dispatch execution threads”).
Therefore, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine the teaching of Chaudhuri with the teaching of Iqbal by using a processor or system on chip comprising a set of graphics cores that are optimized to perform any amount and type of operations associated with machine learning in order to achieve efficient and fast neural network training, and best performance of the trained neural network.
-Regarding claims 8 and 18, Chaudhuri in view of Iqbal teaches the processor of claim 1 and the SoC of claim 11.
Chaudhuri does not disclose further comprising floating point logic units to perform 32-bit floating point operations.
In the same field of endeavor, Iqbal teaches a system on chip (SoC) (Iqbal: FIGS. 13-14, 18-19B; [0287]) for a machine-learning system using neural networks (Iqbal: Abstract; FIGS. 3, 7-8, 10; [0281]). Iqbal further teaches further comprising floating point logic units to perform 32-bit floating point operations (Iqbal: FIGS. 20A-20B; [0289]; [0293]).
Therefore, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine the teaching of Chaudhuri with the teaching of Iqbal by using a s processor or system on chip comprising a set of graphics cores that are optimized to perform any amount and type of operations associated with machine learning in order to achieve efficient and fast neural network training, and best performance of the trained neural network.
-Regarding claim 16, Chaudhuri in view of Iqbal teaches the SoC of claim 11.
Chaudhuri does not disclose comprising one or more processors optimized to perform one or more shader programs.
In the same field of endeavor, Iqbal teaches comprising one or more processors optimized to perform one or more shader programs (Iqbal: [0283], “optimized to execute fragment shader programs”).
Therefore, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine the teaching of Chaudhuri with the teaching of Iqbal by using a processor or system on chip comprising a set of graphics cores that are optimized to perform any amount and type of operations associated with machine learning in order to achieve efficient and fast neural network training, and best performance of the trained neural network.
-Regarding claims 9 and 19, Chaudhuri in view of Iqbal teaches the processor of claim 1 and the SoC of claim 11. The combination further teaches wherein the one or more convolutional layers are to generate the first plurality of feature maps based, at least in part, on the input image, and wherein the input image is smaller than the output image (Chaudhuri: Abstract, “upscaling”; FIG. 4, input 401, output at pooling layer 420, convolution layers 411, 413, 415, 417, 419; FIGS. 1-3, 5, image 217 (input), image 114 (output); [0036]; [0046]-[0048]; [0055], “image super-resolution CNN 103, which gradually upscales downscaled intermediate image 217 to intermediate image 114”; [0056]; FIG. 8, step 805).
-Regarding claims 10 and 20, Chaudhuri in view of Iqbal teaches the processor of claim 1 and the SoC of claim 11. The combination further teaches wherein the one or more convolutional layers are comprised in the neural network(Chaudhuri: FIGS. 1-5).
Response to Arguments
Applicant's arguments filed 05/01/2026 regarding to claim rejections under 35 U.S.C. 103 have been fully considered but they are not persuasive. Applicant argues that Chaudhuri does not disclose “weighted based on the input image” (Remarks: Page 8, 2nd paragraph) and “weighting of one set of feature maps to generate another set of feature maps and then combination of both sets of feature maps”.
Regarding independent claims 1 and 11 and in response to applicant's arguments that Chaudhuri does not disclose “weighted based on the input image” (Remarks: Page 8, 2nd paragraph) and “weighting of one set of feature maps to generate another set of feature maps and then combination of both sets of feature maps” (Remarks: Page 8, last paragraph), the claim does not provide the details about how to weight a plurality of feature maps based on the input image (emphasis added). The claim does not recite whether the weights for the weighting of the feature maps, or the feature maps, or both the weights and the feature maps, or the ways or methods to perform the weighting process are derived from or related to the input image. On the other hand, Chaudhuri discloses to generate a first plurality of feature maps using one or more convolutional layers (FIG. 4, output at pooling layer 420, convolution layers 411, 413, 415, 417, 419; [0046]-[0048]), the first plurality of feature maps corresponding to an input image (FIG. 4, input 401); combine the first plurality of feature maps with a second plurality of feature maps to generate a plurality of combined feature maps (FIG. 4, connection 422, output of convolution layer 421; [0046], “The resultant feature maps are combined, at connection 422 with the output (e.g., feature maps) from pooling layer 420. Connections 422, 424, 426, 428, 430, 432 434, 436, 438, 440 combine the relevant feature maps using any suitable technique or techniques such as addition, concatenation, channel wise concatenation, or the like”; [0047]-[0048]), the second plurality of feature maps generated by weighting the first plurality of feature maps based on the input image (FIG. 4, output of convolution layer 421, input 401; [0046]-[0048]); and upsample the plurality of combined feature maps to generate an output image ([0046], “the resultant feature maps from connection 422 are upsampled (e.g., 2×2 upsampled) at upsampling layer 423”; [0047]-[0048]). See also this office action, pages 2-3. Please note that the feature maps at the output convolution layer 421 ( i.e., the second plurality of feature maps) are obtained based on the feature maps at the output of pooling layer 420 (i.e., the first plurality of feature maps) that are generated based on the input image through a plurality of convolution layers (emphasis added). The feature maps at the output convolution layer 421 can be considered as weighted feature maps at the output of pooling layer 420 (emphasis added). It is known that convolutional neural network is based on the shared-weight architecture of the convolutional kernels or filters that slide along input features and provide translation-equivalent response known as feature map. The convolutional layer is the core building block of a CNN. The layer's parameters consist of a set of learnable filters (or kernels), which have a small receptive field, but extend through the full depth of the input volume. During the forward pass, each filter is convolved across the width and height of the input volume, computing the dot product between the filter entries and the input, producing a 2-dimensional activation map of that filter. See Convolutional neural network - Wikipedia 2026.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhang et al (US 20190378242 A1), hereinafter Zhang teaches a method for generating a super-resolution image is generated based on reference images. Zhang further teaches a content feature map indicating low-frequency content of an image is adaptively fused with a swapped texture feature map including patches of reference images with a neural network based on similarity of texture features, and a similarity score for each pair of matching patches is recorded in a weight map (Zhang: FIGS. 2, 4).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/XIAO LIU/Primary Examiner, Art Unit 2664
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