Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 12, 2026 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 15, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed September 3, 2025. Claims 1 is amended. The Examiner notes that claims 1-14 and 18-20 are examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5-7, 10-14, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Khim (US 2021/0296249 A1) and Nayaran (US 2005/0104217 A1).
With respect to claim 1, Khim teaches:
A semiconductor package, comprising:
a bottom substrate (bottom substrate 11) and a top substrate (top substrate 19) space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween (separated by a gap that contains body 15);
a logic die (electric component 14) mounted on a top surface (top surface of 11) of the bottom substrate (11) in a flip-chip fashion, wherein the logic die has a thickness of 20 to 300 micrometers (para. 39, “Electronic component 14 can have a thickness in the range from approximately 20 μm to approximately 300 μm.”)
wherein the logic die comprises an active front side (bottom of 14),
a passive rear side (top of 14),
and an input/output (I/O) pad (para. 40 “141 can comprise or can be referred to as pads, pillars, or bumps”) provided on the active front side;
wherein the logic die (14) is electrically connected to the bottom substrate (11) through a bump structure (141 and 1112 excluding the pad portions) disposed on a bonding pad (Top interconnects 1112 can comprise or can be referred to as pads, lands, Under Bumped Metallizations (UBMs), vias, downward vias, or pillars.”) on the top surface of the bottom substrate (11),
and wherein the bump structure comprises a gold layer and a nickel layer (para. 32” bottom interconnects 1113 can be provided by plating copper (Cu) or nickel (Ni), sequentially plating gold (Au) and copper (Cu), or sequentially plating gold (Au) and nickel (Ni).”, para. 33 teaches that 1112 can be formed from the same process as 1113)
a plurality of copper cored solder balls (para. 43 “interconnects 18 can comprise a metallic core 18a surrounded by solder coating 18b, where metallic core 18a can comprise copper”) disposed between the bottom substrate (11) and the top substrate (19) around the logic die (14) to electrically connect the bottom substrate with the top substrate (para. 43 “Internal interconnects 18 can electrically connect bottom substrate 11 and top substrate 19 to each other”);
and a sealing resin (para. 28 “Body 15 can comprise or can be referred to as an encapsulant, a mold compound, a resin, or a sealant”) filling in the gap between the bottom substrate (11) and the top substrate (19) and sealing the logic die (14) and the plurality of copper cored solder balls (18) in the gap.
The range 20-300 micrometers taught by Khim overlaps with the claimed range of 125-350 micrometers. It would be obvious to one of ordinary skill in the art to select a die thickness in the claimed range to tune the thermal properties of the die and footprint of the die within desired parameters and/or because in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists (MPEP 2144.05(I)).
Khim fails to teach:
and wherein an interface between the gold layer and the nickel layer is flush with the top surface of the bottom substrate
wherein the nickel layer is disposed under the top surface of the bottom substrate and the gold layer is disposed above the top surface of the bottom substrate
Nayaran teaches in Fig. 3B:
and wherein an interface between the gold layer (metal plating 142 which is preferably gold, see para. 23) and the nickel layer (electroplatable pads 112 which may preferably nickel, see para. 20) is flush with the top surface of the bottom substrate (top surface of insulating material layers 119 which acts as an interconnect substrate)
wherein the nickel layer (112) is disposed under the top surface of the bottom substrate and the gold layer (142) is disposed above the top surface of the bottom substrate (see annotated Fig. 3B below
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Khim differs from the claimed invention in that the interface between gold and nickel is not flush with the top of the substrate. It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have adjusted the shape of the bump so that the interface between gold and nickel is flush with the substrate as taught by Nayaran for the purpose of providing low cost, low resistance, high yield, reliable connections between chips (para. 3-9) See MPEP 2144.04.
With respect to claim 2, it is further obvious over Khim:
wherein the logic die has a thickness of greater than 170 micrometers.
The range 20-300 micrometers taught by Khim overlaps with the claimed range of “over 170 micrometers”. It would be obvious to one of ordinary skill in the art to select a die thickness in the claimed range to tune the thermal properties of the die and footprint of the die within desired parameters and/or because in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists (MPEP 2144.05(I)).
With respect to claim 5, Khim further teaches:
wherein an underfill (underfill 16) is disposed in a space between the logic die (14) and the top surface of the bottom substrate (11).
Although Khim does not specify that the underfill is a resin, the use of epoxy resin as an underfill in bonding is well known in the art. It would be obvious to the ordinary artisan to use an underfill that is a resin because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
With respect to claim 6, Khim further teaches:
wherein the bottom substrate (11) and the top substrate (19) are printed wiring boards (both 11 and 19 are boards with conductive paths 1111 and 1911, respectively) or package substrates.
With respect to claim 7, Khim further teaches:
wherein the gap has a gap height ranging between 50-300 micrometers (the gap height is the same as the height of the internal interconnects 18. Para. 43 teaches “Internal interconnects 18 can have a diameter in the range from approximately 50 μm to approximately 300 μm.”)
The range 20-300 micrometers taught by Khim overlaps with the claimed range of 160-450 micrometers. It would be obvious to one of ordinary skill in the art to select a gap height in the claimed range to balance the thermal properties of the device with miniaturization within desired parameters and/or because in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists (MPEP 2144.05(I)).
With respect to claim 10, Khim further teaches:
wherein each of the plurality of copper cored solder balls (18) comprises a copper core coated with a solder layer (para. 43 “interconnects 18 can comprise a metallic core 18a surrounded by solder coating 18b”)
With respect to claim 11, Khim further teaches:
wherein the logic die (14) is electrically connected to the bottom substrate (11) through a conductive element (pillar or bump that is part of interconnect 141, top interconnect 1112, and seed layer 11B) on the I/O pad (pad that is part of interconnect 141), (para. 40 “141 can comprise or can be referred to as pads, pillars, or bumps”)
wherein the conductive element comprises a copper bump on the I/O pad (para. 40 “141 can comprise or can be referred to as pads, pillars, or bumps,” para. 32 “bottom interconnects 1113 can be provided by plating copper (Cu)”, para. 33 “top interconnects 1112 of conductive structure 111, and dielectric layers of dielectric structure 112, can be provided in a similar manner to that described above”).
With respect to claim 12, Khim further teaches:
wherein the copper bump (copper part of 141, 1112, and 11B) is composed of a seed layer and a copper layer (para. 32 “bottom interconnects 1113 can be provided by plating copper (Cu) or nickel (Ni), sequentially plating gold (Au) and copper (Cu), or sequentially plating gold (Au) and nickel (Ni), on the exposed portions of seed layer 11B”)
With respect to claim 13, Khim further teaches:
wherein the copper bump (copper part of 141, 1112, and 11B) has a bump height of equal to or less than 20 micrometers (para. 32 “Bottom interconnects 1113 can have a line/space/thickness in the range from approximately 0.5/0.5/0.5 micrometers (μm) to approximately 10/10/10 μm.” Para. 33 teaches that 1112 can be made in the same manner as 1113, Para. 40 “device interconnects 141 can have a thickness in the range from approximately 1 μm to approximately 50 μm”)
The total range 1.5-60 micrometers of the copper bump taught by Khim overlaps with the claimed range of under 20 micrometers. It would be obvious to one of ordinary skill in the art to select a bump height in the claimed range to balance the thermal properties of the device with miniaturization within desired parameters and/or because in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists (MPEP 2144.05(I)).
With respect to claim 14, Khim further teaches:
wherein the copper bump (copper layer of 141, 1112, and 11B) is directly bonded to the bump structure (non-copper parts of 1112, including gold located on 1112, para. 34 “In some examples, a bonding material, for example solder or gold, can be further located on top interconnects 1112” and nickel layer plated alongside copper “para. 32 “ interconnects can be provided by plating copper (Cu) or nickel (Ni), sequentially plating gold (Au) and copper (Cu), or sequentially plating gold (Au) and nickel (Ni))
With respect to claim 18, Khim further teaches:
wherein the bump structure (1112) has a bump height of equal to or less than 5 micrometers (para. 32 “Bottom interconnects 1113 can have a line/space/thickness in the range from approximately 0.5/0.5/0.5 micrometers (μm) to approximately 10/10/10 μm.” Para. 33 teaches that 1112 can be made in the same manner as 1113).
The range 0.5-10 micrometers of the bump taught by Khim overlaps with the claimed range of under 5 micrometers. It would be obvious to one of ordinary skill in the art to select a bump height in the claimed range to balance the thermal properties of the device with miniaturization within desired parameters and/or because in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists (MPEP 2144.05(I)).
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Khim (US 2021/0296249 A1) and Nayaran (US 2005/0104217 A1) as applied to claim 1 above in view of Lin (US 2014/0151867 A1).
With respect to claims 3-4, Khim/Nayaran teaches all limitations of claim 1 upon which claims 3-4 depend. Khim/Nayaran fails to teach:
wherein the I/O pad is an aluminum pad and is partially covered by a topmost passivation layer
wherein the topmost passivation layer is a silicon nitride layer
Lin teaches in Fig. 1:
wherein the I/O pad is an aluminum pad (para. 21 “metal pad 304 may comprise but is not limited to aluminum”) and is partially covered by a topmost passivation layer (insulation layer 302).
wherein the topmost passivation layer is a silicon nitride layer (para. 21 “the insulation layer 302 may comprise but is not limited to silicon nitride”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Lin into the device of Khim/Nayaran to include aluminum pads partially covered by a silicon nitride layer. The ordinary artisan would have been motivated to modify Khim/Nayaran in the manner set forth above for the purpose of making a connection between semiconductor devices with the benefit of stress buffering and insulating the pad (para. 21 of Lin) and because the use of aluminum for the pads is prima facie obvious because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Claims 8 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Khim (US 2021/0296249 A1) and Nayaran (US 2005/0104217 A1) as applied to claim 1 above in view of Cho (US 2017/0221866 A1).
With respect to claim 8, Khim/Nayaran teaches all limitations of independent claim 1 upon which claim 8 depends. Khim/Nayaran fails to teach:
wherein an aspect ratio of the plurality of copper cored solder balls ranges between 1.1-2.0.
Cho teaches in Fig. 4:
wherein an aspect ratio of the plurality of copper cored solder balls (solder bump 130 with core portion 132 made of copper) ranges between 1.1-2.0 (para. 20 “the height H of the first solder bump 130 may be about 1 or about 1.5 times the width W of the first solder bump 130”.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Cho into the device of Khim/Nayaran to use the solder bumps of Khim/Nayaran with an aspect ratio of 1.5. The ordinary artisan would have been motivated to modify Khim/Nayaran in the manner set forth above for the purpose connecting to package substrates with the benefit of improving the contact margin of the solder bumps, preventing electrical shorts, and reducing the pitch between solder joints (para. 35 of Cho).
With respect to claim 19, Khim/Nayaran teaches all limitations of independent claim 1 upon which claim 19 depends. Khim/Nayaran fails to teach:
and a memory package mounted on the semiconductor package.
Cho teaches:
and a memory package mounted (para. 30 “second semiconductor chip 220 may be a memory chip”) on the semiconductor package (semiconductor device 100).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Cho into the device of Khim/Nayaran to mount a m. The ordinary artisan would have been motivated to modify Khim/Nayaran in the manner set forth above for the purpose of creating a stacked semiconductor package with the benefit of increasing integration of a semiconductor device.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Khim (US 2021/0296249 A1) and Nayaran (US 2005/0104217 A1) as applied to claim 1 above in view of Park (US 2016/0190054 A1)
With respect to claims 9, Khim/Nayaran teaches all limitations of claim 1 upon which claim 9 depends. Khim/Nayaran fails to teach:
wherein a ball pitch of the plurality of copper cored solder balls is 0.2-0.3 mm.
Park teaches in Fig. 6:
wherein a ball pitch of the plurality of copper cored solder balls (conductive ball 112 with coper core body 113) is 0.2-0.3 mm (para. 80 “top ball pitches (the pitch between conductive balls) from a range of 0.30 mm and below (For illustrative purposes these sizes can include a range between 0.30 mm to 0.20 mm”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Park into the device of Khim/Nayaran to include a ball pitch from 0.2-0.3 mm. The ordinary artisan would have been motivated to modify Khim/Nayaran in the manner set forth above for the purpose of choosing a pitch size that minimizes space while providing enough support to the structure with the benefit of reducing the signal and power travel path of the package and the package profile (para. 92 of Park) and/or because it has been ruled that changes of thickness are prima facie obvious absent persuasive evidence that the particular size is significant (MPEP 2144.04(IV)(A)).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Khim (US 2021/0296249 A1) and Nayaran (US 2005/0104217 A1) in view of Cho (US 2017/0221866 A1) as applied to claim 19 above and further in view of Hsu (US 2016/0172292 A1).
With respect to claim 20, Khim/Nayaran/Cho teaches all limitations of claim 19 upon which claim 20 depends. Khim/Nayaran/Cho are silent to the type of memory package used and therefore do not teach:
wherein the memory package comprises a LPDDR DRAM package.
Hsu teaches:
wherein the memory package (memory die 400) comprises a LPDDR DRAM package (para. 30, “the memory die 400 may comprise a low-power double data rate DRAM (LPDDR DRAM”)
Hsu contains a LPDDR DRAM memory die that differs from the device of Khim/Nayaran/Cho by the substitution of the nonspecific memory chip of Khim/Nayaran/Cho. The LPDDR DRAM and its function is known in the art as a memory device with low power usage. The ordinary artisan could have substituted the known LPDDR DRAM with the memory device of Khim/Nayaran/Cho with predictable results. (MPEP 2143(I)(B))
Response to Arguments
Applicant’s arguments with respect to claims 1-14 and 18-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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