Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-6, 8-12, and 26-27 are pending in this application. Claims 1-6 are amended, claims 7 and 13-25 are canceled, and claims 26-27 are new by preliminary amendment filed 7 February 2023.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are:
“A neural network contour generation mechanism” in claims 1-6, 8-12, and 26-27
“a neuron summer” in claim 2
“means for generating errors” in claim 5
All of the elements above are considered generic placeholders because they are only coupled with functional language and the claims do not recite sufficient structure to perform the functions. For example, claim 1 recites the neural network contour generation mechanism “comprising a device which perturbs analog neurons . . .” This recites a function of the mechanism, but only recites the generic structure of “a device,” which is not sufficient to perform the perturbation.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 2, it recites “an analog circuit sampling and holding an activation result of the perturbation to calculate σ’(z) a difference between the activation result of the perturbation.” It is unclear if “sampling and holding an activation result” are operations performed by the analog circuit or if they are part of the name of “an analog circuit.” And the term “σ’(z)” is indefinite because none of σ, σ’, or z are clearly defined by the claim. The phrase “a difference between the activation result of the perturbation” creates a run-on sentence. It is unclear if this phrase is intended to define σ’(z) or if it is an additional limitation. Furthermore, a difference requires two elements or values. For example, “a difference between A and B” means A-B. But the present phrase lists only a single element: “the activation result of the perturbation.” So, it cannot be determined what the difference is. Because of the indefinite terms, the examiner is unable to make a meaningful interpretation of the present limitation, and can only examine the limitation “a neuron summer to integrate a perturbation” with respect to prior art.
Regarding Claim 3, as in claim 2, the term “σ’(z)” is indefinite because the terms have not been defined. As such, the multiplication of “σ’(z)” by a curl of a cost function is also indefinite. Since the terms of the multiplication are indefinite, the examiner is unable to make a meaningful interpretation of the present claim for examination under prior art.
Regarding Claims 4 and 5, they are rejected as being dependent on rejected base claims.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 5 of U.S. Patent No. 11,604,996. Although the claims at issue are not identical, they are not patentably distinct from each other because the Patent includes all of the limitations of claims 1-3, as shown in the following table:
Present Application
U.S. Patent 11,604,996
1. A neural network error contour generation mechanism comprising:
a device which perturbs analog neurons to measure an error which results from perturbations at different points within the neural network; and
a neural network update circuit modifying analog weight values to direct the neural network error contour generation mechanism towards a target in response to the error generated.
1. A neural network error contour generation mechanism comprising
a device which perturbs analog neurons to measure an error which results from perturbations at different points within the neural network,
wherein the device comprises:
a neuron summer circuit to integrate a perturbation formed of weighted and biased inputs of an error function;
an analog circuit coupled to the neuron summer sampling and holding an activation result of the perturbation to calculate σ′(z) defined as a difference between the activation result and the perturbation; and
a multiplier circuit multiplying σ′(z) by a curl of a cost function to generate output layer errors.
5. The neural network error contour generation mechanism of claim 1, comprising a neural network update circuit modifying analog weight values to direct the neural network error contour generation mechanism towards a target in response to an error contour generated.
2. The neural network error contour generation mechanism of claim 1, comprising
a neuron summer to integrate a perturbation; and
an analog circuit sampling and holding an activation result of the perturbation to calculate σ′(z) a difference between the activation result of the perturbation,
From 1:
a neuron summer circuit to integrate a perturbation formed of weighted and biased inputs of an error function;
an analog circuit coupled to the neuron summer sampling and holding an activation result of the perturbation to calculate σ′(z) defined as a difference between the activation result and the perturbation;
3. The neural network error contour generation mechanism of claim 2, comprising a multiplier circuit multiplying σ'(z) by a curl of a cost function to generate output layer errors.
From 1:
a multiplier circuit multiplying σ′(z) by a curl of a cost function to generate output layer errors.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, 6, 8, 12, and 26-27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maliuk, Dzmitry, Haralampos-G. Stratigopoulos, and Yiorgos Makris (“An analog VLSI multilayer perceptron and its application towards built-in self-test in analog circuits,” 2010 IEEE 16th International On-Line Testing Symposium. IEEE, 2010; hereinafter “Maliuk”).
Regarding Claim 1, Maliuk teaches a neural network error contour generation mechanism (p. 72, section II. A. and p. 74, section II. E.—an error surface {contour} is generated for an analog neural network) comprising:
a device which perturbs analog neurons to measure an error which results from perturbations at different points within the neural network (p. 74, section II. E.—analog neuron weights are perturbed to measure an error); and
a neural network update circuit modifying analog weight values to direct the neural network error contour generation mechanism towards a target in response to the error contour generated (p. 74, section II. E.—the training modifies weight values to direct the neural network towards target outputs in response to the error contour generated).
Regarding Claim 2, Maliuk teaches:
a neuron summer to integrate a perturbation (p. 72, section II. B., first paragraph—a neuron sums output values, thus integrating a perturbation an the neuron); and
an analog circuit sampling and holding an activation result of the perturbation to calculate σ’(z) a difference between the activation result of the perturbation (pp. 73-74, section II. D. and fig. 6(a)—the neuron circuit is an analog circuit that produces an activation result of the perturbation. As detailed above with respect to 35 U.S.C. 112(b), only a general mapping for this limitation is possible because the examiner is unable to make a meaningful interpretation of the meaning of the limitation).
Regarding Claim 3, as explained above with respect to 35 U.S.C. 112(b), the examiner is unable to make a meaningful interpretation of the claim, so an art rejection cannot be applied.
Regarding Claim 4, Maliuk teaches wherein the neurons are comprised of one or more of: switched charge multipliers, division and current mode summation circuits, and decision circuits (p. 72, section II. C. and fig. 4—the neurons include multiplying DACs, which are switched charge multipliers).
Regarding Claim 6, Maliuk teaches wherein the error caused by a perturbation at each weighted input to a neuron is measured at a respective output of the neural network (pp. 73-74, section II. D. and fig. 6(a)—output Vout).
Regarding Claim 8, Maliuk teaches a neural network update circuit modifying analog weight values to direct the neural network error contour generation mechanism towards a target in response to an error contour generated (p. 74, section II. E.—the training modifies weight values to direct the neural network towards target outputs in response to the error contour generated).
Regarding Claim 12, Maliuk teaches wherein the error is a quadratic difference (p. 74, section II. E., first paragraph—the mean squared error is a quadratic difference).
Regarding Claim 26, Maliuk teaches a neural network error contour generation mechanism (p. 72, section II. A. and p. 74, section II. E.—an error surface {contour} is generated for an analog neural network) comprising a device which perturbs analog neurons to measure an error which results from perturbations at different points within the neural network (p. 74, section II. E.—analog neuron weights are perturbed to measure an error), wherein the error is modified by a weighted value, the weighted value updated to direct the neural network error contour generation mechanism towards a target in response to the error generated (p. 74, section II. E.—the training modifies weight values to direct the neural network towards target outputs in response to the error contour generated. The error is modified by a temperature T, which is updated at different stages of the training).
Regarding Claim 27, Maliuk teaches a neural network error contour generation mechanism (p. 72, section II. A. and p. 74, section II. E.—an error surface {contour} is generated for an analog neural network) comprising a device which perturbs analog neurons to measure an error which results from perturbations at different points within the neural network (p. 74, section II. E.—analog neuron weights are perturbed to measure an error), wherein the neural network error contour generation mechanism uses a varying weighted value to direct the neural network error contour generation mechanism towards a target in response to the error generated (p. 74, section II. E.—the training modifies weight values to direct the neural network towards target outputs in response to the error contour generated. The temperature T is a varying weighted value which is changed at different stages of the training to direct the neural network error contour generation mechanism towards a target in response to the error generated).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Maliuk, as applied to claims 1 and 8, above, in view of Kurokawa (U.S. 2017/0116512).
Regarding Claims 9 and 10, Maliuk does not explicitly teach wherein an error contour generated is stored in an analog memory. However, Kurokawa teaches an analog neural network wherein generated values updated by an error circuit are stored in an analog memory (fig. 7; ¶ [0092], [0106] – [0107], and [0129] – [0133]).
All of the claimed elements were known in Maliuk and Kurokawa and could have been combined by known methods with no change in their respective functions. It therefore would have been obvious to a person of ordinary skill in the art at the time of filing of the applicant’s invention to combine the analog memory of Kurokawa with the error contour of Maliuk to yield the predictable result of a neural network error contour generation mechanism wherein the error contour generated is stored in an analog memory. One would be motivated to make this combination for the purpose of reducing chip area and power consumption compared to digital implementations and DRAM-based analog memory structures (Kurokawa, ¶ [0014] and [0017]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Maliuk, as applied to claim 1, above, in view of Mirhassani, Mitra, Majid Ahmadi, and William C. Miller (“A feed-forward time-multiplexed neural network with mixed-signal neuron–synapse arrays,” Microelectronic engineering 84.2 (2007): 300-307; hereinafter “Mirhassani”).
Regarding Claim 11, Maliuk teaches analog bias values (section II. C, p. 73), but does not explicitly teach a circuit modifying analog bias values to direct the neural network error contour generation mechanism towards a target. However, Mirhassani teaches a circuit modifying bias values to direct the neural network error generation mechanism towards a target (p. 302 and fig. 3—training using perturbation based on the Madaline Rule III updates both weights and biases to direct the neural network error generation mechanism towards a target).
All of the claimed elements were known in Maliuk and Mirhassani and could have been combined by known methods with no change in their respective functions. It therefore would have been obvious to a person of ordinary skill in the art at the time of filing of the applicant’s invention to combine the bias updating of Mirhassani with neural network error contour generation mechanism and analog bias values of Maliuk to yield the predictable result of a circuit modifying analog bias values to direct the neural network error contour generation mechanism towards a target. One would be motivated to make this combination for the purpose of improving the speed and accuracy of training.
Allowable Subject Matter
Claim 5 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
None of the prior art of record teaches “The neural network error contour generation mechanism of claim 3, comprising means for generating errors for layers below an output layer by using one of switched charge multipliers or division and current mode summation circuits to generate error values by backpropagation through the layers” as recited by claim 5. Maliuk does not generate error values by backpropagation. Instead, as described in section II. E, Maliuk applies a random perturbation to all neurons and updates weights of the neurons if an error decreases (or does not increase by more than a function of the error and a temperature value). This mechanism is incompatible with a backpropagation process, which propagates error values backwards through a neural network to determine how neuron weights should be updated. It would not be obvious to modify the training method of Maliuk with art that teaches backpropagation because such a combination would change the principle of operation of Maliuk.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. This art includes:
Baker (U.S. 2020/0143240) teaches a neural network that calculates an error cost function using mini-batches for training with backpropagation
Jabri et al. (U.S. Patent 5,640,494) teaches an analog neural network that perturbs neurons to generate an error
Taha et al. (U.S. 2017/0011290) teaches a neural network that stores weights in analog memristor memory and performs backpropagation training
Schaul, Tom, Ioannis Antonoglou, and David Silver (“Unit tests for stochastic optimization,” arXiv preprint arXiv:1312.6055 (2013)) teaches using the curl of a vector field to optimize machine learning
Flower, Barry, and Marwan Jabri (“Summed weight neuron perturbation: An O (n) improvement over weight perturbation,” Advances in neural information processing systems 5 (1992)) teaches a neural network that uses summed weight neuron perturbation
Montalvo, Antonio J., Ronald S. Gyurcsik, and John J. Paulos (“An analog VLSI neural network with on-chip perturbation learning,” IEEE Journal of Solid-State Circuits 32.4 (2002): 535-543) teaches an analog neural network with perturbation learning that stores weights in dynamic memory until training achieves convergence, and then stores the weights to floating gates in the neurons
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAL W SCHNEE whose telephone number is (571) 270-1918. The examiner can normally be reached M-F 7:30 a.m. - 6:00 p.m.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Huntley can be reached on 303-297-4307. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAL SCHNEE/Primary Examiner, Art Unit 2129