DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Responsive to communications on 04/08/2024
Claims 1-20 pending in the application
Claim 1-20 are rejected
Claims 4-6, 7-17, and 20 are objected to
Priority
Application data sheet received on 02/08/2023 claims domestic priority to provisional application 63310419 filing date 02/15/2022. Application Data sheet accepted by the examiner.
Information Disclosure Statement
Responsive to IDS forms received on 01/23/2024 and 04/08/2024. IDS forms accepted by the examiner and all references considered.
Drawings
Responsive to drawings received on 02/08/2023. Drawings accepted by the examiner.
Specification
Responsive to amended specifications received on 01/03/2024. Specification accepted by the examiner.
Claim Objections
Claims 4-6, 7-17, and 20 are objected to for the reasons below:
Claims 4, 14, and 20 are objected to because of the following informalities: the claims stated “floating one or more other terminals” and then “measuring a voltage at one of the one or more floated terminals.” The claim should number the terminals such as in claim 5. For example “floating one or more of a third or fourth terminals” and then “measuring a voltage at one of the third of fourth terminals.” Appropriate correction is required.
Claims 5 and 16 are objected to because of the following informalities: The claim states “from a second result from the division.” Claims 4 and 14 also reference “the division.” The division of claim 5/16 and claim 4/14 are different divisions. The claim should reference “a second result from a second division”. Appropriate correction is required.
Claims 6 and 17 are objected to because of the following informalities: The claims state “from a third result of the division.” This is objected to for the same reasons as “the second result from the division” as stated above. The claim should reference “a third result from a third division” . Appropriate correction is required. Appropriate correction is required.
Claims 6 and 17 are objected to because of the following informalities: The claims state “applying a voltage between a counter-clockwise terminal from among the first terminal, the second terminal, and a fourth terminal of the internal circuit of the leaf cell and a terminal from among the first, second, and third terminals that is across from the missing third terminal,” It does not make sense that the third terminal is across from the missing third terminal, it seems the claim should be written as “from among the first, second, and fourth terminals that is across from the missing third terminal,” Appropriate correction is required.
Claim 7 is objected to for the following reasons. Claim 7 states “iteratively reduce number of resistors in each of the leaf cells by at least removing dangling resistors;” This was likely meant to be written as “iteratively reduce a number of resistors in each of the leaf cells by at least removing dangling resistors;” Appropriate correction is required.
Claims 8-13, and 15 are objected to for the dependency on the above objected to claims.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention recites a judicial exception, an abstract idea, which has not been integrated into practical application and the claims further do not recite significantly more than the judicial exception.
Claim 1
Step 1: Is the claimed invention one of the four statutory categories? :
YES. The claim recites the method comprising which is a process.
Step 2A Prong 1, inquiry "Is the claim directed to a law of nature, a natural phenomenon or an abstract idea?":
YES. Claim 1 recites: A method for transient analysis of a memory module circuit
The claim does not outline actionable steps towards perform transient analysis. Instead the claim states to perform transient analysis in a broad manner.
MPEP 2106.04(a)(2)(III)(B) states “If a claim recites a limitation that can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper, the limitation falls within the mental processes grouping, and the claim recites an abstract idea.”
In “Guide to Transient Analysis in SPICE Simulations for Electronics” by Zachariah Peterson, Peterson states page 2: “A basic transient analysis simulation is probably the easiest of all SPICE simulations to perform and understand. In principle, you can calculate the transient response in the above graph by hand as long as you have the circuit diagram, but the problem is often intractable (Examiner note: often but not always, under broadest reasonable interpretation and when defined broadly, this can be practically performed in the mind), which is why SPICE simulators come in handy. In circuit design, SPICE simulators are the primary tool for working with complex circuits that may have a range of circuit blocks and components.”
From the above passage, the examiner understands that performing a transient analysis, when described broadly and without actionable specific steps, is a process which can practically be performed in the human mind by pen and paper, especially because the circuit diagram (aka netlist) is evaluated and simplified later in the claim. Therefore This is a mental process which can be performed with pen and paper by drawing circuits.
determining port to port resistances between terminals of internal circuits of a plurality of leaf cells of a netlist representing the memory module circuit;
The netlist is a logical diagram or a machine readable file which describes the connections in a circuit. Par 64 of this specification “For example, FIG. TA illustrates an example logical netlist 100 representing a memory module generated by a memory compiler. In electronic design, a netlist is a description of the connectivity of an electronic circuit and includes a list of the electronic components in a circuit and a list of the nodes they are connected to. A netlist may be a machine readable file that contains all the connections between all the components in an electronic circuit design. For example, memory compilers are software tools that build different types and configurations of memories from the leaf cells.”
The actionable steps performed in this method pertain to a determination of port to port resistances between the terminals of internal circuits of leaf cells that exist inside of this descriptive netlist.
MPEP 2106.04(a)(2)(III)(B) states “If a claim recites a limitation that can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper, the limitation falls within the mental processes grouping, and the claim recites an abstract idea.”
The Department of Electrical and Computer Engineering at UCSB, Course ece2c, lecture two_port 2021 discusses determining resistances between ports. See page W2-6
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As demonstrated from the above, determining port to port resistances between ports, when derived from a netlist, is a process performed by one ordinarily skilled in electrical engineering and physics. This is often performed by students and researchers through diagramming and solving for mathematic equations which relate current, voltage, and resistance, when certain variables are already provided. This is a mental process which can be performed with pen and paper by drawing circuits. Therefore, this claim limitation recites an abstract idea pertaining to a mental process.
generating a plurality of equivalent networks corresponding to the internal circuits of the leaf cells, the equivalent networks being connected to each other;
The process of generating a plurality of equivalent networks, corresponding to the internal circuits of the lead cells, where the equivalent networks are connected to each other, is the process of taking the newly calculated port to port resistances to simplify the total resistance of a leaf cell and connect it to one circuit.
From the examiners understanding, this is the process of forming a “stitched netlist” as outlined in figure 1B.
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MPEP 2106.04(a)(2)(III)(B) states “If a claim recites a limitation that can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper, the limitation falls within the mental processes grouping, and the claim recites an abstract idea.”
As stated above, the netlist is a description of the connections for a circuit. This is not a physical circuit having its electrical wiring modified, but rather, this is a simplification process performed on a netlist to better interpret the resistances present across the different leaf cells.
The process then, of generating the equivalent networks, is the mental process described above used to calculate the current, resistance etc. through physics equations and then connecting the nodes together in the diagram description. This is a mental process which can be performed with pen and paper by drawing circuits. Therefore, this claim limitation recites an abstract idea pertaining to a mental process.
promoting the equivalent networks of the leaf cells to a hierarchical level above the leaf cells in the netlist representing the memory module circuit;
Promoting the equitant networks to a hierarchical level above the leaf cells in the netlist, as understood by the examiner, is a restructuring of the descriptive network pertaining to the memory module circuit. The examiner understands this process as what is demonstrated in fig 1.C
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MPEP 2106.04(a)(2)(III)(B) states “If a claim recites a limitation that can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper, the limitation falls within the mental processes grouping, and the claim recites an abstract idea.”
In “Computer Aids for VLSI Design” Rubin chapter 1 states par 1: “The first significant characteristic of VLSI and all other design is a heavy reliance on hierarchical description. The major reason for using hierarchical description is to hide the vast amount of detail in a design. By reducing the distracting detail to a single object that is lower in the hierarchy, one can greatly simplify many CAD operations. For example, simulation, verification, design-rule checking, and layout constraints can all benefit from hierarchical representation, which makes them much more computationally tractable.” … 1.2.2 par 1: “The most difficult problem that designers face is that of selecting a hierarchical organization for their circuit. This organization defines the way that the designer will think about the circuit, since layout is typically examined one hierarchical level at a time. “
As already stated, this is not a modification of a physical circuit. This is a restructuring of a logical description of the connections in the circuit. This promotion is modifying the description to state that the equivalent networks are not a part of leaf cells. For instance, the netlist will not longer describe the signal passing through a connection with leaf cells, instead, the user of the invention will deduce the actual resistance loss caused by these leaf cells, and approximate them directly into the netlist. This is a mental process which can be performed with pen and paper by drawing circuits, which is also normally performed by one ordinarily skilled in the art when designing circuits for simulations.
shorting one or more terminals of each of the leaf cells to a central node of a corresponding one of the equivalent networks;
As understood by the examiner, “shorting terminals” in this context refers to a mock deletion of terminals off of a netlist after already determining the equivalent resistances. This is done to prevent double counting. This is the same mental process already performed above, with an additional step of modifying the netlist to short the now redundant terminals. This is a mental process which can be performed with pen and paper by drawing circuits.
and performing the transient analysis of the leaf cells of the netlist representing the memory module circuit.
As stated above, the claim does not outline actionable steps towards perform transient analysis. Instead the claim states to perform transient analysis in a broad manner.
MPEP 2106.04(a)(2)(III)(B) states “If a claim recites a limitation that can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper, the limitation falls within the mental processes grouping, and the claim recites an abstract idea.”
In “Guide to Transient Analysis in SPICE Simulations for Electronics” by Zachariah Peterson, Peterson states page 2: “A basic transient analysis simulation is probably the easiest of all SPICE simulations to perform and understand. In principle, you can calculate the transient response in the above graph by hand as long as you have the circuit diagram, but the problem is often intractable (Examiner note: often but not always), which is why SPICE simulators come in handy. In circuit design, SPICE simulators are the primary tool for working with complex circuits that may have a range of circuit blocks and components.”
From the above passage, the examiner understands that performing a transient analysis, when described broadly and without actionable specific steps, is a process which can practically be performed in the human mind by pen and paper, especially because the circuit diagram (aka netlist) is evaluated and simplified earlier in the claim. Therefore This is a mental process which can be performed with pen and paper by drawing circuits.
Step 2A Prong 2, Does the claim recite additional elements that integrate the judicial exception into a practical application?
NO. Claim 1 additionally recites the leaf cells … memory module circuit
As stated above, the simplification of the circuit given a netlist is a mental process. The claim states additional elements, that the work of analyzing a is done on a netlist which contains leaf cells and represents a memory module circuit.
The MPEP 2106.05(g) outlines examples of insignificant and extra solution activity. With an example being “Selecting a particular data source or type of data to be manipulated:” One example given is “iii. Selecting information, based on types of information and availability of information in a power-grid environment, for collection, analysis and display, Electric Power Group, LLC v. Alstom S.A., 830 F.3d 1350, 1354-55, 119 USPQ2d 1739, 1742 (Fed. Cir. 2016); and”
The examiner views these limitations as being similar to the above examples, where this claim is directed to the analysis of netlist data, based on a memory module circuit and leaf cells present.
In order to determine if the limitations above are Insignificant Extra-solution activity, the MPEP 2106.05(g)(2) also considers “Whether the limitation is significant (i.e. it imposes meaningful limits on the claim such that it is not nominally or tangentially related to the invention).”
The inclusion of leaf cells and memory module circuits are insignificant limitation to the invention. Since these are examples of circuits, and components of circuits, which are the primary components for transient analysis.
Therefore, this limitation will be further addressed in Step 2B
Step 2B, does the claim recites additional elements that amount to significantly more than the judicial exception.
NO. In step 2B, the examiner will evaluate whether or not the above additional limitations are well known in the art.
In “Computer Aids for VLSI Design” Rubin chapter 1 par 3 states :”Certain terms are used commonly in describing hierarchy. A cell that does not contain any instances of other cells is at the bottom of the hierarchy and is called a leaf cell.”
Also in section 1.2.2 Rubin states “For example, suppose that a 4K memory chip is to be designed, and further suppose that the design for a single bit of that memory is already done. Since the size of this bit of memory is the most important factor in the chip, all other circuitry must be designed to accommodate this cell. Therefore the design composition must proceed in a bottom-up manner, starting with the single bit of memory (see Fig. 1.14). In this example there are six levels of hierarchy starting at the single bit, aggregating a row of eight bits; stacking four of those vertically; stacking eight at the next higher level; and so on. The highest level of the hierarchy shows four arrays, each containing 32 × 32 bits. Memory-driving circuitry with the correct spacing is then placed around the bits.”
Where the examiner notes that memory module circuitry is well known in the art of circuits, and also that the above passage implies that leaf cells are known and considered in the art.
Therefore the above extra limitations are well known in the art and are considered insignificant extra solution activity.
Based on the above facts, the office concludes that claim 1 is not eligible under 35 USC 101.
Claim 2:The method of claim 1, wherein the internal circuits of the leaf cells comprise one or more parasitic resistances of the leaf cells,
This limitation pertains to the internal circuits present in the netlist which are being analyzed by the judicial exception. From the examiners understanding, the term parasitic resistances refers to an inherent resistance present in the leaf cells. This is information present in the netlist. As already stated, the analysis of the netlist was determined to recite a mental process performed by a pen and paper, the presence of resistance information, whether or not the information is labeled as parasitic, does not influence that outcome. Therefore, this limitation is a further recitation of the above mental process.
and wherein the equivalent networks comprise one or more equivalent resistances corresponding to the one or more parasitic resistances of the leaf cells.
As stated above, the equivalent networks is a simplification process performed on a netlist to better interpret the resistances present across the different leaf cells. Whether the resistances present encompass parasitic resistances, which are inherent to the leaf cells, does not influence the process as outlined. Therefore, this limitation is a further recitation of the above mental process.
Based on the above facts, the office concludes that claim 2 is not eligible under 35 USC 101.
Claim 3:
The method of claim 2, wherein promoting the equivalent networks of the leaf cells comprises connecting the one or more equivalent resistances corresponding to the one or more parasitic resistances of the leaf cells outside the leaf cells at inputs of the leaf cells.
As previously stated, From the examiners understanding, the term parasitic resistances refers to an inherent resistance present in the leaf cells. This is information present in the netlist. As stated above, connecting the equivalent resistances is the mental process described above used to calculate the current, resistance etc. through physics equations and then connecting the nodes together in the diagram description. This is a mental process which can be performed with pen and paper by drawing circuits, regardless if the resistances are considered to be parasitic. Therefore, this limitation is a further recitation of the above mental process.
Based on the above facts, the office concludes that claim 3 is not eligible under 35 USC 101.
Claim 4:
The method of claim 1, wherein the port to port resistances between the terminals of the internal circuits of the leaf cells are determined based on (see claim 1)
a DC simulation of the leaf cells by:
When recited at a high degree of generality. A “DC simulation of the leaf cells” encompasses a static analysis of the components of the leaf cells in relation to voltage, current, and resistance. The MPEP 2106.04(a)(2)(III)(B) states “If a claim recites a limitation that can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper, the limitation falls within the mental processes grouping, and the claim recites an abstract idea.” A personal ordinarily skilled in the art can perform a DC analysis using governing physics equations with a model circuit laid out on a piece of paper. Therefore this claim limitation is a further recitation of an abstract idea.
applying a voltage between a first terminal and a second terminal of each of the internal circuits of the leaf cells to determine an applied voltage and floating one or more other terminals of each of the internal circuits of the leaf cells;
As understood by the examiner, this is a simulation, not a real circuit terminal being tested. There is not a physical voltage being applied to the circuit, this is a “conceptual” voltage applied to a simulated circuit. Furthermore, when the claim states “floating” in the context of a simulation, it is understood as making the current 0 through those terminals. The MPEP 2106.04(a)(2)(III) states “Accordingly, the "mental processes" abstract idea grouping is defined as concepts performed in the human mind, and examples of mental processes include observations, evaluations, judgments, and opinions. “
And MPEP 2106.04(a)(2)(III)(B) states “If a claim recites a limitation that can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper, the limitation falls within the mental processes grouping, and the claim recites an abstract idea.” This claim limitation encompasses a user making a decision of what the voltage should be for the circuit and writing it down on the simulation. Therefore this claim limitation is a further recitation of an abstract idea.
determining a first resistance value between the first and second terminals by dividing the measured voltage by the measured current; and
The MPEP 2106.04(a)(2)(I)(C) states “A claim that recites a mathematical calculation, when the claim is given its broadest reasonable interpretation in light of the specification, will be considered as falling within the "mathematical concepts" grouping. A mathematical calculation is a mathematical operation (such as multiplication) or an act of calculating using mathematical methods to determine a variable or number, e.g., performing an arithmetic operation such as exponentiation. There is no particular word or set of words that indicates a claim recites a mathematical calculation. That is, a claim does not have to recite the word "calculating" in order to be considered a mathematical calculation. For example, a step of "determining" a variable or number using mathematical methods or "performing" a mathematical operation may also be considered mathematical calculations when the broadest reasonable interpretation of the claim in light of the specification encompasses a mathematical calculation.” This is a recitation of a mathematic calculation.
determining a second resistance value between the first and second terminals by dividing the applied voltage by the measured current and subtracting the first resistance value from a result from the division.
The MPEP 2106.04(a)(2)(I)(C) states “A claim that recites a mathematical calculation, when the claim is given its broadest reasonable interpretation in light of the specification, will be considered as falling within the "mathematical concepts" grouping. A mathematical calculation is a mathematical operation (such as multiplication) or an act of calculating using mathematical methods to determine a variable or number, e.g., performing an arithmetic operation such as exponentiation. There is no particular word or set of words that indicates a claim recites a mathematical calculation. That is, a claim does not have to recite the word "calculating" in order to be considered a mathematical calculation. For example, a step of "determining" a variable or number using mathematical methods or "performing" a mathematical operation may also be considered mathematical calculations when the broadest reasonable interpretation of the claim in light of the specification encompasses a mathematical calculation.” This is a recitation of a mathematic calculation.
Additional elements:
measuring a current between the first and second terminals of each of the internal circuits of the leaf cells to determine a measured current;
As understood by the examiner, this measurement is being performed by a simulation software. This is a collection of data related to the circuit to be used in calculating the resistance. The MPEP 2106.05(h) states “ limitations that amount to merely indicating a field of use or technological environment in which to apply a judicial exception do not amount to significantly more than the exception itself, and cannot integrate a judicial exception into a practical application” with an example given of “Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection and analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment,” Because this limitation is related to collecting information for analysis (measuring a current to determine resistance, at a high degree of generality without physical components performing the action) the claim is directed to claiming a field of use and does not amount to significantly more than the exception itself.
measuring a voltage at one of the one or more floated terminals of each of the internal circuits of the leaf cells to determine a measured voltage;
As understood by the examiner, this measurement is being performed by a simulation software. This is a collection of data related to the circuit to be used in calculating the resistance. The MPEP 2106.05(h) states “ limitations that amount to merely indicating a field of use or technological environment in which to apply a judicial exception do not amount to significantly more than the exception itself, and cannot integrate a judicial exception into a practical application” with an example given of “Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection and analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment,” Because this limitation is related to collecting information for analysis (measuring a voltage to determine resistance, at a high degree of generality without physical components performing the action) the claim is directed to claiming a field of use and does not amount to significantly more than the exception itself.
Claim 5:
Claim 5 is an effective duplicate of claim 4, except it describes a process of further analysis, where the steps of claim 4 are repeated for the “other” terminals. This does not modify the judicial exceptions or field of use activities mentioned above in claim 4. Therefore claim 5 is rejected in light of the rejection of claim 4 under a similar rational.
Claim 6:
The method of claim 4, further comprising:
determining that an internal circuit from among the internal circuits of the leaf cells is missing a third terminal;
MPEP 2106.04(a)(2)(III) states “Accordingly, the "mental processes" abstract idea grouping is defined as concepts performed in the human mind, and examples of mental processes include observations, evaluations, judgments, and opinions. “ This claim is directed to an observation and evaluation which can be performed by a human when stated at a high degree of generality. Therefore this claim recites an abstract idea of a mental process.
applying a voltage between a counter-clockwise terminal from among the first terminal, the second terminal, and a fourth terminal of the internal circuit of the leaf cell and a terminal from among the first, second, and third terminals that is across from the missing third terminal, the counter-clockwise terminal being in a counter-clockwise position from the missing third terminal;
As understood by the examiner, this is a simulation, not a real circuit terminal being tested. There is not a physical voltage being applied to the circuit, this is a “conceptual” voltage applied to a simulated circuit. Furthermore, when the claim states “floating” in the context of a simulation, it is understood as making the current 0 through those terminals. The MPEP 2106.04(a)(2)(III) states “Accordingly, the "mental processes" abstract idea grouping is defined as concepts performed in the human mind, and examples of mental processes include observations, evaluations, judgments, and opinions. “
And MPEP 2106.04(a)(2)(III)(B) states “If a claim recites a limitation that can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper, the limitation falls within the mental processes grouping, and the claim recites an abstract idea.” This claim limitation encompasses a user making a decision of what the voltage should be for the circuit and writing it down on the simulation. Therefore this claim limitation is a further recitation of an abstract idea.
and determining a resistance of the terminal across from the missing third terminal by dividing the voltage at the clockwise terminal by the current between the counter-clockwise terminal and the terminal across from the missing third terminal, and subtracting a resistance of the counter-clockwise terminal from a third result of the division.
The MPEP 2106.04(a)(2)(I)(C) states “A claim that recites a mathematical calculation, when the claim is given its broadest reasonable interpretation in light of the specification, will be considered as falling within the "mathematical concepts" grouping. A mathematical calculation is a mathematical operation (such as multiplication) or an act of calculating using mathematical methods to determine a variable or number, e.g., performing an arithmetic operation such as exponentiation. There is no particular word or set of words that indicates a claim recites a mathematical calculation. That is, a claim does not have to recite the word "calculating" in order to be considered a mathematical calculation. For example, a step of "determining" a variable or number using mathematical methods or "performing" a mathematical operation may also be considered mathematical calculations when the broadest reasonable interpretation of the claim in light of the specification encompasses a mathematical calculation.” This is a recitation of a mathematic calculation.
Additional Elements:
measuring a current between the counter-clockwise terminal and the terminal across from the missing third terminal;
As understood by the examiner, this measurement is being performed by a simulation software. This is a collection of data related to the circuit to be used in calculating the resistance. The MPEP 2106.05(h) states “ limitations that amount to merely indicating a field of use or technological environment in which to apply a judicial exception do not amount to significantly more than the exception itself, and cannot integrate a judicial exception into a practical application” with an example given of “Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection and analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment,” Because this limitation is related to collecting information for analysis (measuring a current to determine resistance, at a high degree of generality without physical components performing the action) the claim is directed to claiming a field of use and does not amount to significantly more than the exception itself.
measuring a voltage at a clockwise terminal from among the first, second, and fourth terminals, the clockwise terminal being in a clockwise position from the missing third terminal;
As understood by the examiner, this measurement is being performed by a simulation software. This is a collection of data related to the circuit to be used in calculating the resistance. The MPEP 2106.05(h) states “ limitations that amount to merely indicating a field of use or technological environment in which to apply a judicial exception do not amount to significantly more than the exception itself, and cannot integrate a judicial exception into a practical application” with an example given of “Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection and analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment,” Because this limitation is related to collecting information for analysis (measuring a voltage to determine resistance, at a high degree of generality without physical components performing the action) the claim is directed to claiming a field of use and does not amount to significantly more than the exception itself.
Claim 7:
Step 1: Is the claimed invention one of the four statutory categories? :
YES. The claim recites “the system comprising” which is a machine.
Step 2A Prong 1, inquiry "Is the claim directed to a law of nature, a natural phenomenon or an abstract idea?":
YES. Claim 1 recites A system for transient analysis of a memory module circuit
The claim does not outline actionable steps towards perform transient analysis. Instead the claim states to perform transient analysis in a broad manner.
MPEP 2106.04(a)(2)(III)(B) states “If a claim recites a limitation that can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper, the limitation falls within the mental processes grouping, and the claim recites an abstract idea.”
In “Guide to Transient Analysis in SPICE Simulations for Electronics” by Zachariah Peterson, Peterson states page 2: “A basic transient analysis simulation is probably the easiest of all SPICE simulations to perform and understand. In principle, you can calculate the transient response in the above graph by hand as long as you have the circuit diagram, but the problem is often intractable (Examiner note: often but not always), which is why SPICE simulators come in handy. In circuit design, SPICE simulators are the primary tool for working with complex circuits that may have a range of circuit blocks and components.”
From the above passage, the examiner understands that performing a transient analysis, when described broadly and without actionable specific steps, is a process which can practically be performed in the human mind by pen and paper, especially because the circuit diagram (aka netlist) is evaluated and simplified earlier in the claim. Therefore This is a mental process which can be performed with pen and paper by drawing circuits.
remove one or more transistors and capacitors in each of a plurality of leaf cells of a netlist representing the memory module circuit;
The netlist is a logical diagram or a machine readable file which describes the connections in a circuit. Par 64 of this specification “For example, FIG. TA illustrates an example logical netlist 100 representing a memory module generated by a memory compiler. In electronic design, a netlist is a description of the connectivity of an electronic circuit and includes a list of the electronic components in a circuit and a list of the nodes they are connected to. A netlist may be a machine readable file that contains all the connections between all the components in an electronic circuit design. For example, memory compilers are software tools that build different types and configurations of memories from the leaf cells.”
The examiner understands this limitation like in steps 520 and 530.
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The actionable steps performed in this method step is the removal of descriptive components in a netlist. This is not a physical removal or modification of a circuit. Instead, this claim encompasses using a pencil to erase components of a diagram or deleting components in a machine readable description.
MPEP 2106.04(a)(2)(III)(B) states “If a claim recites a limitation that can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper, the limitation falls within the mental processes grouping, and the claim recites an abstract idea.”
As outlined this step encompasses the process of modifying a netlist. This is a mental process which can be performed with pen and paper by drawing circuits. Therefore, this claim limitation recites an abstract idea pertaining to a mental process.
iteratively reduce number of resistors in each of the leaf cells by at least removing dangling resistors;
Similarly to the step recited above, the actionable step performed in this method step is the further removal of descriptive components in a netlist. This is not a physical removal or modification of a circuit. Instead, this claim encompasses using a pencil to erase components of a diagram or deleting components in a machine readable description.
MPEP 2106.04(a)(2)(III)(B) states “If a claim recites a limitation that can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper, the limitation falls within the mental processes grouping, and the claim recites an abstract idea.”
As outlined this step encompasses the process of modifying a netlist. This is a mental process which can be performed with pen and paper by drawing circuits. Therefore, this claim limitation recites an abstract idea pertaining to a mental process.
generate equivalent networks corresponding to internal circuits of the leaf cells;
The process of generating a plurality of equivalent networks, corresponding to the internal circuits of the lead cells, where the equivalent networks are connected to each other, is the process of taking the newly calculated port to port resistances to simplify the total resistance of a leaf cell and connect it to one circuit.
From the examiners understanding, this is the process of forming a “stitched netlist” as outlined in figure 1B.
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MPEP 2106.04(a)(2)(III)(B) states “If a claim recites a limitation that can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper, the limitation falls within the mental processes grouping, and the claim recites an abstract idea.”
As stated above, the netlist is a description of the connections for a circuit. This is not a physical circuit having its electrical wiring modified, but rather, this is a simplification process performed on a netlist to better interpret the resistances present across the different leaf cells.
The process then, of generating the equivalent networks, is the mental process described above used to calculate the current, resistance etc. through physics equations and then connecting the nodes together in the diagram description. This is a mental process which can be performed with pen and paper by drawing circuits. Therefore, this claim limitation recites an abstract idea pertaining to a mental process.
promote the equivalent networks of the leaf cells to a hierarchical level above the leaf cells in the memory module circuit;
Promoting the equitant networks to a hierarchical level above the leaf cells in the netlist, as understood by the examiner, is a restructuring of the descriptive network pertaining to the memory module circuit. The examiner understands this process as what is demonstrated in fig 1.C
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MPEP 2106.04(a)(2)(III)(B) states “If a claim recites a limitation that can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper, the limitation falls within the mental processes grouping, and the claim recites an abstract idea.”
In “Computer Aids for VLSI Design” Rubin chapter 1 states par 1: “The first significant characteristic of VLSI and all other design is a heavy reliance on hierarchical description. The major reason for using hierarchical description is to hide the vast amount of detail in a design. By reducing the distracting detail to a single object that is lower in the hierarchy, one can greatly simplify many CAD operations. For example, simulation, verification, design-rule checking, and layout constraints can all benefit from hierarchical representation, which makes them much more computationally tractable.” … 1.2.2 par 1: “The most difficult problem that designers face is that of selecting a hierarchical organization for their circuit. This organization defines the way that the designer will think about the circuit, since layout is typically examined one hierarchical level at a time. “
As already stated, this is not a modification of a physical circuit. This is a restructuring of a logical description of the connections in the circuit. This promotion is modifying the description to state that the equivalent networks are not a part of leaf cells. For instance, the netlist will no longer describe the signal passing through a connection with leaf cells, instead, the user of the invention will deduce the actual resistance loss caused by these leaf cells, and approximate them directly into the netlist. This is a mental process which can be performed with pen and paper by drawing circuits, which is also normally performed by one ordinarily skilled in the art when designing circuits for simulations
and perform the transient analysis of the leaf cells of the netlist representing the memory module circuit.
The claim does not outline actionable steps towards perform transient analysis. Instead the claim states to perform transient analysis in a broad manner.
MPEP 2106.04(a)(2)(III)(B) states “If a claim recites a limitation that can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper, the limitation falls within the mental processes grouping, and the claim recites an abstract idea.”
In “Guide to Transient Analysis in SPICE Simulations for Electronics” by Zachariah Peterson, Peterson states page 2: “A basic transient analysis simulation is probably the easiest of all SPICE simulations to perform and understand. In principle, you can calculate the transient response in the above graph by hand as long as you have the circuit diagram, but the problem is often intractable (Examiner note: often but not always), which is why SPICE simulators come in handy. In circuit design, SPICE simulators are the primary tool for working with complex circuits that may have a range of circuit blocks and components.”
From the above passage, the examiner understands that performing a transient analysis, when described broadly and without actionable specific steps, is a process which can practically be performed in the human mind by pen and paper, especially because the circuit diagram (aka netlist) is evaluated and simplified earlier in the claim. Therefore This is a mental process which can be performed with pen and paper by drawing circuits.
Step 2A Prong 2, Does the claim recite additional elements that integrate the judicial exception into a practical application?
NO. Claim 1 additionally recites a memory storing instructions;
and a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
This limitation describes the computer hardware used to perform the instructions which were determined to recite judicial exceptions. The MPEP 2106.05(f)(2) states “Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more.” Therefore this limitation does not integrate the judicial exception into a practical application or provide significantly more.
Transistors … capacitors
This limitation refers to what is being deleted in the netlist, which was determined to be a mental process. The MPEP 2106.05(h) states “limitations that amount to merely indicating a field of use or technological environment in which to apply a judicial exception do not amount to significantly more than the exception itself, and cannot integrate a judicial exception into a practical application” The examiner interprets this limitation as stating that the netlist belongs to the field of electronic circuits, which is interpreted as merely indicating the technological environment in which to apply the judicial exception of modifying a netlist. Therefore this limitation does not amount to significantly more than the exception itself, and cannot integrate a judicial exception into a practical application
the leaf cells … memory module circuit
As stated above, the simplification of the circuit given a netlist is a mental process. The claim states additional elements, that the netlist contains leaf cells and represents a memory module circuit.
The MPEP 2106.05(g) outlines examples of insignificant and extra solution activity. With an example being “Selecting a particular data source or type of data to be manipulated:” One example given is “iii. Selecting information, based on types of information and availability of information in a power-grid environment, for collection, analysis and display, Electric Power Group, LLC v. Alstom S.A., 830 F.3d 1350, 1354-55, 119 USPQ2d 1739, 1742 (Fed. Cir. 2016); and”
The examiner views these limitations as being similar to the above examples, where this claim is directed to the analysis of netlist data, based on a memory module circuit and leaf cells present.
In order to determine if the limitations above are Insignificant Extra-solution activity, the MPEP 2106.05(g)(2) also considers “Whether the limitation is significant (i.e. it imposes meaningful limits on the claim such that it is not nominally or tangentially related to the invention).”
The inclusion of leaf cells and memory module circuits are insignificant limitation to the invention. Since these are examples of circuits, and components of circuits, which are the primary components for transient analysis.
Therefore, this limitation will be further addressed in Step 2B
Step 2B, does the claim recites additional elements that amount to significantly more than the judicial exception.
NO. As stated in Step 2A Prong 2, the leaf cells … memory module circuit
In step 2B, the examiner will evaluate whether or not the above limitations are well known in the art.
In “Computer Aids for VLSI Design” Rubin chapter 1 par 3 states :”Certain terms are used commonly in describing hierarchy. A cell that does not contain any instances of other cells is at the bottom of the hierarchy and is called a leaf cell.”
Also in section 1.2.2 Rubin states “For example, suppose that a 4K memory chip is to be designed, and further suppose that the design for a single bit of that memory is already done. Since the size of this bit of memory is the most important factor in the chip, all other circuitry must be designed to accommodate this cell. Therefore the design composition must proceed in a bottom-up manner, starting with the single bit of memory (see Fig. 1.14). In this example there are six levels of hierarchy starting at the single bit, aggregating a row of eight bits; stacking four of those vertically; stacking eight at the next higher level; and so on. The highest level of the hierarchy shows four arrays, each containing 32 × 32 bits. Memory-driving circuitry with the correct spacing is then placed around the bits.”
Where the examiner notes that memory module circuitry is well known in the art of circuits, and also that the above passage implies that leaf cells are known and considered in the art.
Therefore the above extra limitations are well known in the art and are considered insignificant extra solution activity.
Based on the above facts, the office concludes that claim 7 is not eligible under 35 USC 101.
Claim 8:
The system of claim 7, wherein the processor is further configured to:
determine the internal circuits of the leaf cells, each of the internal circuits comprising one or more remaining resistors after the iterative reduction of the resistors in each of the leaf cells.
From the examiners understanding and when recited broadly, the step of determining the internal circuit of the lead cell encompasses determining what is remaining after the iterative reduction. This is the process of observing the resulting netlist.
MPEP 2106.04(a)(2)(III) states “Accordingly, the "mental processes" abstract idea grouping is defined as concepts performed in the human mind, and examples of mental processes include observations, evaluations, judgments, and opinions. “
Therefore this claim limitation is a further recitation of a mental process.
Based on the above facts, the office concludes that claim 8 is not eligible under 35 USC 101.
Claim 9:
The system of claim 7, wherein a total number of resistors in each of the leaf cells are further iteratively reduced by combining serial, parallel, and triode resistor configurations in the internal circuits of each of the leaf cells.
As stated previously, the reduction of resistors in leaf cells is the mental process of modifying a netlist.
The process of combining serial, parallel, and triode resistor configurations as understood by the examiner is the methodology used to perform this modification. As understood by one normally skilled in the art, this combination is not a physical combination of pieces being performed, rather, it is a mental simplification process used to simplify the internal configuration of the circuits based on circuit diagrams.
MPEP 2106.04(a)(2)(III)(B) states “If a claim recites a limitation that can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper, the limitation falls within the mental processes grouping, and the claim recites an abstract idea.”
Because this claim limitations pertains to performing the mental process of modifying a netlist, this claim is a further recitation of a mental process.
Based on the above facts, the office concludes that claim 9 is not eligible under 35 USC 101.
Claim 10:The system of claim 7, wherein the processor is further configured to:
determine port to port resistances between terminals of the internal circuits of the leaf cells;
The netlist is a logical diagram or a machine readable file which describes the connections in a circuit. Par 64 of this specification “For example, FIG. TA illustrates an example logical netlist 100 representing a memory module generated by a memory compiler. In electronic design, a netlist is a description of the connectivity of an electronic circuit and includes a list of the electronic components in a circuit and a list of the nodes they are connected to. A netlist may be a machine readable file that contains all the connections between all the components in an electronic circuit design. For example, memory compilers are software tools that build different types and configurations of memories from the leaf cells.”
The actionable steps performed in this method pertain to a determination of port to port resistances between the terminals of internal circuits of leaf cells that exist inside of this descriptive netlist.
MPEP 2106.04(a)(2)(III)(B) states “If a claim recites a limitation that can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper, the limitation falls within the mental processes grouping, and the claim recites an abstract idea.”
The Department of Electrical and Computer Engineering at UCSB, Course ece2c, lecture two_port 2021 discusses determining resistances between ports. See page W2-6
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As demonstrated from the above, determining port to port resistances between ports, when derived from a netlist, is a process performed by one ordinarily skilled in electrical engineering and physics. This is often performed by students and researchers through diagramming and solving for mathematic equations which relate current, voltage, and resistance, when certain variables are already provided. This is a mental process which can be performed with pen and paper by drawing circuits. Therefore, this claim limitation recites an abstract idea pertaining to a mental process.
and short one or more terminals of each of the leaf cells to a central node of a corresponding one of the equivalent networks.
As understood by the examiner, “shorting terminals” in this context refers to a mock deletion of terminals off of a netlist after already determining the equivalent resistances. This is done to prevent double counting. This is the same mental process already performed above, with an additional step of modifying the netlist to short the now redundant terminals to a central node. This is a mental process which can be performed with pen and paper by drawing circuits.
Based on the above facts, the office concludes that claim 10 is not eligible under 35 USC 101.
Claim 11:
The system of claim 10, wherein the equivalent networks corresponding to the internal circuits of the leaf cells are generated based on the port to port resistances between the terminals of the internal circuits of the leaf cells.
As stated in the claim above, determining port to port resistances between ports, when derived from a netlist, is a process performed by one ordinarily skilled in electrical engineering and physics. This is often performed by students and researchers through diagramming and solving for mathematic equations which relate current, voltage, and resistance, when certain variables are already provided. This is a mental process which can be performed with pen and paper by drawing circuits.
Secondly, of generating the equivalent networks, is the mental process described above used to calculate the current, resistance etc. through physics equations and then connecting the nodes together in the diagram description. This is a mental process which can be performed with pen and paper by drawing circuits.
The process of generating the equivalent networks based on the port to port resistances is therefore the mental process of generating an equivalent network based on a mathematic value (the port to port resistances). For example, the equivalent network will be equivalent to the sum of the port to port resistances. Therefore, this claim limitation is a further recitation towards the abstract idea of generating equivalent networks.
Based on the above facts, the office concludes that claim 11 is not eligible under 35 USC 101.
Claim 12:
The system of claim 10, wherein the internal circuits of the leaf cells comprise one or more parasitic resistances of the leaf cells,
This limitation pertains to the internal circuits present in the netlist which are being analyzed by the judicial exception. From the examiners understanding, the term parasitic resistances refers to an inherent resistance present in the leaf cells. This is information present in the netlist. As already stated, the analysis of the netlist was determined to recite a mental process performed by a pen and paper, the presence of resistance information, whether or not the information is labeled as parasitic, does not influence that outcome. Therefore, this limitation is a further recitation of the above mental process.
and wherein the equivalent networks comprise one or more equivalent resistances corresponding to the one or more parasitic resistances of the leaf cells.
As stated above, the equivalent networks is a simplification process performed on a netlist to better interpret the resistances present across the different leaf cells. Whether the resistances present encompass parasitic resistances, which are inherent to the leaf cells, does not influence the process as outlined. Therefore, this limitation is a further recitation of the above mental process.
Based on the above facts, the office concludes that claim 12 is not eligible under 35 USC 101.
Claim 13:The system of claim 12, wherein promoting the equivalent networks of the leaf cells comprises connecting the one or more equivalent resistances corresponding to the one or more parasitic resistances of the leaf cells outside the leaf cells at an input of each of the leaf cells.
As previously stated, From the examiners understanding, the term parasitic resistances refers to an inherent resistance present in the leaf cells. This is information present in the netlist. As stated above, connecting the equivalent resistances is the mental process described above used to calculate the current, resistance etc. through physics equations and then connecting the nodes together in the diagram description. This is a mental process which can be performed with pen and paper by drawing circuits, regardless if the resistances are considered to be parasitic. Therefore, this limitation is a further recitation of the above mental process.
Based on the above facts, the office concludes that claim 13 is not eligible under 35 USC 101.
Claim 14:
Claim 14 is greater in scope to claim 4, where claim 4 contains all the limitations of claim 14, except that claim 14 depends on claim 10. Therefore, claim 14 is rejected under the same rational as claim 4 and 10.
Claim 15:
Claim 15 is effectively similar to claim 4, except that it depends on claim 14. Therefore, claim 15 is rejected under the same rational as claims 4 and 14.
Claim 16:
Claim 16 is effectively similar to claim 5, except that it depends on claim 14. Therefore, claim 16 is rejected under the same rational as claims 5 and 14.
Claim 17:
Claim 17 is effectively similar to claim 6, except that it depends from claim 15. Therefore, claim 17 is rejected under the same rational as claims 6 and 17.
Claim 18
Step 1: Is the claimed invention one of the four statutory categories? :
YES. The claim recites A non-transitory computer readable medium which is an article of manufacture.
Step 2A Prong 1, inquiry "Is the claim directed to a law of nature, a natural phenomenon or an abstract idea?":
YES. Claim 18 recites generate equivalent networks corresponding to internal circuits of a plurality of leaf cells of a netlist representing a memory module circuit;
The process of generating a plurality of equivalent networks, corresponding to the internal circuits of the lead cells, where the equivalent networks are connected to each other, is the process of taking the newly calculated port to port resistances to simplify the total resistance of a leaf cell and connect it to one circuit.
From the examiners understanding, this is the process of forming a “stitched netlist” as outlined in figure 1B.
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MPEP 2106.04(a)(2)(III)(B) states “If a claim recites a limitation that can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper, the limitation falls within the mental processes grouping, and the claim recites an abstract idea.”
As stated above, the netlist is a description of the connections for a circuit. This is not a physical circuit having its electrical wiring modified, but rather, this is a simplification process performed on a netlist to better interpret the resistances present across the different leaf cells.
The process then, of generating the equivalent networks, is the mental process described above used to calculate the current, resistance etc. through physics equations and then connecting the nodes together in the diagram description. This is a mental process which can be performed with pen and paper by drawing circuits. Therefore, this claim limitation recites an abstract idea pertaining to a mental process.
promote the equivalent networks of the leaf cells to a hierarchical level above the leaf cells in the memory module circuit;
Promoting the equivalent networks to a hierarchical level above the leaf cells in the netlist, as understood by the examiner, is a restructuring of the descriptive network pertaining to the memory module circuit. The examiner understands this process as what is demonstrated in fig 1.C
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MPEP 2106.04(a)(2)(III)(B) states “If a claim recites a limitation that can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper, the limitation falls within the mental processes grouping, and the claim recites an abstract idea.”
In “Computer Aids for VLSI Design” Rubin chapter 1 states par 1: “The first significant characteristic of VLSI and all other design is a heavy reliance on hierarchical description. The major reason for using hierarchical description is to hide the vast amount of detail in a design. By reducing the distracting detail to a single object that is lower in the hierarchy, one can greatly simplify many CAD operations. For example, simulation, verification, design-rule checking, and layout constraints can all benefit from hierarchical representation, which makes them much more computationally tractable.” … 1.2.2 par 1: “The most difficult problem that designers face is that of selecting a hierarchical organization for their circuit. This organization defines the way that the designer will think about the circuit, since layout is typically examined one hierarchical level at a time. “
As already stated, this is not a modification of a physical circuit. This is a restructuring of a logical description of the connections in the circuit. This promotion is modifying the description to state that the equivalent networks are not a part of leaf cells. For instance, the netlist will not longer describe the signal passing through a connection with leaf cells, instead, the user of the invention will deduce the actual resistance loss caused by these leaf cells, and approximate them directly into the netlist. This is a mental process which can be performed with pen and paper by drawing circuits, which is also normally performed by one ordinarily skilled in the art when designing circuits for simulations.
and perform a transient analysis of the leaf cells of the netlist representing the memory module circuit.
The claim does not outline actionable steps towards perform transient analysis. Instead the claim states to perform transient analysis in a broad manner.
MPEP 2106.04(a)(2)(III)(B) states “If a claim recites a limitation that can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper, the limitation falls within the mental processes grouping, and the claim recites an abstract idea.”
In “Guide to Transient Analysis in SPICE Simulations for Electronics” by Zachariah Peterson, Peterson states page 2: “A basic transient analysis simulation is probably the easiest of all SPICE simulations to perform and understand. In principle, you can calculate the transient response in the above graph by hand as long as you have the circuit diagram, but the problem is often intractable (Examiner note: often but not always), which is why SPICE simulators come in handy. In circuit design, SPICE simulators are the primary tool for working with complex circuits that may have a range of circuit blocks and components.”
From the above passage, the examiner understands that performing a transient analysis, when described broadly and without actionable specific steps, is a process which can practically be performed in the human mind by pen and paper, especially because the circuit diagram (aka netlist) is evaluated and simplified earlier in the claim. Therefore This is a mental process which can be performed with pen and paper by drawing circuits.
Step 2A Prong 2, Does the claim recite additional elements that integrate the judicial exception into a practical application?
NO. Claim 18 additionally recites A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:
This limitation describes the computer hardware or machinery used to apply the instructions which recite judicial exceptions. The MPEP 2106.05(f)(2) states “Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more.” Therefore this claim limitation does not integrate a judicial exception into a practical application or provide significantly more.
the leaf cells … memory module circuit
As stated above, the simplification of the circuit given a netlist is a mental process. The claim states additional elements, that the netlist contains leaf cells and represents a memory module circuit.
The MPEP 2106.05(g) outlines examples of insignificant and extra solution activity. With an example being “Selecting a particular data source or type of data to be manipulated:” One example given is “iii. Selecting information, based on types of information and availability of information in a power-grid environment, for collection, analysis and display, Electric Power Group, LLC v. Alstom S.A., 830 F.3d 1350, 1354-55, 119 USPQ2d 1739, 1742 (Fed. Cir. 2016); and”
The examiner views these limitations as being similar to the above examples, where this claim is directed to the analysis of netlist data, based on a memory module circuit and leaf cells present.
In order to determine if the limitations above are Insignificant Extra-solution activity, the MPEP 2106.05(g)(2) also considers “Whether the limitation is significant (i.e. it imposes meaningful limits on the claim such that it is not nominally or tangentially related to the invention).”
The inclusion of leaf cells and memory module circuits are insignificant limitation to the invention. Since these are examples of circuits, and components of circuits, which are the primary components for transient analysis.
Therefore, this limitation will be further addressed in Step 2B
Step 2B, does the claim recites additional elements that amount to significantly more than the judicial exception.
NO. As stated in Step 2A Prong 2, the leaf cells … memory module circuit
In step 2B, the examiner will evaluate whether or not the above limitations are well known in the art.
In “Computer Aids for VLSI Design” Rubin chapter 1 par 3 states :”Certain terms are used commonly in describing hierarchy. A cell that does not contain any instances of other cells is at the bottom of the hierarchy and is called a leaf cell.”
Also in section 1.2.2 Rubin states “For example, suppose that a 4K memory chip is to be designed, and further suppose that the design for a single bit of that memory is already done. Since the size of this bit of memory is the most important factor in the chip, all other circuitry must be designed to accommodate this cell. Therefore the design composition must proceed in a bottom-up manner, starting with the single bit of memory (see Fig. 1.14). In this example there are six levels of hierarchy starting at the single bit, aggregating a row of eight bits; stacking four of those vertically; stacking eight at the next higher level; and so on. The highest level of the hierarchy shows four arrays, each containing 32 × 32 bits. Memory-driving circuitry with the correct spacing is then placed around the bits.”
Where the examiner notes that memory module circuitry is well known in the art of circuits, and also that the above passage implies that leaf cells are known and considered in the art.
Therefore the above extra limitations are well known in the art and are considered insignificant extra solution activity.
Based on the above facts, the office concludes that claim 18 is not eligible under 35 USC 101.
Claim 19:The non-transitory computer readable medium of claim 18, wherein the processor is further configured to: (see claim 18)
determine port to port resistances between terminals of the internal circuits of the leaf cells;
The netlist is a logical diagram or a machine readable file which describes the connections in a circuit. Par 64 of this specification “For example, FIG. TA illustrates an example logical netlist 100 representing a memory module generated by a memory compiler. In electronic design, a netlist is a description of the connectivity of an electronic circuit and includes a list of the electronic components in a circuit and a list of the nodes they are connected to. A netlist may be a machine readable file that contains all the connections between all the components in an electronic circuit design. For example, memory compilers are software tools that build different types and configurations of memories from the leaf cells.”
The actionable steps performed in this method pertain to a determination of port to port resistances between the terminals of internal circuits of leaf cells that exist inside of this descriptive netlist.
MPEP 2106.04(a)(2)(III)(B) states “If a claim recites a limitation that can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper, the limitation falls within the mental processes grouping, and the claim recites an abstract idea.”
The Department of Electrical and Computer Engineering at UCSB, Course ece2c, lecture two_port 2021 discusses determining resistances between ports. See page W2-6
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As demonstrated from the above, determining port to port resistances between ports, when derived from a netlist, is a process performed by one ordinarily skilled in electrical engineering and physics. This is often performed by students and researchers through diagramming and solving for mathematic equations which relate current, voltage, and resistance, when certain variables are already provided. This is a mental process which can be performed with pen and paper by drawing circuits. Therefore, this claim limitation recites an abstract idea pertaining to a mental process.
and short one or more terminals of each of the leaf cells to a central node of a corresponding one of the equivalent networks,
As understood by the examiner, “shorting terminals” in this context refers to a mock deletion of terminals off of a netlist after already determining the equivalent resistances. This is done to prevent double counting. This is the same mental process already performed above, with an additional step of modifying the netlist to short the now redundant terminals to a central node. This is a mental process which can be performed with pen and paper by drawing circuits.
wherein the internal circuits of the leaf cells comprise one or more parasitic resistances of the leaf cells,
This limitation pertains to the internal circuits present in the netlist which are being analyzed by the judicial exception. From the examiners understanding, the term parasitic resistances refers to an inherent resistance present in the leaf cells. This is information present in the netlist. As already stated, the analysis of the netlist was determined to recite a mental process performed by a pen and paper, the presence of resistance information, whether or not the information is labeled as parasitic, does not influence that outcome. Therefore, this limitation is a further recitation of the above mental process.
wherein the equivalent networks comprise one or more equivalent resistances corresponding to the one or more parasitic resistances of the leaf cells, and
As stated above, the equivalent networks is a simplification process performed on a netlist to better interpret the resistances present across the different leaf cells. Whether the resistances present encompass parasitic resistances, which are inherent to the leaf cells, does not influence the process as outlined. Therefore, this limitation is a further recitation of the above mental process.
wherein promoting the equivalent networks of the leaf cells comprise connecting the one or more equivalent resistances corresponding to the one or more parasitic resistances of the leaf cells outside the leaf cells at inputs of the leaf cells.
As previously stated, From the examiners understanding, the term parasitic resistances refers to an inherent resistance present in the leaf cells. This is information present in the netlist. As stated above, connecting the equivalent resistances is the mental process described above used to calculate the current, resistance etc. through physics equations and then connecting the nodes together in the diagram description. This is a mental process which can be performed with pen and paper by drawing circuits, regardless if the resistances are considered to be parasitic. Therefore, this limitation is a further recitation of the above mental process.
Based on the above facts, the office concludes that claim 19 is not eligible under 35 USC 101.
Claim 20:Claim 20 is effectively similar to claim 4, except that it depends from claim 18. Therefore, claim 20 is rejected under the same rational as claims 4 and 18.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-8, 10-13, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over US 2004/0128637 A1 (Teene_2004), US 10,997,333 B1 (Singh_2021), US 6,807,520 B1 (Zhou_2004) and “Chapter 1: The Characteristics of Digital Electronic Design” (Rubin_1994) .
Claim 1:
Teene_2004 makes obvious A method (par 8: “The present invention provides an apparatus and method for automatically generating a visual symbolic representation of a resistance network and an equivalent point to point resistance for any set of terminals on the resistance network.”) for (Par 4: The extracted RC parasitics are used for a number of different applications including delay, power drop, and electromigration analysis. Accurate resistance extraction is essential for these applications.) the method comprising: determining port to port resistances between terminals (par 42: “More specifically, the resistance network may have multiple source and destination terminals. A source terminal is either an input port or source/drain of a transistor. A destination terminal is either an output port or a gate of a transistor. There are two approaches to evaluate the equivalent point to point resistance. With the first approach, the resistance from a source to all the destination terminals is calculated. This approach gives an equivalent resistance for the overall network. With the second approach, the resistance from a source to a single destination terminal is calculated. ) of internal circuits of a plurality of par 44: “FIG. 3 is an exemplary diagram illustrating the process for generating a resistance network graph visual representation and point to point resistance. As shown in FIG. 3, a cell layout 310 is obtained for a portion of an integrated circuit. The parasitics of the cell layout are extracted to generate an extracted parasitics data structure) of a netlist representing the ( par 36: “The graph data structure representation of the resistance network is generated by first reading the RC parasitics netlist.”) generating a plurality of equivalent ((par 41: “After the symbolic view of the graph data structure is generated, equivalent point to point resistance for any set of terminals on the resistance network may be generated”) the equivalent (par 35: “From the RC parasitics, a graph data structure representation of the resistance network is generated. The resistance graph consists of nodes and arcs. The arcs represent the resistors and have attributes that include-the resistance value, interconnect layer and name (the name corresponds to the resistor identifier in the netlist). The nodes represent the resistor connection. The graph terminals are the resistor network inputs and outputs, these are either device terminals or input/output pins.) Examiner note: See FIG._3 which depicts equivalent networks of point to point resistance being connected to each other. ) ((Par 4: The extracted RC parasitics are used for a number of different applications including delay, power drop, and electromigration analysis. Accurate resistance extraction is essential for these applications.)
Teene_2004 does not expressly recite transient
memory module
networks
promoting the equivalent networks of the leaf cells to a hierarchical level above the leaf cells in the netlist representing the memory module circuit
shorting one or more terminals of each of the leaf cells to a central node of a corresponding one of the equivalent networks;
Singh_2021 however makes obvious transient (col 26 par 1: “A layout for each of the multiple design fabrics of the electronic design may be identified at 204F; and an extracted model that represents a set of circuit components may be determined or extracted at 206F from these multiple layouts. An extracted model described herein may also include, for example, one or more elements describing the properties of components (e.g., inductors, capacitors, resistors, etc.) as 10 well as the transient or steady-state electrical behavior of a circuit component in response to one or more stimuli by one or more electrical signals.”)
networks (col 9 par 6: “For example, the single extracted view may be generated by selectively flattening one or more hierarchical levels pertaining to an extracted model of interest while preserving the original schematic design(s) for the remaining hierarchical levels. As a result, the netlist corresponding to the single extracted view is much smaller that those created by conventional approaches that create a respective extracted view for each of a plurality of hierarchical levels.” Examiner note: Where the extracted view generated involves generated equivalent networks in the netlist.
promoting the equivalent networks of the leaf cells (col 30 par 2: “Although the leaf hierarchical level ( 408A) does not pertain to any extracted models, these conventional approaches nevertheless create an extracted view 408B by flattening the leaf hierarchical level” Examiner note: Where this makes obvious the use of leaf cells in this process) to a hierarchical level above the leaf cells (col 35 par 2: “An extracted view generation module may thus generate the single extracted view 602D by flattening hierarchical levels 0, 1, and 2 while preserving the remaining hierarchical levels. More particularly, the schematic circuit components at hierarchical levels 0, 1, and 2 are promoted by the flattening process and propagated into the single extracted view 602D while the original schematic designs corresponding to the remaining hierarchical levels are preserved and referenced in the extracted view 602D.”) in the netlist representing the col 35 par 3: “FIG. 6E illustrates an example netlist of the electronic 15 design illustrated in FIG. 6A and created with some of the techniques described herein in one or more embodiments. More specifically, FIG. 6E illustrates the resulting netlist created by some embodiments described above with reference to FIGS. 6A and 6D. The resulting netlist 602E is much 20 smaller in size because it includes much fewer sub-circuits and information than the netlist 602C illustrated in FIG. 6C. The smaller size and lower complexity are a result of the selective flattening of only hierarchical levels 0, 1, and 2 while preserving the original schematic designs for the remaining hierarchical levels ( e.g., the leaf hierarchical level) that do not pertain to the aforementioned extracted models, without flattening these remaining hierarchical levels)
Teene_2004 and Singh_2021 are analogous art to the claimed invention because they are from the same field of endeavor called circuit design and planning. Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to combine Teene_2004 and Singh_2021.
The rationale for doing so would have been to follow a teaching and motivation proposed in the prior art. Teene_2004 outlines a method which generated equivalent point to point resistances for a circuit for design and verification including parasitic extraction, where the resistance is stored in a table as daya par 4: “Resistance/capacitance (RC) parasitic extraction of cell and interconnect structures is an essential part of the integrated circuit design and verification process.” … par 10: “The point to point resistance may be used for detailed analysis and verification of the extracted parasitics.” … par 50: “The point to point resistance generation module 460 generates a table of point to point resistance values for any set of terminals in the reduced graph data structure.” Singh_2021 is also involved in circuit design and verification, specifically in parasitics. Singh_2021 states col 1 par 3: “Circuit designers and verification engineers use different methods to verify circuit designs. One common method of verification is the use of simulation.” Singh_2021 uses pasasitic data col 13 par 1: “For example, some embodiments may
store parasitic data of some parameterized, pre-existing, or pre-characterized electronic circuit component designs in a tabular structure (e.g., a database) so that these one or more computing systems, when modeling an electronic circuit component design as model in an extracted view, may look up the parasitic data” this is used to col 18 par 2: “one or more signoff parasitic extraction modules to provide silicon-accurate interconnect parasitic extraction and ensure first-pass silicon success, and one or more power signoff modules to perform various power integrity analyses transistor-level electro migration and IR-drop analyses, or other power and signal integrity analyses with SPICE-level accuracy or better accuracy with SPICE or SPICE-like simulations (e.g., FastSPICE, HSPICE, PSPICE, or any other SPICE-based or SPICE-compatible simulations) to ensure an electronic 20 design meets or exceeds power, performance, and/or area goals in some embodiments.” Therefore, it would have been obvious to combine the parasitic resistances extraction of Teene_2014 with the hierarchical networks simulation process of Singh_2021 which uses that information for the benefit of simulation and verification to ensure an electronic design meets requirements to obtain the invention as specified in the claims.
Teene_2004 and Singh_2021 do not expressly recite memory module
shorting one or more terminals of each of the leaf cells to a central node of a corresponding one of the equivalent networks;
Zhou_2004 however makes obvious
Leaf (col 5 par 6: “The term "leaf cell" is used to mean a set of circuit elements as specified by the circuit designer as a reusable unit.”
Teene_2004, Singh_2021, and Zhou_2004 are analogous art to the claimed invention because they are from the same field of endeavor called circuit planning. Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to combine Teene_2004, Singh_2021, and Zhou_2004. The rational would have been to apply a known technique to a known device ready for improvement to yeidl a predictable result. The prior art of Teene_2004 works on cells but does not specify the term “leaf cell.” The definition of Zhou_2004 makes obvious the term “leaf cell” over the prior art of Teene_2004. Therefore it would have been obvious to combine the cell workflow of Teene_2004 with the usage of “leaf cells” of Zhou_2004 for the predictable result of determining parasitic resistance for leaf cells.
Zhou_2004 further makes obvious shorting one or more terminals of each of the leaf cells (see fig 9. “CUT LEAF GROUP ) to a central node of a corresponding one of the equivalent networks; (col 2 par 4: “The system and method 45 utilize, in one embodiment, an event driven simulator that divides or "cuts" along the hierarchical boundaries of the input netlist in order to produce subcircuits that are then converted into Thevenin equivalent circuit models. Once a Thevenin equivalent circuit model is computed, matrix 50 equations/computations are used to compute the cut node voltages and then sensitivity vectors may be used to determine the internal node voltages. The cut node voltages are stored in a flattened cut node voltage data structure that is dynamic. Internal node voltages may be stored in instance 55 specific dynamic data structures. This is done for each event.” (Examiners note: Where the process above involves conceptually “shorting one or more terminals of each of the leaf cells to a central node of a corresponding one of the equivalent networks;“ as is done in the netlist in light of the specifications)
Teene_2004, Singh_2021, and Zhou_2004 are analogous art to the claimed invention because they are from the same field of endeavor called circuit planning. Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to combine Teene_2004, Singh_2021, and Zhou_2004. The rationale for doing so would have been to follow a teaching and motivation proposed in the prior art. Firstly, Zhou_2004 col 1 par 3 states “Circuit simulators are computer implemented processes that can simulate the expected operation and behavior of a circuit design by applying a set of input signals to the netlist and propagating the resultant signals through the netlist to its output nodes. Circuit simulators can be used, in one way, to 35 verify that a netlist properly performs its specified operation and/or to measure the performance of the design.” And furthermore that col 14 line 5 “An advantage of the present invention is that the structural, e.g., static data, of the input netlist does not need to be flattened in order for the simulation to operate. By avoiding this flattening requirement ( that is required of the prior art), the present invention can operate using significantly less memory resources over a prior art simulator. …. Line 35: “Regarding hierarchical extraction, post-layout extraction with parasitics can be done hierarchically, but has not been done up to now because simulation tools could not take advantage of a hierarchical database (other than to reduce the amount of input data). This is because conventional simulators flatten a hierarchical database; so there is no advantage afforded by the effort of doing hierarchical extraction because the simulation tools that use the data will flatten it anyway. However, the cut procedure of the present invention makes hierarchical extraction a useful operation. In essence, a set of identical leaf cells that have identical layouts have identical internal parasitic elements, and these parasitic elements can be extracted once and shared among the set of identical leaf cells.“ Therefore, it would have been obvious to combine the parasitic resistance extraction process and hierarchical simulations of Teene_2004 and Sing_2021 with the netlist simplification method using equivalents of Zhou_2004 for the benefit of taking advantage of hierarchical extractions to simulate the performance of a design with parasitics using less memory to obtain the invention as specified in the claims.
Teene_2004, Singh_2021, and Zhou_2004 do not expressly recite memory module
Rubin_1994 makes obvious memory module (page 3 par 5: “For example, suppose that a 4K memory chip is to be designed”)
Teene_2004, Singh_2021, Zhou_2004, and Rubin_1994 are analogous art to the claimed invention because they are from the same field of endeavor called chip design and netlists. Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to combine Teene_2004, Singh_2021, Zhou_2004, and Rubin_1994. The rationale for doing so would have been applying a known technique to a known device ready for improvements to yield a predictable result. The prior arts of Teene_2004, Singh_2021, and Zhou_2004 apply techniques for circuits. The prior arts of Teene_2004, Singh_2021, Zhou_2004 are silent that the technique is applied to memory module. Rubin_1994 outlines chip design and netlists as they apply to memory chips. One ordinarily skilled in the art would recognize applying the known techniques of Teene_2004, Singh_2021, and Zhou_2004 which apply to netlists would provide predictable results when also applied to memory modules. Therefore, it would have been obvious to combine the workflows of Teene_2004, Singh_2021, and Zhou_2004 with the usage of a memory chip of Rubin_1994 for the predictable result of simulation/simplifying a netlist of a memory module to obtain the invention as specified in the claims.
Claim 2:
The method of claim 1,
Teene_2014 makes further obvious wherein the internal circuits of the leaf cells comprise one or more parasitic resistances of the leaf cells,( (par 44: “FIG. 3 is an exemplary diagram illustrating the process for generating a resistance network graph visual representation and point to point resistance. As shown in FIG. 3, a cell layout 310 is obtained for a portion of an integrated circuit. The parasitics of the cell layout are extracted to generate an extracted parasitics data structure ) and wherein the equivalent networks comprise one or more equivalent resistances corresponding to the one or more parasitic resistances of the leaf cells. ((abstract: “Thereafter, equivalent point to point resistance for any set of terminals on the resistance network may be generated. The point to point resistance may be used for detailed analysis and verification of the extracted parasitics.”)
Claim 3:
The method of claim 2,
Teene_2014 makes further obvious wherein promoting the equivalent networks of the leaf cells comprises connecting the one or more equivalent resistances corresponding to the one or more parasitic resistances of the leaf cells outside the leaf cells at inputs of the leaf cells.
(See Fig 3. Where the examiner understands the Resistance Network Graph (330) to make obvious the workflow described in the claim, which the examiner understands as essentially connecting the equivalent resistances of the leaf cells to each other in the netlist representation)
Claim 7:
A system (par 8: “The present invention provides an apparatus and method for automatically generating a visual symbolic representation of a resistance network and an equivalent point to point resistance for any set of terminals on the resistance network.”) for (Par 4: The extracted RC parasitics are used for a number of different applications including delay, power drop, and electromigration analysis. Accurate resistance extraction is essential for these applications.) the system comprising: a memory storing instructions; (par 33: “The processes of the present invention are performed by processor 202 using computer implemented instructions, which may be located in a memory such as, for example, main memory 204, memory 224, or in one or more peripheral devices 226-230.”) and a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to: (par 28: “Processor 202 and main memory 204 are connected to PCI local bus 206 through PCI bridge 208. PCI bridge 208 also may include an integrated memory controller and cache memory for processor 202.”)
par 39: “For dangling node reduction, all the nodes of the graph data structure are scanned and a determination is made as to whether any non-terminal node has one and only one connection. If so, then the node and arc are deleted from the graph data structure. These reduction techniques are repeated until no more reduction is possible. (Examiner note: iteratively) The result is a fully reduced graph data structure.”) Examiner note: explanation of mapping, see par 35 which explains relationship of nodes/arcs to resistors: “From the RC parasitics, a graph data structure representation of the resistance network is generated. The resistance graph consists of nodes and arcs. The arcs represent the resistors and have attributes that include-the resistance value, interconnect layer and name (the name corresponds to the resistor identifier in the netlist). The nodes represent the resistor connection. The graph terminals are the resistor network inputs and outputs, these are either device terminals or input/output pins.”
generate equivalent ((par 41: “After the symbolic view of the graph data structure is generated, equivalent point to point resistance for any set of terminals on the resistance network may be generated”) ((Par 4: The extracted RC parasitics are used for a number of different applications including delay, power drop, and electromigration analysis. Accurate resistance extraction is essential for these applications.)
Teene_2004 does not expressly recite Transient
Memory module
remove one or more transistors and capacitors in each of a plurality of leaf cells of a netlist representing the memory module circuit;
networks
promote the equivalent networks of the leaf cells to a hierarchical level above the leaf cells in the memory module circuit
leaf
Singh_2021 however, makes obvious Transient (col 26 par 1: “A layout for each of the multiple design fabrics of the electronic design may be identified at 204F; and an extracted model that represents a set of circuit components may be determined or extracted at 206F from these multiple layouts. An extracted model described herein may also include, for example, one or more elements describing the properties of components (e.g., inductors, capacitors, resistors, etc.) as 10 well as the transient or steady-state electrical behavior of a circuit component in response to one or more stimuli by one or more electrical signals.”)
networks (col 9 par 6: “For example, the single extracted view may be generated by selectively flattening one or more hierarchical levels pertaining to an extracted model of interest while preserving the original schematic design(s) for the remaining hierarchical levels. As a result, the netlist corresponding to the single extracted view is much smaller that those created by conventional approaches that create a respective extracted view for each of a plurality of hierarchical levels.” Examiner note: Where the extracted view generated involves generated equivalent networks in the netlist.
promote the equivalent networks of the leaf cells col 30 par 2: “Although the leaf hierarchical level ( 408A) does not pertain to any extracted models, these conventional approaches nevertheless create an extracted view 408B by flattening the leaf hierarchical level” Examiner note: Where this makes obvious the use of leaf cells in this process) to a hierarchical level above the leaf cells (col 35 par 2: “An extracted view generation module may thus generate the single extracted view 602D by flattening hierarchical levels 0, 1, and 2 while preserving the remaining hierarchical levels. More particularly, the schematic circuit components at hierarchical levels 0, 1, and 2 are promoted by the flattening process and propagated into the single extracted view 602D while the original schematic designs corresponding to the remaining hierarchical levels are preserved and referenced in the extracted view 602D.”) in the col 35 par 3: “FIG. 6E illustrates an example netlist of the electronic 15 design illustrated in FIG. 6A and created with some of the techniques described herein in one or more embodiments. More specifically, FIG. 6E illustrates the resulting netlist created by some embodiments described above with reference to FIGS. 6A and 6D. The resulting netlist 602E is much 20 smaller in size because it includes much fewer sub-circuits and information than the netlist 602C illustrated in FIG. 6C. The smaller size and lower complexity are a result of the selective flattening of only hierarchical levels 0, 1, and 2 while preserving the original schematic designs for the remaining hierarchical levels ( e.g., the leaf hierarchical level) that do not pertain to the aforementioned extracted models, without flattening these remaining hierarchical levels)
Teene_2004 and Singh_2021 are analogous art to the claimed invention because they are from the same field of endeavor called circuit design and planning. Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to combine Teene_2004 and Singh_2021.
The rationale for doing so would have been to follow a teaching and motivation proposed in the prior art. Teene_2004 outlines a method which generated equivalent point to point resistances for a circuit for design and verification including parasitic extraction, where the resistance is stored in a table as daya par 4: “Resistance/capacitance (RC) parasitic extraction of cell and interconnect structures is an essential part of the integrated circuit design and verification process.” … par 10: “The point to point resistance may be used for detailed analysis and verification of the extracted parasitics.” … par 50: “The point to point resistance generation module 460 generates a table of point to point resistance values for any set of terminals in the reduced graph data structure.” Singh_2021 is also involved in circuit design and verification, specifically in parasitics. Singh_2021 states col 1 par 3: “Circuit designers and verification engineers use different methods to verify circuit designs. One common method of verification is the use of simulation.” Singh_2021 uses pasasitic data col 13 par 1: “For example, some embodiments may
store parasitic data of some parameterized, pre-existing, or pre-characterized electronic circuit component designs in a tabular structure (e.g., a database) so that these one or more computing systems, when modeling an electronic circuit component design as model in an extracted view, may look up the parasitic data” this is used to col 18 par 2: “one or more signoff parasitic extraction modules to provide silicon-accurate interconnect parasitic extraction and ensure first-pass silicon success, and one or more power signoff modules to perform various power integrity analyses transistor-level electro migration and IR-drop analyses, or other power and signal integrity analyses with SPICE-level accuracy or better accuracy with SPICE or SPICE-like simulations (e.g., FastSPICE, HSPICE, PSPICE, or any other SPICE-based or SPICE-compatible simulations) to ensure an electronic 20 design meets or exceeds power, performance, and/or area goals in some embodiments.” Therefore, it would have been obvious to combine the parasitic resistances extraction of Teene_2014 with the hierarchical networks simulation process of Singh_2021 which uses that information for the benefit of simulation and verification to ensure an electronic design meets requirements to obtain the invention as specified in the claims.
Teene_2004 and Singh_2021 do not expressly recite memory module
remove one or more transistors and capacitors in each of a plurality of leaf cells of a netlist representing the memory module circuit;
Zhou_2004 however makes obvious
Leaf (col 5 par 6: “The term "leaf cell" is used to mean a set of circuit elements as specified by the circuit designer as a reusable unit.”
Teene_2004, Singh_2021, and Zhou_2004 are analogous art to the claimed invention because they are from the same field of endeavor called circuit planning. Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to combine Teene_2004, Singh_2021, and Zhou_2004. The rational would have been to apply a known technique to a known device ready for improvement to yeidl a predictable result. The prior art of Teene_2004 works on cells but does not specify the term “leaf cell.” The definition of Zhou_2004 makes obvious the term “leaf cell” over the prior art of Teene_2004. Therefore it would have been obvious to combine the cell workflow of Teene_2004 with the usage of “leaf cells” of Zhou_2004 for the predictable result of determining parasitic resistance for leaf cells.
remove one or more transistors and capacitors (Zhou_2004 col 5 par 8: “Subsequent processing of floating capacitors ( e.g., capacitors with neither terminal tied to a supply voltage) does the following: 1) discards "small" floating capacitors, but compensates by adding the capacitance value to the node capacitance values for the two nodes, thereby allowing partitioning at those nodes;” ) in each of a plurality of leaf cells (col 5 par 6: “The term "leaf cell" is used to mean a set of circuit elements as specified by the circuit designer as a reusable unit.”) of a netlist representing the (Col 6 par 3: “Embodiments of the present invention are drawn to an integrated circuit simulator that advantageously utilizes cut techniques that are based on circuit boundaries that are defined on the hierarchy of an input hierarchical netlist.”)
Teene_2004, Singh_2021, and Zhou_2004 are analogous art to the claimed invention because they are from the same field of endeavor called circuit planning. Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to combine Teene_2004, Singh_2021, and Zhou_2004. The rationale for doing so would have been to follow a teaching and motivation proposed in the prior art. Zhou_2004 col 1 par 3 states “Circuit simulators are computer implemented processes that can simulate the expected operation and behavior of a circuit design by applying a set of input signals to the netlist and propagating the resultant signals through the netlist to its output nodes. Circuit simulators can be used, in one way, to 35 verify that a netlist properly performs its specified operation and/or to measure the performance of the design.” And furthermore that col 14 line 5 “An advantage of the present invention is that the structural, e.g., static data, of the input netlist does not need to be flattened in order for the simulation to operate. By avoiding this flattening requirement ( that is required of the prior art), the present invention can operate using significantly less memory resources over a prior art simulator. …. Line 35: “Regarding hierarchical extraction, post-layout extraction with parasitics can be done hierarchically, but has not been done up to now because simulation tools could not take advantage of a hierarchical database (other than to reduce the amount of input data). This is because conventional simulators flatten a hierarchical database; so there is no advantage afforded by the effort of doing hierarchical extraction because the simulation tools that use the data will flatten it anyway. However, the cut procedure of the present invention makes hierarchical extraction a useful operation. In essence, a set of identical leaf cells that have identical layouts have identical internal parasitic elements, and these parasitic elements can be extracted once and shared among the set of identical leaf cells.“ Therefore, it would have been obvious to combine the parasitic resistance extraction process and hierarchical simulations of Teene_2004 and Sing_2021 with the netlist simplification method using equivalents of Zhou_2004 for the benefit of taking advantage of hierarchical extractions to simulate the performance of a design with parasitics using less memory to obtain the invention as specified in the claims.
Teene_2004, Singh_2021, and Zhou_2004 do not expressly recite memory module
Rubin_1994 makes obvious memory module (page 3 par 5: “For example, suppose that a 4K memory chip is to be designed”)
Teene_2004, Singh_2021, Zhou_2004, and Rubin_1994 are analogous art to the claimed invention because they are from the same field of endeavor called chip design and netlists. Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to combine Teene_2004, Singh_2021, Zhou_2004, and Rubin_1994. The rationale for doing so would have been applying a known technique to a known device ready for improvements to yield a predictable result. The prior arts of Teene_2004, Singh_2021, and Zhou_2004 apply techniques for circuits. The prior arts of Teene_2004, Singh_2021, Zhou_2004 are silent that the technique is applied to memory module. Rubin_1994 outlines chip design and netlists as they apply to memory chips. One ordinarily skilled in the art would recognize applying the known techniques of Teene_2004, Singh_2021, and Zhou_2004 which apply to netlists would provide predictable results when also applied to memory modules. Therefore, it would have been obvious to combine the workflows of Teene_2004, Singh_2021, and Zhou_2004 with the usage of a memory chip of Rubin_1994 for the predictable result of simulation/simplifying a netlist of a memory module to obtain the invention as specified in the claims.
Claim 8:The system of claim 7,
Teene_2014 makes further obvious wherein the processor is further configured to: determine the internal circuits of the leaf cells, each of the internal circuits comprising one or more remaining resistors after the iterative reduction of the resistors in each of the leaf cells. ((par 40-41: “Following reduction, if any, a visual representation of the resistance network is generated using the graph data structure. The visual representation of the resistance network is generated as a symbolic view of a graph generated from the graph data structure. This symbolic view may include nodes representing resistor connections, arcs between nodes representing resistors, labels identifying resistance values and names of elements ( corresponding to netlist identifiers), and the like. Layers of the resistance network may be represented, for example, in various colors, shading, or any other distinguishing manner. After the symbolic view of the graph data structure is generated, equivalent point to point resistance for any set of terminals on the resistance network may be generated.”)
Claim 10:
The system of claim 7, wherein the processor is further configured to:
Teene_2014 makes obvious determine port to port resistances between terminals (par 42: “More specifically, the resistance network may have multiple source and destination terminals. A source terminal is either an input port or source/drain of a transistor. A destination terminal is either an output port or a gate of a transistor. There are two approaches to evaluate the equivalent point to point resistance. With the first approach, the resistance from a source to all the destination terminals is calculated. This approach gives an equivalent resistance for the overall network. With the second approach, the resistance from a source to a single destination terminal is calculated. ) of the internal circuits of the par 44: “FIG. 3 is an exemplary diagram illustrating the process for generating a resistance network graph visual representation and point to point resistance. As shown in FIG. 3, a cell layout 310 is obtained for a portion of an integrated circuit. The parasitics of the cell layout are extracted to generate an extracted parasitics data structure)
Teene_2014 does not expressly recite leaf
and short one or more terminals of each of the leaf cells to a central node of a corresponding one of the equivalent networks.
Zhou_2004 however makes obvious Leaf (col 5 par 6: “The term "leaf cell" is used to mean a set of circuit elements as specified by the circuit designer as a reusable unit.”
As stated above, it would have been obvious to combine the cell workflow of Teene_2004 with the usage of “leaf cells” of Zhou_2004 for the predictable result of determining parasitic resistance for leaf cells.
Zhou_2004 further makes obvious shorting one or more terminals of each of the leaf cells (see fig 9. “CUT LEAF GROUP ) to a central node of a corresponding one of the equivalent networks; (col 2 par 4: “The system and method 45 utilize, in one embodiment, an event driven simulator that divides or "cuts" along the hierarchical boundaries of the input netlist in order to produce subcircuits that are then converted into Thevenin equivalent circuit models. Once a Thevenin equivalent circuit model is computed, matrix 50 equations/computations are used to compute the cut node voltages and then sensitivity vectors may be used to determine the internal node voltages. The cut node voltages are stored in a flattened cut node voltage data structure that is dynamic. Internal node voltages may be stored in instance 55 specific dynamic data structures. This is done for each event.” (Examiners note: Where the process above involves conceptually “shorting one or more terminals of each of the leaf cells to a central node of a corresponding one of the equivalent networks;“ as is done in the netlist in light of the specifications)
As states above, it would have been obvious to combine the parasitic resistance extraction process and hierarchical simulations of Teene_2004 and Sing_2021 with the netlist simplification method using equivalents of Zhou_2004 for the benefit of taking advantage of hierarchical extractions to simulate the performance of a design with parasitics using less memory to obtain the invention as specified in the claims.
Claim 11:
The system of claim 10, wherein the equivalent networks corresponding to the internal circuits of the leaf cells are generated based (see claim 7)
Teene_2014 makes obvious on the port to port resistances between the terminals of the internal circuits of the leaf cells. , ((par 41: “After the symbolic view of the graph data structure is generated, equivalent point to point resistance for any set of terminals on the resistance network may be generated”) Examiner note: see claim 7 for mappings to networks and leaf cells.
Claim 12:Teene_2014 makes further obvious The system of claim 10, wherein the internal circuits of the leaf cells comprise one or more parasitic resistances of the leaf cells, ,( (par 44: “FIG. 3 is an exemplary diagram illustrating the process for generating a resistance network graph visual representation and point to point resistance. As shown in FIG. 3, a cell layout 310 is obtained for a portion of an integrated circuit. The parasitics of the cell layout are extracted to generate an extracted parasitics data structure )
and wherein the equivalent networks comprise one or more equivalent resistances corresponding to the one or more parasitic resistances of the leaf cells. ((abstract: “Thereafter, equivalent point to point resistance for any set of terminals on the resistance network may be generated. The point to point resistance may be used for detailed analysis and verification of the extracted parasitics.”)
Claim 13:
Teene_2014 makes further obvious The system of claim 12, wherein promoting the equivalent networks of the leaf cells comprises connecting the one or more equivalent resistances corresponding to the one or more parasitic resistances of the leaf cells outside the leaf cells at an input of each of the leaf cells. (See Fig 3. Where the examiner understands the Resistance Network Graph (330) to make obvious the workflow described in the claim, which the examiner understands as essentially connecting the equivalent resistances of the leaf cells to each other in the netlist representation)
Claim 18:
Teene_2014 A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to: (par 28: “Processor 202 and main memory 204 are connected to PCI local bus 206 through PCI bridge 208. PCI bridge 208 also may include an integrated memory controller and cache memory for processor 202.” … par 33: “The processes of the present invention are performed by processor 202 using computer implemented instructions, which may be located in a memory such as, for example, main memory 204, memory 224, or in one or more peripheral devices)
generate equivalent networks [resistances] corresponding to internal circuits of a plurality of leaf cells of a netlist representing a memory module circuit; (((par 41: “After the symbolic view of the graph data structure is generated, equivalent point to point resistance for any set of terminals on the resistance network may be generated”) Examiner note: explanation of mapping, see par 35 which explains relationship of nodes/arcs to resistors: “From the RC parasitics, a graph data structure representation of the resistance network is generated. The resistance graph consists of nodes and arcs. The arcs represent the resistors and have attributes that include-the resistance value, interconnect layer and name (the name corresponds to the resistor identifier in the netlist). The nodes represent the resistor connection. The graph terminals are the resistor network inputs and outputs, these are either device terminals or input/output pins.”
promote the equivalent networks of the leaf cells to a hierarchical level above the leaf cells in the memory module circuit; and perform a transient analysis of the leaf cells of the netlist representing the memory module circuit. ((Par 4: The extracted RC parasitics are used for a number of different applications including delay, power drop, and electromigration analysis. Accurate resistance extraction is essential for these applications.)
Teene_2014 does not expressly recite networks
Leaf
Memory module
promote the equivalent networks of the leaf cells to a hierarchical level above the leaf cells in the memory module circuit
transient
Singh_2021 however, makes obvious
Transient (col 26 par 1: “A layout for each of the multiple design fabrics of the electronic design may be identified at 204F; and an extracted model that represents a set of circuit components may be determined or extracted at 206F from these multiple layouts. An extracted model described herein may also include, for example, one or more elements describing the properties of components (e.g., inductors, capacitors, resistors, etc.) as 10 well as the transient or steady-state electrical behavior of a circuit component in response to one or more stimuli by one or more electrical signals.”)
networks (col 9 par 6: “For example, the single extracted view may be generated by selectively flattening one or more hierarchical levels pertaining to an extracted model of interest while preserving the original schematic design(s) for the remaining hierarchical levels. As a result, the netlist corresponding to the single extracted view is much smaller that those created by conventional approaches that create a respective extracted view for each of a plurality of hierarchical levels.” Examiner note: Where the extracted view generated involves generated equivalent networks in the netlist.
promote the equivalent networks of the leaf cells col 30 par 2: “Although the leaf hierarchical level ( 408A) does not pertain to any extracted models, these conventional approaches nevertheless create an extracted view 408B by flattening the leaf hierarchical level” Examiner note: Where this makes obvious the use of leaf cells in this process) to a hierarchical level above the leaf cells (col 35 par 2: “An extracted view generation module may thus generate the single extracted view 602D by flattening hierarchical levels 0, 1, and 2 while preserving the remaining hierarchical levels. More particularly, the schematic circuit components at hierarchical levels 0, 1, and 2 are promoted by the flattening process and propagated into the single extracted view 602D while the original schematic designs corresponding to the remaining hierarchical levels are preserved and referenced in the extracted view 602D.”) in the memory module circuit (col 35 par 3: “FIG. 6E illustrates an example netlist of the electronic 15 design illustrated in FIG. 6A and created with some of the techniques described herein in one or more embodiments. More specifically, FIG. 6E illustrates the resulting netlist created by some embodiments described above with reference to FIGS. 6A and 6D. The resulting netlist 602E is much 20 smaller in size because it includes much fewer sub-circuits and information than the netlist 602C illustrated in FIG. 6C. The smaller size and lower complexity are a result of the selective flattening of only hierarchical levels 0, 1, and 2 while preserving the original schematic designs for the remaining hierarchical levels ( e.g., the leaf hierarchical level) that do not pertain to the aforementioned extracted models, without flattening these remaining hierarchical levels)
Teene_2004 and Singh_2021 are analogous art to the claimed invention because they are from the same field of endeavor called circuit design and planning. Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to combine Teene_2004 and Singh_2021.
The rationale for doing so would have been to follow a teaching and motivation proposed in the prior art. Teene_2004 outlines a method which generated equivalent point to point resistances for a circuit for design and verification including parasitic extraction, where the resistance is stored in a table as daya par 4: “Resistance/capacitance (RC) parasitic extraction of cell and interconnect structures is an essential part of the integrated circuit design and verification process.” … par 10: “The point to point resistance may be used for detailed analysis and verification of the extracted parasitics.” … par 50: “The point to point resistance generation module 460 generates a table of point to point resistance values for any set of terminals in the reduced graph data structure.” Singh_2021 is also involved in circuit design and verification, specifically in parasitics. Singh_2021 states col 1 par 3: “Circuit designers and verification engineers use different methods to verify circuit designs. One common method of verification is the use of simulation.” Singh_2021 uses pasasitic data col 13 par 1: “For example, some embodiments may
store parasitic data of some parameterized, pre-existing, or pre-characterized electronic circuit component designs in a tabular structure (e.g., a database) so that these one or more computing systems, when modeling an electronic circuit component design as model in an extracted view, may look up the parasitic data” this is used to col 18 par 2: “one or more signoff parasitic extraction modules to provide silicon-accurate interconnect parasitic extraction and ensure first-pass silicon success, and one or more power signoff modules to perform various power integrity analyses transistor-level electro migration and IR-drop analyses, or other power and signal integrity analyses with SPICE-level accuracy or better accuracy with SPICE or SPICE-like simulations (e.g., FastSPICE, HSPICE, PSPICE, or any other SPICE-based or SPICE-compatible simulations) to ensure an electronic 20 design meets or exceeds power, performance, and/or area goals in some embodiments.” Therefore, it would have been obvious to combine the parasitic resistances extraction of Teene_2014 with the hierarchical networks simulation process of Singh_2021 which uses that information for the benefit of simulation and verification to ensure an electronic design meets requirements to obtain the invention as specified in the claims.
Teene_2004 and Singh_2021 do not expressly recite memory module
Leaf
Zhou_2004 however makes obvious memory module
Leaf (col 5 par 6: “The term "leaf cell" is used to mean a set of circuit elements as specified by the circuit designer as a reusable unit.”
Teene_2004, Singh_2021, and Zhou_2004 are analogous art to the claimed invention because they are from the same field of endeavor called circuit planning. Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to combine Teene_2004, Singh_2021, and Zhou_2004. The rational would have been to apply a known technique to a known device ready for improvement to yeidl a predictable result. The prior art of Teene_2004 works on cells but does not specify the term “leaf cell.” The definition of Zhou_2004 makes obvious the term “leaf cell” over the prior art of Teene_2004. Therefore it would have been obvious to combine the cell workflow of Teene_2004 with the usage of “leaf cells” of Zhou_2004 for the predictable result of determining parasitic resistance for leaf cells.
Teene_2004, Singh_2021, and Zhou_2004 do not expressly recite memory module
Rubin_1994 makes obvious memory module (page 3 par 5: “For example, suppose that a 4K memory chip is to be designed”)
Teene_2004, Singh_2021, Zhou_2004, and Rubin_1994 are analogous art to the claimed invention because they are from the same field of endeavor called chip design and netlists. Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to combine Teene_2004, Singh_2021, Zhou_2004, and Rubin_1994. The rationale for doing so would have been applying a known technique to a known device ready for improvements to yield a predictable result. The prior arts of Teene_2004, Singh_2021, and Zhou_2004 apply techniques for circuits. The prior arts of Teene_2004, Singh_2021, Zhou_2004 are silent that the technique is applied to memory module. Rubin_1994 outlines chip design and netlists as they apply to memory chips. One ordinarily skilled in the art would recognize applying the known techniques of Teene_2004, Singh_2021, and Zhou_2004 which apply to netlists would provide predictable results when also applied to memory modules. Therefore, it would have been obvious to combine the workflows of Teene_2004, Singh_2021, and Zhou_2004 with the usage of a memory chip of Rubin_1994 for the predictable result of simulation/simplifying a netlist of a memory module to obtain the invention as specified in the claims.
Claim 19:The non-transitory computer readable medium of claim 18, wherein the processor is further configured to:
Teene_2014 makes further obvious determine port to port resistances between terminals (par 42: “More specifically, the resistance network may have multiple source and destination terminals. A source terminal is either an input port or source/drain of a transistor. A destination terminal is either an output port or a gate of a transistor. There are two approaches to evaluate the equivalent point to point resistance. With the first approach, the resistance from a source to all the destination terminals is calculated. This approach gives an equivalent resistance for the overall network. With the second approach, the resistance from a source to a single destination terminal is calculated. ) of the internal circuits of the leaf cells; (par 44: “FIG. 3 is an exemplary diagram illustrating the process for generating a resistance network graph visual representation and point to point resistance. As shown in FIG. 3, a cell layout 310 is obtained for a portion of an integrated circuit. The parasitics of the cell layout are extracted to generate an extracted parasitics data structure) and short one or more terminals of each of the leaf cells to a central node of a corresponding one of the equivalent networks, wherein the internal circuits of the leaf cells comprise one or more parasitic resistances of the leaf cells, (par 44: “FIG. 3 is an exemplary diagram illustrating the process for generating a resistance network graph visual representation and point to point resistance. As shown in FIG. 3, a cell layout 310 is obtained for a portion of an integrated circuit. The parasitics of the cell layout are extracted to generate an extracted parasitics data structure ) wherein the equivalent networks comprise one or more equivalent resistances corresponding to the one or more parasitic resistances of the leaf cells, ((abstract: “Thereafter, equivalent point to point resistance for any set of terminals on the resistance network may be generated. The point to point resistance may be used for detailed analysis and verification of the extracted parasitics.”) and wherein promoting the equivalent networks of the leaf cells comprise connecting the one or more equivalent resistances corresponding to the one or more parasitic resistances of the leaf cells outside the leaf cells at inputs of the leaf cells. (See Fig 3. Where the examiner understands the Resistance Network Graph (330) to make obvious the workflow described in the claim, which the examiner understands as essentially connecting the equivalent resistances of the leaf cells to each other in the netlist representation)
Teene_2014 does not expressly recite and short one or more terminals of each of the leaf cells to a central node of a corresponding one of the equivalent networks,
Zhou_2004 however makes obvious shorting one or more terminals of each of the leaf cells (see fig 9. “CUT LEAF GROUP ) to a central node of a corresponding one of the equivalent networks; (col 2 par 4: “The system and method 45 utilize, in one embodiment, an event driven simulator that divides or "cuts" along the hierarchical boundaries of the input netlist in order to produce subcircuits that are then converted into Thevenin equivalent circuit models. Once a Thevenin equivalent circuit model is computed, matrix 50 equations/computations are used to compute the cut node voltages and then sensitivity vectors may be used to determine the internal node voltages. The cut node voltages are stored in a flattened cut node voltage data structure that is dynamic. Internal node voltages may be stored in instance 55 specific dynamic data structures. This is done for each event.” (Examiners note: Where the process above involves conceptually “shorting one or more terminals of each of the leaf cells to a central node of a corresponding one of the equivalent networks;“ as is done in the netlist in light of the specifications)
Teene_2004, Singh_2021, and Zhou_2004 are analogous art to the claimed invention because they are from the same field of endeavor called circuit planning. Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to combine Teene_2004, Singh_2021, and Zhou_2004. The rationale for doing so would have been to follow a teaching and motivation proposed in the prior art. Firstly, Zhou_2004 col 1 par 3 states “Circuit simulators are computer implemented processes that can simulate the expected operation and behavior of a circuit design by applying a set of input signals to the netlist and propagating the resultant signals through the netlist to its output nodes. Circuit simulators can be used, in one way, to 35 verify that a netlist properly performs its specified operation and/or to measure the performance of the design.” And furthermore that col 14 line 5 “An advantage of the present invention is that the structural, e.g., static data, of the input netlist does not need to be flattened in order for the simulation to operate. By avoiding this flattening requirement ( that is required of the prior art), the present invention can operate using significantly less memory resources over a prior art simulator. …. Line 35: “Regarding hierarchical extraction, post-layout extraction with parasitics can be done hierarchically, but has not been done up to now because simulation tools could not take advantage of a hierarchical database (other than to reduce the amount of input data). This is because conventional simulators flatten a hierarchical database; so there is no advantage afforded by the effort of doing hierarchical extraction because the simulation tools that use the data will flatten it anyway. However, the cut procedure of the present invention makes hierarchical extraction a useful operation. In essence, a set of identical leaf cells that have identical layouts have identical internal parasitic elements, and these parasitic elements can be extracted once and shared among the set of identical leaf cells.“ Therefore, it would have been obvious to combine the parasitic resistance extraction process and hierarchical simulations of Teene_2004 and Sing_2021 with the netlist simplification method using equivalents of Zhou_2004 for the benefit of taking advantage of hierarchical extractions to simulate the performance of a design with parasitics using less memory to obtain the invention as specified in the claims.
Claims 4-6, 14-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Teene_2004, Singh_2021, Zhou_2004, Rubin_1994, and “A Floating-Gate Transmission-Line Model Technique for Measuring Source Resistance in Heterostructure Field-Effect Transistors” (Alamo_1989),
Claim 4:Teene_2014 makes obvious The method of claim 1, wherein the port to port resistances between the terminals of the internal circuits of the leaf cells are determined based on (see claim 1)
par 42: “There are two approaches to evaluate the equivalent point to point resistance … With the second approach, the resistance from a source to a single destination terminal is calculated. This approach gives the resistance between the two terminals when all other terminals are "floating." This allows for better comparison of individual resistance paths within the resistance network.
measuring a current between the first and second terminals of each of the internal circuits of the leaf cells to determine a measured current;
par 43: “A current matrix I is then created where Is is 1 for the source terminal s and Ii is O for all non source terminals i. The matrix equation V=I/G is then solved using the current matrix I (Examiner note: Where the source and drain terminals are the first and second terminals)
par 43: “The matrix equation V=I/G is then solved using the current matrix I and conductance
matrix G.”
determining a first resistance value between the first and second terminals
Par 43: “The source to destination resistance is then calculated as Rsd=(Vs/Vd)-1.” Examiner note: Resistance (source to drain) = (voltage source / voltage drain) -1. Where the current is 1.
Teen_2014 does not expressly recite a DC simulation of the leaf cells by:
applying a voltage between a first terminal and a second terminal of each of the internal circuits of the leaf cells to determine an applied voltage
measuring
Singh_2021 makes obvious a DC (See figure. 5C “type=dc”) simulation (col 2 par 1: “The simulator may then perform another round of simulation with the updated simulation view.”) of the leaf cells by (col 35 par 3: “the leaf hierarchical level”)
As already states, Teen_2014 and Singh_2021 are analogous art to the claimed invention because they are from the same field of endeavor called circuits. Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to combine Teen_2014 and Singh_2021. The rationale for doing so would have been to follow a teaching and motivation proposed in the art. Singh_2021 col 1 par 3 states “Circuit designers and verification engineers use different methods to verify circuit designs. One common method of verification is the use of simulation.” Therefore, it would have been obvious to combine the resistance extraction workflow of Teen_2014 with simulation of Singh_2021 for the benefit of verifying the circuit designs of Teene_2014 using the common method of verification to obtain the invention as specified in the claims.
Singh_2021 does not expressly recite applying a voltage between a first terminal and a second terminal of each of the internal circuits of the leaf cells to determine an applied voltage
measuring
Alamo_1989 however makes obvious applying a voltage between a first terminal and a second terminal of each of the internal circuits of the leaf cells to determine an applied voltage page 2388 col 2 par 2: “As Fig. 4(b) shows, current is now injected from the drain to the source. and the gate is left floating. There is no current through R,, and, therefore, the gate samples the voltage in the middle of the intrinsic channel. The three measured resistances are” Examiner note: Where the drain and source are a first and second terminal, and the gate is the other terminal. Where one ordinarily skilled in the art understands injecting a current to make obvious applying a voltage due to Ohms law.
measuring page 2388 col 2 par 2: There is no current through R,, and, therefore, the gate samples the voltage in the middle of the intrinsic channel.
determining a first resistance value between the first and second terminals by dividing the measured voltage by the measured current; and determining a second resistance value between the first and second terminals by dividing the applied voltage by the measured current
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Examiner note: Where one ordinarily skilled in the art would be able to apply these calculations for resistance (ohms law) to determine a first and second resistance value given a voltage and current as shown above.
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313
709
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Examiners note: Where the above makes obvious subtracting a first resistance value from the result to get the second resistance value. Where the first and second resistance are understood as Rs and Rd.
Teene_2014, and Alamo_1989 are analogous art to the claimed invention because they are from the same field of endeavor called measuring resistances . Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to combine Teene_2014, Singh_2021 and Alamo_1989.
The rationale for doing so would have been to follow a teaching and motivation proposed in the art. Alamo_1989 introduction states “In order to optimize device design by having a low source resistance, its value must first be accurately measured.” And Alamo_1989 conclusion states “A new simple technique to measure the source resistance in HFET’s, called the floating-gate transmission line model (FGTLM), has been developed. The technique is based on measurements taken on actual device structures of different gate lengths, with no need for dedicated test patterns.” Where HFET’s are a type of transistor. Teene_2014 displays an invention for analyzing and displaying the resistance of terminals in a network par 2; “The present invention is directed to an apparatus and method visualizing and analyzing resistance networks. More specifically, the present invention is directed to a mechanism for automatically generating a visual representation of a resistance network to facilitate visual verification and a mechanism for automatically generating equivalent point to point resistance.”
Therefore, it would have been obvious to combine the point to point resistance calculations of Teene_2014 with the workflow to calculate the source resistance of Alamo_1989 for the benefit of accurately measuring a source value with a simple technique for the analysis and display technique of Teene_2014 to obtain the invention as specified in the claims.
Claim 5:
Claim 5 is an effective duplicate of claim 4, except it describes a process of further analysis, where the steps of claim 4 are repeated for the “other” terminals. Alamo_1989 further makes this obvious. See page 2388 col 2: “A. Floating-Drain Configuration” “B. Floating-Gate Configuration” and “C. Floating-Source Configuration” Where the prior art of Alamo_1989 makes obvious repeating the process of claim 4 by testing the previously floated gate and floating the other gates. Therefore claim 5 is rejected in light of the rejection of claim 4 and the additional rational provided by Alamo_1989.
Claim 6:The method of claim 4, further comprising:
Alamo_1989 makes further obvious determining that an internal circuit from among the internal circuits of the leaf cells is missing a third terminal;
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Examiner note: Where the examiner understands this process as occurring in a leaf cell with internal circuits. Where a “third terminal” is considered missing.
applying a voltage between a counter-clockwise terminal from among the first terminal, the second terminal, and a fourth terminal of the internal circuit of the leaf cell and a terminal from among the first, second, and third terminals that is across from the missing third terminal, the counter-clockwise terminal being in a counter-clockwise position from the missing third terminal;
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Examiner note: Where applying a current makes obvious to one ordinarily skilled in the art applying a voltage due to the relationship between voltage and current.
measuring a current between the counter-clockwise terminal and the terminal across from the missing third terminal;
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Examiner note: Where the current is measured/ known.
measuring a voltage at a clockwise terminal from among the first, second, and fourth terminals, the clockwise terminal being in a clockwise position from the missing third terminal;
See page 2388 “There is no current through R,, and, therefore, the gate samples the voltage in the middle of the intrinsic channel” Where this passage makes obvious applying the same logic to configuration C and sampling the voltage at S.
and determining a resistance of the terminal across from the missing third terminal by dividing the voltage at the clockwise terminal by the current between the counter-clockwise terminal and the terminal across from the missing third terminal,
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Examiner note: Where one ordinarily skilled in the art would be able to apply these calculations for resistance (ohms law) to determine a first and second resistance value given a voltage and current as shown above.
and subtracting a resistance of the counter-clockwise terminal from a third result of the division.
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See equation 16 which makes obvious subtracting the resistance for G and D.
As stated previously it would have been obvious to combine the point to point resistance calculations of Teene_2014 with the workflow to calculate the source resistance of Alamo_1989 for the benefit of accurately measuring a source value with a simple technique for the analysis and display technique of Teene_2014 to obtain the invention as specified in the claims.
Claim 14:
Claim 14 is greater in scope to claim 4, where claim 4 contains all the limitations of claim 14, except that claim 14 depends on claim 10. Therefore, claim 14 is rejected under the same rational as claim 4 and 10.
Claim 15:
Claim 15 is effectively similar to claim 4, except that it depends on claim 14. Therefore, claim 15 is rejected under the same rational as claims 4 and 14.
Claim 16:
Claim 16 is effectively similar to claim 5, except that it depends on claim 14. Therefore, claim 16 is rejected under the same rational as claims 5 and 14.
Claim 17:
Claim 17 is effectively similar to claim 6, except that it depends from claim 15. Therefore, claim 17 is rejected under the same rational as claims 6 and 17.
Claim 20:Claim 20 is effectively similar to claim 4, except that it depends from claim 18. Therefore, claim 20 is rejected under the same rational as claims 4 and 18.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Teene_2004, Singh_2021, Zhou_2004, Rubin_1994, and “A perfect triode system 10 out of 10” (Lampizator_2010)
Claim 9:
Teene_2014 makes further obvious The system of claim 7, wherein a total number of resistors in each of the leaf cells are further iteratively reduced by combining serial, parallel, . (par 37: “The graph data structure of the resistance network may then be reduced using, for example, a single layer series and parallel reduction, all layers series and parallel reduction, layer specific reduction, or the like”)
Teene_2014 does not expressly recite and triode resistor configurations
Lampizator_2010 however makes obvious and triode resistor configurations (page 3 line 25; “In this system we use instead of anode resistor or anode choke - a triode which is configured to resist like a resistor “
Teene_2014 and Lampizator_2010 are analogous art to the claimed invention because they are from the same field of endeavor called circuits. Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to combine Teene_2014 and Lampizator_2010. The rationale for doing so would have been to apply a known technique to a known method ready for improvement to yield a predictable result. Teene_2014 describes simplifying networks into resistance values, as well as combining those resistance values. Teene_2014 states “par 37: “The graph data structure of the resistance network may then be reduced using, for example, a single layer series and parallel reduction, all layers series and parallel reduction, layer specific reduction, or the like” The prior art of Lampizator_2010 makes obvious the presence of Triode configurations as resistors and calculating those resistance. One ordinarily skilled in the art would recognize that when the invention of Teene_2014 is analyzing a triode configuration, that the prior art of teene_2014 would be applicable to all sorts of configurations known in the art and used in circuits. Therefore, it would have been obvious to combine the circuit resistance simplification of Teene_2014 with the explicit recitation of Triode resistors of Lampazitor_2010 to yield the predictable result of combining resistances to obtain the invention as specified in the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AHMAD HUSSAM SHALABY whose telephone number is (571)272-7414. The examiner can normally be reached Mon-Fri 7:30am - 5pm.
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/A.H.S./Examiner, Art Unit 2187
/EMERSON C PUENTE/Supervisory Patent Examiner, Art Unit 2187
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