DETAILED ACTION
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S. PGPub 2018/0135809) in view of Tsai (U.S. PGPub 2013/0146936) and Okabe (U.S. PGPub 2011/0018022).
Regarding claim 1, Kim teaches a manufacturing method of a semiconductor element, comprising: providing a substrate, forming a semiconductor stack on the substrate, forming an ohmic contact layer on the semiconductor stack (Fig. 6B, substrate 110, semiconductor stack 120, ohmic contact layer 130, [0094]-[0099]) and performing a mesa process on the semiconductor stack before forming post-processing steps (Fig. 7B, 120m, [0128], [0098]). Kim teaches wherein the ohmic contact layer is ITO ([0099]-[0100]), wherein a second electrode in a second opening of a passivation layer is formed in the post-processing steps, wherein a sidewall of the second electrode and a sidewall of the second opening are aligned, and a portion of the second electrode is disposed outside of the second opening (Fig. 10B, 153, 151, [0112]; 140, [0132]-[0133]; see attached annotated Fig. 10B).
Kim does not explicitly teach wherein the second electrode does not cover a top surface of a passivation layer, does not contact the second-type semiconductor layer, wherein a sidewall of the second electrode and a sidewall of a second opening of the passivation layer are aligned, and a portion of the second electrode is disposed outside of the second opening.
Kim teaches wherein the opening in the ohmic contact layer is optionally formed ([0102], “the contact electrode 130 may further include at least one second opening”; [0112], “In the structure wherein the contact electrode 130 includes the second opening”; [0130], “patterning of the contact electrode 130 may further include forming second openings that partially expose the second conductive type semiconductor layer). If the contact opening is not formed, the second electrode does not contact the second-type semiconductor layer.
Tsai teaches wherein a second electrode covers a top surface of a passivation layer (Fig. 12, [0107], 22, 24) and further teaches as a known alternative structure wherein the second electrode does not cover the top surface of the passivation layer, wherein a sidewall of the second electrode and a sidewall of a second opening of the passivation layer are aligned, and a portion of the second electrode is disposed outside of the second opening (Figs. 7 and 10, [0107]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Tsai with Kim such that the second electrode does not cover a top surface of a passivation layer, does not contact the second-type semiconductor layer, wherein a sidewall of the second electrode and a sidewall of a second opening of the passivation layer are aligned, and a portion of the second electrode is disposed outside of the second opening because the prior art teaches an structure which differs from the claim by substitution with a different structure, the claimed structure is known in the art, a person of ordinary skill could have substituted one known structure for another, and the combination would have yielded predictable results to one of ordinary skill in the art before the time of the invention. See MPEP 2143.I.B.
Kim further does not explicitly teach performing an annealing process on the ohmic contact layer and performing the mesa process after performing the annealing process.
Okabe teaches forming an ITO ohmic contact layer and performing an annealing process on the ohmic contact layer after deposition (109, [0049]-[0051]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Okabe with Kim such that the method comprises performing an annealing process on the ohmic contact layer and performing the mesa process after performing the annealing process for the purpose of improving the conductivity of the ohmic contact layer (Okabe, [0120]).
Regarding claim 2, the combination of Kim, Tsai, and Okabe teaches performing an isolation process on the semiconductor stack so that the semiconductor stack is divided into a plurality of separated parts (Kim, Figs. 7A-7B, 120i, [0128]-[0129]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Kim, Tsai, and Okabe for the reasons set forth in the rejection of claim 1.
Regarding claim 3, the combination of Kim, Tsai, and Okabe teaches forming a passivation layer on the ohmic contact layer and on the semiconductor stack (Kim, Fig. 8B, 140, [0132]-[0133]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Kim, Tsai, and Okabe for the reasons set forth in the rejection of claim 1.
Regarding claims 4-5, the combination of Kim, Tsai, and Okabe teaches wherein the mesa process comprises etching the semiconductor stack to form a platform and a concave surrounding the platform on the semiconductor stack, and the platform and the concave together form a stepped structure and performing an isolation process on the semiconductor stack so that the concave of the semiconductor stack is penetrated to divide the semiconductor stack into a plurality of separated parts (Kim, Figs. 7A-7B, 120i, [0128]-[0129]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Kim, Tsai, and Okabe for the reasons set forth in the rejection of claim 1.
Regarding claims 6-8, the combination of Kim, Tsai, and Okabe teaches wherein the semiconductor stack comprises a first-type semiconductor layer, a quantum well layer, and a second-type semiconductor layer stacked sequentially, wherein the first-type semiconductor layer is an N-type semiconductor layer and the first-type semiconductor layer is an P-type semiconductor layer (Kim, [0154]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Kim, Tsai, and Okabe for the reasons set forth in the rejection of claim 1.
Regarding claims 9-10, the combination of Kim, Tsai, and Okabe wherein the ohmic contact layer comprises a transparent conductive material, wherein the transparent conductive material is a crystallized indium tin oxide (Kim, [0099]-[0100]; Okabe, [0119]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Kim, Tsai, and Okabe for the reasons set forth in the rejection of claim 1.
Claims 11-15 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S. PGPub 2018/0135809) in view of Tsai (U.S. PGPub 2013/0146936).
Regarding claim 11, Kim teaches a first-type semiconductor layer, comprising a platform and a concave surrounding the platform, wherein the platform and the concave together form a stepped structure (121, [0154], Fig. 7B, 120m/120i, [0124]-[0128]); a quantum well layer disposed on the platform of the first-type semiconductor layer (123, [0154]), a second-type semiconductor layer disposed on the quantum well layer (125, [0154]), an ohmic contact layer disposed on the second type semiconductor layer (130, [0160]-[0161]); a first electrode electrically connected to the first type semiconductor layer and a second electrode electrically connected to the ohmic contact layer.
Kim does not explicitly teach wherein the second electrode does not cover a top surface of a passivation layer, does not contact the second-type semiconductor layer, wherein a sidewall of the second electrode and a sidewall of a second opening of the passivation layer are aligned, and a portion of the second electrode is disposed outside of the second opening.
Kim teaches wherein the opening in the ohmic contact layer is optionally formed ([0102], “the contact electrode 130 may further include at least one second opening”; [0112], “In the structure wherein the contact electrode 130 includes the second opening”; [0130], “patterning of the contact electrode 130 may further include forming second openings that partially expose the second conductive type semiconductor layer). If the contact opening is not formed, the second electrode does not contact the second-type semiconductor layer.
Tsai teaches wherein a second electrode covers a top surface of a passivation layer (Fig. 12, [0107], 22, 24) and further teaches as a known alternative structure wherein the second electrode does not cover the top surface of the passivation layer, wherein a sidewall of the second electrode and a sidewall of a second opening of the passivation layer are aligned, and a portion of the second electrode is disposed outside of the second opening (Figs. 7 and 10, [0107]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Tsai with Kim such that the second electrode does not cover a top surface of a passivation layer, does not contact the second-type semiconductor layer, wherein a sidewall of the second electrode and a sidewall of a second opening of the passivation layer are aligned, and a portion of the second electrode is disposed outside of the second opening because the prior art teaches an structure which differs from the claim by substitution with a different structure, the claimed structure is known in the art, a person of ordinary skill could have substituted one known structure for another, and the combination would have yielded predictable results to one of ordinary skill in the art before the time of the invention. See MPEP 2143.I.B.
Regarding claims 12-13, the combination of Kim and Tsai teaches wherein the first-type semiconductor layer is an N-type semiconductor layer and wherein the second-type semiconductor layer is a P-type semiconductor layer (Kim, [0154]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Kim, Tsai, and Okabe for the reasons set forth in the rejection of claim 11.
Regarding claim 14, the combination of Kim and Tsai teaches wherein the passivation layer disposed on the ohmic contact layer and on the first-type semiconductor layer, the passivation layer comprising a first opening and a second opening, wherein the first electrode electrically connected to the first-type semiconductor layer via the first opening and the second electrode is electrically connected to the ohmic contact layer via the second opening (Kim, 140, [0132]-[0133]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Kim, Tsai, and Okabe for the reasons set forth in the rejection of claim 11.
Regarding claim 15, the combination of Kim and Tsai teaches wherein the ohmic contact layer comprises a transparent conductive material (Kim, [0160]-[0161]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Kim, Tsai, and Okabe for the reasons set forth in the rejection of claim 11.
Regarding claims 17-20, the combination of Kim and Tsai teaches wherein the second electrode has a marginal portion and a central portion, a top surface of the second electrode is recessed from the marginal portion to the central portion, wherein a recess is in the central portion, wherein a height of the marginal portion is different from a height of the central portion (Kim, [0113], 153a). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Kim, Tsai, and Okabe for the reasons set forth in the rejection of claim 11.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S. PGPub 2018/0135809) in view of Tsai (U.S. PGPub 2013/0146936) and Okabe (U.S. PGPub 2011/0018022).
Regarding claim 16, the combination of Kim and Tsai further does not explicitly teach performing an annealing process on the ohmic contact layer and performing the mesa process after performing the annealing process.
Okabe teaches forming an ITO ohmic contact layer and performing an annealing process on the ohmic contact layer after deposition (109, [0049]-[0051]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Okabe with Kim and Tsai such that the method comprises performing an annealing process on the ohmic contact layer and performing the mesa process after performing the annealing process for the purpose of improving the conductivity of the ohmic contact layer (Okabe, [0120]).
Conclusion
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/ALIA SABUR/Primary Examiner, Art Unit 2812