DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Restriction to one of the following inventions is required under 35 U.S.C. 121:
I. Claims 1-11 and 14-20, drawn to an accelerator for performing a reciprocal square root operation of a single floating-point input operand, classified in at least G06F7/5525 - Roots or inverse roots of single operands.
II. Claims 12-13, drawn to a multiplier for performing a multiplication operation between a first operand by a second operand, classified in at least G06F 7/4876 – Multiplying.
The inventions are independent or distinct, each from the other because:
Inventions I and II are directed to related products. The related inventions are distinct if: (1) the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect; (2) the inventions do not overlap in scope, i.e., are mutually exclusive; and (3) the inventions as claimed are not obvious variants. See MPEP § 806.05(j). In the instant case, the inventions as claimed have a materially different design, mode of operation, function. Invention I requires an accelerator comprising a reciprocal square root component for generating a reciprocal square root of an input operand while Invention II requires a multiplier for generating a product of a first operand and a second operand. Furthermore, the inventions as claimed do not encompass overlapping subject matter and there is nothing of record to show them to be obvious variants.
Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply:
The inventions require a different field of search, including different classification search and search queries. For instance, Invention I requires a search in G06F7/5525 - Roots or inverse roots of single operands and a search for the concept of an accelerator comprising a reciprocal square root component for generating a reciprocal square root of an input operand while the search for Invention II does not. Invention II requires a search in G06F 7/4876 – Multiplying and a search for the concept of a multiplier for generating a product of a first operand and a second operand while the search for Invention II does not.
Applicant is advised that the reply to this requirement to be complete must include (i) an election of an invention to be examined even though the requirement may be traversed (37 CFR 1.143) and (ii) identification of the claims encompassing the elected invention.
The election of an invention may be made with or without traverse. To reserve a right to petition, the election must be made with traverse. If the reply does not distinctly and specifically point out supposed errors in the restriction requirement, the election shall be treated as an election without traverse. Traversal must be presented at the time of election in order to be considered timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are added after the election, applicant must indicate which of these claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
During a telephone conversation with Applicant’s Representative, Attorney for Applicant, Susan Yee, Registration Number 41388, on 09/23/2026, a provisional election was made without traverse to prosecute the invention of Group I, claims 1-11 and 14-20. Affirmation of this election must be made by applicant in replying to this Office action. Claims 12-13 are withdrawn from further consideration by the examiner, 37 CFR 1.142(b), as being drawn to a non-elected invention.
Applicant is reminded that upon the cancelation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17(i).
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
A. instructions comprising a reciprocal square root instruction as specified in claim 2
B. wherein the reciprocal square root component includes a precomputed table as specified in claim 4
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 728 in Figure 7
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
The abstract is objected to because it refers to purported merits of the invention. Further, the abstract does not include the organization and operation of the system or the steps of the process.
Appropriate correction is required.
Claim Objections
Claims 7 and 16 are objected to under 37 C.F.R. 1.75(d)(1) which requires the claim or claims must conform to the invention as set forth in the remainder of the specification and the terms and phrases used in the claims must find clear support or antecedent basis in the description so that the meaning of the terms in the claims may be ascertainable by reference to the description. Therefore, the following should be corrected.
A. In claim 7 line 2, “infinity (+
∞
)” should read “positive infinity (+
∞
)” instead. Claim 16 recites a similar limitation in line 2 as is objected to for the same reason.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
A. reciprocal square root component first recited in claim 1
B. instruction decode unit in claim 2
C. data fetch unit in claim 2
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
A. reciprocal square root component (first recited in claim 1): see paragraph [0069] “implement the … reciprocal square root component 604 with "nand4_ 2," "fulladder," "and3 _ 2" cells, or a combination thereof. Any precomputed table (e.g., … reciprocal square root component 604) can be implemented as a read-only memory (ROM)”
B. instruction decode unit (claim 2): see Fig. 1 reference numeral 116 and paragraph [0024] instruction decode unit is a conventional instruction decoder
C. data fetch unit (claim 2): see Fig. 1 reference numeral 110 and paragraph [0026] instruction decode unit is a conventional data fetch unit
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 10, 14 and 20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Gschwind et al. (US 20130212139 A1), hereinafter Gschwind.
Regarding claim 1, Gschwind teaches an integrated circuit comprising:
an accelerator that receives an input operand comprising an input exponent and an input mantissa and performs operations to generate an output, the accelerator comprising (Gschwind Fig. 2 and paragraphs [0031-0033] accelerator – 200; input operand – 205; output – 230):
a selector that selects the output (Gschwind Fig. 2 and paragraph [0032] selector – multiplexer 225);
a reciprocal square root component that provides a resultant with a value in a range of [1.0,2.0) to the selector (Gschwind Fig. 2 and paragraphs [0032-0033] reciprocal square root component – 210; resultant - computed value from 210 (i.e., 230)); and
a detector that detects whether the input operand is zero, infinity, or non- numeric and provides a value to the selector based on the input operand being zero, infinity, or non-numeric (Gschwind Fig. 2 and paragraphs [0032-0033] detector – 215, 220 and/or Nan logic).
Regarding claim 10, Gschwind teaches all the limitations of claim 1 as stated above. Further, Gschwind teaches wherein the selector selects the resultant from the reciprocal square root component as the output based on the input operand being positive non-zero finite (Gschwind Fig. 2 and paragraph [0032] “If nothing is detected by the zero detection 215 and the infinity detect 220, the multiplexer 225 passes the computed value from the reciprocal estimate function 210, and this computed value is a single precision result value 230”).
Regarding claims 14 and 20, they are directed to a method practiced by the circuit of claims 1 and 10 respectively. All steps performed by the method of claims 14 and 20 would be practiced by the circuit of claims 1 and 10 respectively. Claims 1 and 10 analysis applies equally to claims 14 and 20 respectively.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Gschwind as applied to claim 1 above, and further in view of Heinecke et al. (US 20240045683 A1), hereinafter Heinecke.
Regarding claim 2, Gschwind teaches all the limitations of claim 1 as stated above. Further, Gschwind teaches
wherein the accelerator is an execution unit (Gschwind Figs. 2-3 and paragraph [0042] “the circuits 312 are configured to compute the reciprocal estimate of the input value at block 520. Computing the reciprocal estimate at block 520 can include the description discussed for diagram 200 in FIG. 2”) and
.
Gschwind does not explicitly teach the integrated circuit further comprises: an instruction decode unit that decodes instructions comprising a reciprocal square root instruction; and a data fetch unit that accesses the input operand based on the reciprocal square root instruction.
However, on the same field of endeavor, Heinecke discloses an integrated circuit comprising an instruction decode unit that decodes instructions comprising a reciprocal square root instruction; a data fetch unit that accesses the input operand based on the reciprocal square root instruction; and an execution unit for executing the instructions to calculate a reciprocal square root (Heinecke Figs. 3-4 and 11A-11B and paragraphs [0050, 0052, 0058-0063, 0071, 0103-0107] instruction decode unit - decode stage/circuitry; reciprocal square root instruction - instruction to calculate a reciprocal square root (VRSQRTNEPFP8); data fetch unit - register read/memory read stage/circuitry).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Gschwind using Heinecke and configure the processor to include a processor pipeline including an instruction decode unit that decodes instructions comprising a reciprocal square root instruction; and a data fetch unit that accesses the input operand based on the reciprocal square root instruction; and the execution unit to execute the reciprocal square root instruction and generate the output value. One of ordinary skill in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. The predictable result is a processor pipeline for configured to process a reciprocal square root instruction and generate an output result. See MPEP 2141 subsection III(A) for more information.
Therefore, the combination of Gschwind as modified in view of Heinecke teaches the integrated circuit further comprises: an instruction decode unit that decodes instructions comprising a reciprocal square root instruction; and a data fetch unit that accesses the input operand based on the reciprocal square root instruction.
Regarding claim 3, Gschwind as modified in view of Heinecke teaches all the limitations of claim 1 as stated above. Further, Gschwind as modified in view of Heinecke teaches wherein the instruction decode unit and the data fetch unit are comprised within a single unit (Heinecke paragraph [0103] “In one example, the decode stage 1106 and the register read/memory read stage 1114 may be combined into one pipeline stage”).
Claims 4, 8-9, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Gschwind as applied to claims 1 and 14 above, and further in view of Fossum et al. (US 6654777 B1), hereinafter Fossum.
Regarding claim 4, Gschwind teaches all the limitations of claim 1 as stated above.
Gschwind does not explicitly teach wherein the reciprocal square root component includes a precomputed table.
However, on the same field of endeavor, Fossum discloses a reciprocal square root component that includes a precomputed table (Fossum Fig. 4 and col 7 lines 15-17; precomputed table – lookup table 402).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Gschwind using Fossum and configure the reciprocal estimate function 210 to include the circuit arrangement of the inverse square root circuit 400 of Fossum that includes a lookup table 402 in order to improve performance of the reciprocal square root component over software solutions by implementing a hardware circuit that calculates the reciprocal square root function (Fossum col 5 lines 43-47).
Therefore, the combination of Gschwind as modified in view of Fossum teaches wherein the reciprocal square root component includes a precomputed table.
Regarding claim 8, Gschwind teaches all the limitations of claim 1 as stated above.
Gschwind does not explicitly teach wherein the selector selects the output representing non-numeric based on the input operand being negative non-zero.
However, on the same field of endeavor, Fossum discloses selecting and outputting an output representing non-numeric based on an input operand being negative non-zero (Fossum Fig. 5 and col 8 lines 61-65 “Floating point circuit 500 includes a multiplexer circuit, represented by the decision block 502, that determines if the input is a negative number (by examining the sign bit S) and, if so, generates (block 504) a predetermined NaN value for the output”).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Gschwind using Fossum and configure the circuit to include additional logic for detecting whether the input operand is negative by examining the sign bit and configure the multiplexer to output a NaN value if the input operand is negative for handling the special case where the input is negative (Fossum col 6 lines 19-20; col 8 lines 54-57).
Therefore, the combination of Gschwind as modified in view of Fossum teaches wherein the selector selects the output representing non-numeric based on the input operand being negative non-zero.
Regarding claim 9, Gschwind teaches all the limitations of claim 1 as stated above. Further, Gschwind teaches the circuit may further have logic to handle the replication of a NaN input to a NaN output (Gschwind paragraph [0033]).
Gschwind does not explicitly teach wherein the selector selects the output representing non-numeric based on the input operand being non-numeric.
However, on the same field of endeavor, Fossum discloses selecting and outputting an output representing non-numeric based on an input operand being non-numeric (Fossum Fig. 5 and col 8 line 65 to col 9 line 2 “The floating point circuit 500 further includes a multiplexer circuit represented by block 506 that determines if the input value is an IEEE NaN and, if so, generates (block 508) a predetermined NaN as the output”).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Gschwind using Fossum and configure the circuit to include additional logic for detecting whether the input operand is non-numeric and configure the multiplexer to output a NaN value if the input operand is non-numeric for handling the special case where the input is non-numeric (Fossum col 5 lines 48-53; col 8 lines 54-57).
Therefore, the combination of Gschwind as modified in view of Fossum teaches wherein the selector selects the output representing non-numeric based on the input operand being non-numeric.
Regarding claims 17-18, they are directed to a method practiced by the circuit of claims 8-9 respectively. All steps performed by the method of claims 17-18 would be practiced by the circuit of claims 8-9 respectively. Claims 8-9 analysis applies equally to claims 17-18 respectively.
Claims 5 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Gschwind as applied to claims 1 and 14 above, and further in view of Xi et al. (US 20230161554 A1), hereinafter Xi.
Regarding claim 5, Gschwind teaches all the limitations of claim 1 as stated above.
Gschwind does not explicitly teach wherein the accelerator further comprises a subtracter and a negater that generates an unbounded exponent based on the input exponent.
However, on the same field of endeavor, Xi discloses computing a reciprocal function comprising subtracting the bias exponent and negating the bias exponent to compute the exponent value of the output (Xi Fig. 2 and paragraph [0058]).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Gschwind using Xi and configure circuit 200 to include a subtracter and a negater in order to provide circuit components for computing the exponent value of the output (Xi paragraph [0058]). As discussed in paragraphs [0032-0033] of Gschwind, the result value 230 is a floating-point number. Therefore, it would be obvious to include components for computing the exponent part of the result value.
Therefore, the combination of Gschwind as modified in view of Xi teaches wherein the accelerator further comprises a subtracter and a negater that generates an unbounded exponent based on the input exponent.
Regarding claim 19, they are directed to a method practiced by the circuit of claim 5. All steps performed by the method of claim 19 would be practiced by the circuit of claim 5. Claim 5 analysis applies equally to claim 19.
Claims 6-7 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Gschwind as applied to claims 1 and 14 above, and further in view of Moudgill et al. (US 20220129262 A1), hereinafter Moudgill.
Regarding claim 6, Gschwind teaches all the limitations of claim 1 as stated above. Further, Gschwind teaches wherein the selector selects the output representing positive zero based on the input operand (Gschwind Fig. 2 and paragraph [0032]).
Gschwind does not explicitly teach wherein the selector selects the output representing positive zero based on the input operand being zero.
However, on the same field of endeavor, Moudgill discloses selecting an output representing positive zero based on an input operand being zero (Moudgill paragraphs [0081, 0122] and table 1).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Gschwind using Moudgill and configure the selector to select the output representing positive zero based on the input operand being zero in order to calculate a square root of the input operand and/or provide a unified circuit for calculating both square root and reciprocal square root functions (Moudgill paragraphs [0081, 0121-0123] and table 1).
Therefore, the combination of Gschwind as modified in view of Moudgill teaches wherein the selector selects the output representing positive zero based on the input operand being zero.
Regarding claim 7, Gschwind teaches all the limitations of claim 1 as stated above. Further, Gschwind teaches wherein the selector selects the output representing infinity (+
∞
) based on the input operand
∞
(Gschwind Fig. 2 and paragraph [0032]).
Gschwind does not explicitly teach wherein the selector selects the output representing infinity (+
∞
) based on the input operand being infinity (+
∞
).
However, on the same field of endeavor, Moudgill discloses selecting an output representing infinity (+
∞
) based on an input operand being infinity (+
∞
) (Moudgill paragraphs [0081, 0121] and table 1).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Gschwind using Moudgill and configure the selector to select the output representing infinity (+
∞
) based on the input operand being infinity (+
∞
) in order to calculate a square root of the input operand and/or provide a unified circuit for calculating both square root and reciprocal square root functions (Moudgill paragraphs [0081, 0121-0123] and table 1).
Therefore, the combination of Gschwind as modified in view of Moudgill teaches wherein the selector selects the output representing infinity (+
∞
) based on the input operand being infinity (+
∞
).
Regarding claims 15-16, they are directed to a method practiced by the circuit of claims 6-7 respectively. All steps performed by the method of claims 15-16 would be practiced by the circuit of claims 6-7 respectively. Claims 6-7 analysis applies equally to claims 15-16 respectively.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Gschwind as applied to claim 1 above, and further in view of Shearer (US 20060271615 A1).
Regarding claim 11, Gschwind teaches all the limitations of claim 1 as stated above. Further, Gschwind teaches (Gschwind Fig. 11 and paragraphs [0079-0080]).
Gschwind does not explicitly teach wherein the accelerator is further configured to perform a multiplication operation using the resultant and a second input operand by multiplying the resultant and the second input operand to obtain a multiplication result, the multiplication result comprising a result exponent and a result mantissa.
However, on the same field of endeavor, Shearer discloses performing a multiplication operation using a resultant of reciprocal square root calculation and a second input operand by multiplying the resultant and the second input operand to obtain a multiplication result (Shearer paragraph [0009] resultant - reciprocal square root approximation; second input operand – input; multiplication result – product (square root approximation)).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Gschwind using Shearer and configure the accelerator to perform a multiplication operation using the resultant and a second input operand by multiplying the resultant and the second input operand to obtain a floating-point multiplication result in order to further calculate a square root of the input operand and/or provide a circuit for calculating both square root and reciprocal square root functions (Shearer paragraph [0009]).
Therefore, the combination of Gschwind as modified in view of Shearer teaches wherein the accelerator is further configured to perform a multiplication operation using the resultant and a second input operand by multiplying the resultant and the second input operand to obtain a multiplication result, the multiplication result comprising a result exponent and a result mantissa.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Pasca (US 9904512 B1) directed to a floating-point unit for performing floating-point operations including inverse square root operation and square root operation including exception handling for special cases in both inverse square root operation and square root operation as shown in Fig. 5A.
Foskett et al. (US 7117238 B1) directed to performing an inverse and inverse square root operation including exception handling for the special cases for both inverse and inverse square root operation. The handling of the special cases for the inverse square root operation is disclosed in col 12 lines 9-36.
Steele et al. (US 20030014454 A1) directed to performing a square root operation including exception handling for the special cases as shown in Fig. 3.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlo Waje whose telephone number is (571)272-5767. The examiner can normally be reached 9:00-6:00 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Carlo Waje/Examiner, Art Unit 2151 (571)272-5767
