Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 7/17/2026 have been fully considered but they are not persuasive. The applicant argues that the amended claims are not taught by the prior art. Details can be found in the updated rejections of the claims below.
Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
Applicant's arguments do not comply with 37 CFR 1.111(c) because they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. Further, they do not show how the amendments avoid such references or objections.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-8, 10-17, and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bachmutsky (US 2022/0222010 as listed on the IDS filed 6/13/2024).
In regards to claim 1, Bachmutsky teaches
An apparatus comprising, comprising: an ingress path to receive a memory and/or storage access request generated by a central processing unit (CPU), the access request capable of being sharded into multiple shards, wherein individual shards included in the multiple shards are separately addressed to different logical partitioned memory and/or storage resources an egress path to direct a response to the access request to the CPU; (fig. 7, switch 700 with ingress and egress buffers to receive/send messages/data. ¶26 an application (i.e. from a CPU of a server, see fig. 2) sends (i.e. via ingress path) memory requests to the switch, and the switch responds to the request by supplying the requested data to the application (i.e. to a CPU of a server via an egress path). ¶26 the switch can split a request into N separate requests, each going to a different memory pool of the network. ¶63, 65 and fig. 6 teaches the memory regions may be partitioned into sub-regions (i.e. logical partitioned memory and/or storage resources), and the different storage locations associated with the read are identified (step 604) and then the request can be split (sharded) into multiple unicast requests with addresses endpoints to the appropriate memory nodes/pools (storage resources )
circuitry coupled to the ingress path and the egress path, (fig. 2, 7, switch)
the circuitry to divide the access request into multiple access requests based on information that defines respective memory and/or storage addresses for respective shards from among the multiple shards and direct the multiple access requests toward a network, the circuitry to receive respective multiple responses to the multiple access requests for the multiple shards and construct the response. (¶26 the switch can split a request into N separate requests, each going to a different memory pool of the network, the separate responses are then aggregated into a single response back to the application. ¶63, 65 and fig. 6 teaches the different storage locations associated with the read are identified (step 604) and then based on this information, in step 612 the request can be split (sharded) into multiple unicast requests with addresses endpoints to the appropriate memory nodes/pools (storage resources ). ¶50, fig. 4, the switch maintains an interleaving configuration table 438 that includes an address range field 442 a list of pools 444 and an interleave ID field 440 that identifies a corresponding range in global memory space that are associated with certain interleaving configurations that define which memory pools are employed for different memory regions and the associated type of memory allocation interleaving applied)
In regards to claim 3, Bachmutsky further teaches
wherein the information is to be stored in memory that is coupled to the logic circuitry. (fig. 7, ¶78, the request table 428, configuration table 438, and system address decoder 418 are stored in memory 716 of the switch)
In regards to claims 4-5, Bachmutsky further teaches
wherein the logic circuitry is to construct an in flight record for the multiple access requests. wherein the logic circuitry is to delete the record as a consequence of the respective multiple responses having been received. (¶49, fig. 4, pending queue logic 408 maintains data in a request table 428 to track pending responses (i.e. an in flight record of the multiple access requests that are then used to gather the data from the multiple responses and combine them into a single response returned to the originator. Once the response is sent the originator, then the multiple requests would no longer be considered pending and therefore removed form the request table 428 used by the pending queue logic 408).
In regards to claim 6, Bachmutsky further teaches
wherein, if the memory and/or storage access request is a write request, the logic circuitry is to manipulate the address of the write request to generate a different, unique address for each of the multiple access requests for the multiple shards based on the information that defines respective memory and/or storage addresses for respective shards from among the multiple shards. (fig. 6, ¶61-69 teaches for a received write request (step 602) the decoder can identify the interleaving ranges (i.e. addresses of the different pools to send the multiple requests to), and then can issue either a multicast to all the memory pools to write the data to their indicated memory addresses, or multiple unicast requests with addresses (i.e. different, unique addresses) can be sent to the applicable memory node/pools)
In regards to claim 7, Bachmutsky further teaches
if the memory and/or storage access request is a read request, the logic circuitry is to receive portions of read data with the respective multiple responses and combine the portions of data into complete read data. (¶26, ¶67, fig. 6, for a read request (steps 616, 618) the read responses are gathered from the memory nodes and the data portions received from each memory pool is aggregated (i.e. combined into complete read data) and returned to the requestor)
In regards to claim 8, Bachmutsky teaches
An infrastructure processing unit, comprising: a) a processing core; b) an ASIC block and/or a field programmable gate array (FPGA); c) at least one machine readable medium having software to execute on the processing core and/or firmware to program the FPGA; wherein, logic associated with the processing core and software, ASIC block, and/or FPGA and firmware is to perform i) through vi) below: (¶76-78, fig. 7, CPU/IPU 714, with programmable logic FPGA 720 and/or preprogrammed logic, ASICs, and firmware 718 storage (machine readable medium) that contains instructions/modules executed by the CPU/IPU to implement the FPGA 720 and other associated functions)
The remainder of the claim is similar to claim 1 and rejected for the same reasons as stated above.
In regards to claims 10-14, the claims are substantially similar to respective claims 3-7 and rejected for the same reasons as detailed above.
In regards to claim 15, Bachmutsky teaches
A computing system, comprising: (fig. 8B, system 820)
a) a network; (fig. 8B, ¶80-81, interconnection links 826, and switches 818 that are interconnected to the memory and storage pools and compute drawers of the racks (i.e. a network)
b) a memory pool coupled to the network; (fig. 8B, ¶81, memory pools in pooled memory drawers 812 and pooled memory sled 816)
c) a storage pool coupled to the network; (fig. 8B, ¶81, storage resources in pooled storage drawers 808)
d) a plurality of central processing units (CPUs) coupled to the network; (fig. 8B, ¶81, compute resources in pooled compute drawers 806 (plurality of CPUs)
e) circuitry to perform i) through vi) below: (fig. 8B, ¶80, switch 818)
The remainder of the claim is similar to claim 1 and is rejected for the same reasons as stated above.
In regards to claim 16, Bachmutsky further teaches
wherein the circuitry is within the network. (fig. 8B, ¶80-81 switches 818 (circuitry) are part of the “network”)
In regards to claim 17, Bachmutsky further teaches
wherein the circuitry is between the CPU and the network. (fig. 8B, ¶80-81 switches 818 (circuitry) are between the CPUs 806 and the other part of the “network” links 826 connecting the memory/storage resources)
In regards to claims 19-20, the claims are substantially similar to respective claims 4-5 and rejected for the same reasons as detailed above.
EXAMINER’S NOTE
Examiner has cited particular paragraphs, figures, and/or columns and line numbers in the references applied to the claims above for the convenience of the Applicants. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicants in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON W BLUST whose telephone number is (571)272-6302. The examiner can normally be reached 12-8:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571) 272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON W BLUST/Primary Examiner, Art Unit 2132
