DETAILED ACTION
This Office action is in response to the election filed on 09 March 2026. Claims 1-20 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species I, on which claims 1-12 are readable, in the reply filed on 09 March 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 4 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Singh et al., US 2021/0375666.
With respect to claim 1, Singh et al. disclose a semiconductor device, shown in Fig. 12B, comprising:
a bulk substrate 4 including a first region 300 and a second region 100 (see Fig. 12B and paragraph [0066]);
a buried oxide layer 6 and a semiconductor layer 10C stacked on the first region 300 (see Fig. 12B and paragraph [0066]);
a first gate structure 52C/54C (see paragraphs [0100]-[0104]) disposed on the semiconductor layer 10C, as shown in Fig. 12B;
a first source/drain layer 31C/39C disposed at an upper portion of the semiconductor layer 10C adjacent to the first gate structure 52C/54C (see Fig. 12B and paragraphs [0105];
a second gate structure 52A/54A disposed on the second region 100; and
a second source/drain layer 31A/39A disposed at an upper portion of the bulk substrate 4 adjacent to the second gate structure 52A/54A (Body region 10A is “an upper portion of the bulk substrate 4.),
wherein: the first gate structure 52C/54C includes: a first gate insulation structure 52C disposed on the semiconductor layer 10C; and a first gate electrode 54C disposed on the first gate insulation structure 52C,
the second gate structure i52A/54A includes: a second gate insulation structure 52A disposed on the bulk substrate 4; and a second gate electrode 54A disposed on the second gate insulation structure 52A,
a thickness of the first gate insulation structure 52C is less than a thickness of the second gate insulation structure 52A, and
an upper surface of the first gate structure 52C/54C is lower than an upper surface of the second gate structure 52A/54A with respect to a direction perpendicular to an upper surface of the bulk substrate 4, as shown in Fig. 12B.
With respect to claim 4, in the semiconductor device of Singh et al., the bulk substrate 4 further includes a third region 200, the semiconductor device further comprises: a third gate structure 52B/54B disposed on the third region 200; and a third source/drain layer 31B/39B disposed at an upper portion of the bulk substrate 4 adjacent to the third gate structure 52B/54B (Body region 10B is “an upper portion of the bulk substrate 4.), the third gate structure includes: a third gate insulation structure 52B disposed on the bulk substrate 4; and a third gate electrode 54B disposed on the third gate insulation structure 52B, and a thickness of the third gate insulation structure 52B is greater than the thickness of the first gate insulation structure 52C and smaller than the thickness of the second gate insulation structure 52A, as shown in Fig. 12B.
Claims 1, 9, and 10 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Singh et al., US 2021/0375666.
With respect to claim 1, Singh et al. disclose a semiconductor device, shown in Fig. 12B, comprising:
a bulk substrate 4 including a first region 200 and a second region 100 (see Fig. 12B and paragraph [0066]);
a buried oxide layer 6 and a semiconductor layer 10B stacked on the first region 200 (see Fig. 12B and paragraph [0066]);
a first gate structure 52B/54B (see paragraphs [0100]-[0104]) disposed on the semiconductor layer 10B, as shown in Fig. 12B;
a first source/drain layer 31B/39B disposed at an upper portion of the semiconductor layer 10BC adjacent to the first gate structure 52B/54B (see Fig. 12B and paragraphs [0105];
a second gate structure 52A/54A disposed on the second region 100; and
a second source/drain layer 31A/39A disposed at an upper portion of the bulk substrate 4 adjacent to the second gate structure 52A/54A (Body region 10A is “an upper portion of the bulk substrate 4.),
wherein: the first gate structure 52B/54B includes: a first gate insulation structure 52B disposed on the semiconductor layer 10B; and a first gate electrode 54B disposed on the first gate insulation structure 52B,
the second gate structure i52A/54A includes: a second gate insulation structure 52A disposed on the bulk substrate 4; and a second gate electrode 54A disposed on the second gate insulation structure 52A,
a thickness of the first gate insulation structure 52B is less than a thickness of the second gate insulation structure 52A, and
an upper surface of the first gate structure 52B/54B is lower than an upper surface of the second gate structure 52A/54A with respect to a direction perpendicular to an upper surface of the bulk substrate 4, as shown in Fig. 12B.
With respect to claim 9, in the semiconductor device of Singh et al., the bulk substrate 4 further includes a third region 100, and the buried oxide layer 6 and the semiconductor layer 10C are stacked on the third region 100, the semiconductor device further comprises: a third gate structure 52C/54C on a portion of the semiconductor layer 10C on the third region 100; and a third source/drain layer 31C/39C at an upper portion of the semiconductor layer 10C adjacent to the third gate structure 52C/54C, the third gate structure 52C/54C includes: a third gate insulation structure 52C on the portion of the semiconductor layer 10C; and a third gate electrode 54C on the third gate insulation structure, and a thickness of the third gate insulation structure 52C is less than the thickness of the first gate insulation structure 52B.
With respect to claim 10, in the device of Singh et al., an upper surface of the third gate structure 52C/54C is lower than the upper surface of the first gate structure 52B/54B, as shown in Fig. 12B.
Claims 1 and 12 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Lee et al., US 2020/0303512.
With respect to claim 1, Lee et al. disclose a semiconductor device, shown in Fig. 5, comprising:
a bulk substrate 100 including a first region (on the left in Fig. 5) and a second region (on the right in Fig. 5);
a buried oxide layer 101 and a semiconductor layer 105 stacked on the first region (see Fig. 5 and paragraph [0023]);
a first gate structure GI1/GE1 disposed on the semiconductor layer 105;
a first source/drain layer 131/133 disposed at an upper portion of the semiconductor layer 105 adjacent to the first gate structure GE1, as shown in Fig. 5;
a second gate structure GI2/GE2 disposed on the second region; and
a second source/drain layer 136 disposed at an upper portion of the bulk substrate 100 adjacent to the second gate structure GE2,
wherein: the first gate structure GE1 includes: a first gate insulation structure GI1 disposed on the semiconductor layer 105; and a first gate electrode GE1 disposed on the first gate insulation structure GI1,
the second gate structure GI2/GE2 includes: a second gate insulation structure GI2 disposed on the bulk substrate 101; and a second gate electrode GE2 disposed on the second gate insulation structure GI2,
a thickness of the first gate insulation structure GI1 is less than a thickness of the second gate insulation structure GI2, and
an upper surface of the first gate structure GE1 is lower than an upper surface of the second gate structure GE2 with respect to a direction perpendicular to an upper surface of the bulk substrate 101, as shown in Fig. 5.
With respect to claim 12, in the semiconductor device of Lee et al., one or more of the first and second gate structures extends in a second direction D1 substantially parallel to the upper surface of the bulk substrate 100, as shown in Fig. 5, the semiconductor device further comprises: a first gate spacer ST1 on one or more of opposite sidewalls in a first direction D2 of the first gate electrode GE1, the first direction D2 being substantially parallel to the upper surface of the bulk substrate and crossing the second direction D1; and a second gate spacer ST2 on one or more of opposite sidewalls in the first direction D1 of the second gate electrode GE2, and the first gate insulation structure GI1 covers lower surfaces of the first gate electrode GE1 and the first gate spacer ST1, and the second gate insulation structure GI2 covers lower surfaces of the second gate electrode GE2 and the second gate spacer ST2, as shown in Fig. 5.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US 2020/0303512, as applied to claim 1 above, further in view of Makiyama et al., US 2013/0087855.
Lee et al. is applied as above. Lee et al. lack anticipation the limitations of dependent claims 2 and 3 with respect to the widths and lengths of the gate electrode.
With respect to claim 2, in the same filed of endeavor, Makiyama et al. disclose two SOI transistors in regions Rsn and Rsp and two bulk transistors in regions Rbn and Rbp, as shown in Fig. 17. Makiyama et al. disclose that the gate electrodes 24 of the SOI transistors have a width less than the width of the gate electrodes 33/34 of the bulk transistors, as shown in Fig. 17. In light of this teaching of Makiyama et al, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a width in a first direction of the first gate electrode is less than a width in the first direction of the second gate electrode, the first direction being substantially parallel to the upper surface of the bulk substrate and crossing the second direction.
With respect to claim 3, Makiyama et al. disclose that the gate length of an SOI type MISFET is e.g. 65 nm approximately, and that of a bulk type MISFET is e.g. 160 nm approximately, see paragraph [0069]. Since the gate insulating structure of each transistor underlies the entire gate electrode of the transistor, the length of the gate electrode of a transistor is equal to the length of the gate insulation structure of the transistor. Therefore, in light of this teaching of Makiyama et al, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a length in a first direction of the first gate insulation structure GI1 would be less than a length in the first direction of the second gate insulation structure GI2, the first direction being substantially parallel to the upper surface of the bulk substrate and crossing the second direction.
The limitations of dependent claims 2 and 3 are not deemed to patentably distinguish Applicant’s claimed semiconductor device from that of Lee et al.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US 2020/0303512, as applied to claim 1 above, further in view of Maekawa et al., US 2018/0286850.
Lee et al. is applied as above. Lee et al. lack anticipation of forming a third transistor in a third region, wherein a thickness of the third gate insulation structure is greater than the thickness of the first gate insulation structure and smaller than the thickness of the second gate insulation structure. In the same field of endeavor, Maekawa et al. disclose a high breakdown voltage in region 4A, as shown in Fig. 2. Maekawa et al. disclose the high breakdown voltage transistor Q4 is formed in the high breakdown voltage transistor region 4A, which is a MISFET formed in an I/O region and driven by a relatively high voltage, see paragraph [0051]. Lee et al. disclose that the first gate insulation structure has a relatively small thickness, see paragraph [0039]. Lee et al. show in Fig. 5 that the second gate insulation structure GI2 has a very large thickness, see also paragraphs [0047]-[0048]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the
bulk substrate could further includes a third region comprising a high breakdown voltage transistor, the semiconductor device further comprises: a third gate structure GI4/G4 disposed on the third region; and a third source/drain layer D4/E4 disposed at an upper portion of the bulk substrate adjacent to the third gate structure, the third gate structure includes: a third gate insulation structure GI4 disposed on the bulk substrate; and a third gate electrode G4 disposed on the third gate insulation structure GI4, and a thickness of the third gate insulation structure GI4 is greater than the thickness of the first gate insulation structure GI1 (which is relatively small) and smaller than the thickness of the second gate insulation structure GI2 (which is very thick).
With respect to claim 5, as shown in Fig. 2 of Maekawa et al., the upper surface of the gate structure G4 is lower than all the other gate structures on the substrate SB. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that an upper surface of the third gate structure could be lower than the upper surface of the first gate structure GI1/GE1 in the known semiconductor device of Lee et al..
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Singh et al., US 2021/0375666, as applied to claim 4 above.
With respect to claim 6, as shown in Figs. 12B and 13B of Singh et al., the first gate structure and the first source/drain layer form a first transistor in region 300, the second gate structure and the second source/drain layer form a second transistor in region 100, and the third gate structure and the third source/drain layer form a third transistor in region 200. However, Singh et al. fail to disclose a voltage applied to the third transistor is greater than a voltage applied to the first transistor and smaller than a voltage applied to the second transistor. However, the present claims are drawn to a semiconductor device. It has been well established that the manner of operating a device does not patentably differentiate the claimed device from a prior art device which is structurally the same. "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987)
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Singh et al., US 2021/0375666, as applied to claim 9 above.
With respect to claim 11, as shown in Figs. 12B and 13B of Singh et al., the first gate structure and the first source/drain layer form a first transistor in region 200, the second gate structure and the second source/drain layer form a second transistor in region 100, and the third gate structure and the third source/drain layer form a third transistor in region 100. However, Singh et al. fail to disclose a voltage applied a voltage applied to the third transistor is less than a voltage applied to the first transistor and smaller than a voltage applied to the second transistor. However, the present claims are drawn to a semiconductor device. It has been well established that the manner of operating a device does not patentably differentiate the claimed device from a prior art device which is structurally the same. "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987)
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Singh et al., US 2021/0375666, as applied to claim 4 above, further in view of Baars et al. US 2016/0204128.
Singh et al. is applied as above. Singh et al. clearly teach one or more of the first to third gate structures extends in a second direction substantially parallel to the upper surface of the bulk substrate, as shown in Fig. 12B. Singh et al. lacks anticipation of a width in a first direction of the third gate electrode is greater than a width in the first direction of the first gate electrode and smaller than a width in the first direction of the second gate electrode, the first direction being substantially parallel to the upper surface of the bulk substrate and crossing the second direction. In the same field of endeavor, Baars et al. disclose a semiconductor device comprising three transistors with the gate electrodes of each having a different width, as shown in Fig.6b, since the width of the gate electrode can influence the transistor performance, since narrower gates result in faster switching times, which translates to faster processing speeds. However, higher voltages can be applied to wider gates. Therefore, in light of the teaching of Baars et al., the purview of the skilled artisan, and the desired use of the transistors in the semiconductor device of Singh et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a width in a first direction of the third gate electrode is greater than a width in the first direction of the first gate electrode and smaller than a width in the first direction of the second gate electrode, the first direction being substantially parallel to the upper surface of the bulk substrate and crossing the second direction.
Allowable Subject Matter
Claims 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Although Singh et al. disclose a third transistor, Singh et al. fail to teach or suggest one or more of the first to third gate structures extends in a second direction substantially parallel to the upper surface of the bulk substrate, and wherein a length in a first direction of the third gate insulation structure is greater than a length in the first direction of the first gate insulation structure and smaller than a length in the first direction of the second gate insulation structure, the first direction being substantially parallel to the upper surface of the bulk substrate and crossing the second direction.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additionally cited references disclose semiconductor devices comprising a plurality of transistors.
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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