DETAILED ACTION
This Office action is in response to the Amendment filed on 16 June 2026. Claims 1-20 are pending in the application. Claims 13-20 have been withdrawn from consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species I, on which claims 1-12 are readable, in the reply filed on 09 March 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US 2020/0303512, of record, in view of Iwamatsu, US 2012/0146148, newly cited.
With respect to claim 1, Lee et al. disclose a semiconductor device, shown in Fig. 5, comprising:
a bulk substrate 100 including a first region (on the left in Fig. 5) and a second region (on the right in Fig. 5);
a buried oxide layer 101 and a semiconductor layer 105 stacked on the first region (see Fig. 5 and paragraph [0023]);
a first gate structure GI1/GE1 disposed on the semiconductor layer 105;
a first source/drain layer 131/133 disposed at an upper portion of the semiconductor layer 105 adjacent to the first gate structure GE1, as shown in Fig. 5;
a second gate structure GI2/GE2 disposed on the second region; and
a second source/drain layer 136 disposed at an upper portion of the bulk substrate 100 adjacent to the second gate structure GE2,
wherein: the first gate structure GE1 includes: a first gate insulation structure GI1 disposed on the semiconductor layer 105; and a first gate electrode GE1 disposed on the first gate insulation structure GI1,
the second gate structure GI2/GE2 includes: a second gate insulation structure GI2 disposed on the bulk substrate 101; and a second gate electrode GE2 disposed on the second gate insulation structure GI2,
a thickness of the first gate insulation structure GI1 is less than a thickness of the second gate insulation structure GI2, and
an upper surface of the first gate structure GE1 is lower than an upper surface of the second gate structure GE2 with respect to a direction perpendicular to an upper surface of the bulk substrate 101, as shown in Fig. 5,
wherein the second gate insulation structure GI2 includes first and second insulation patterns 111 and 179, respectively, as shown in Fig. 5, stacked sequentially on the bulk substrate 100m see Fig. 5 and paragraphs [0052]-[0053].
Independent claim 1 has been amended to further require a lower surface of the second insulation pattern (179) is coplanar with a lower surface of the semiconductor layer 105. Admittedly, this limitation is not shown in Fig. 5 of Lee et al., although Lee et al. do discuss that the thickness of both the second insulation pattern 179 and the semiconductor layer can be varied, see paragraphs [0021], [0023], [0043] and [0053]. In the same field of endeavor, Iwamatsu discloses a memory device which includes SOI regions, see Fig. 20, in which a lower surface of the second insulation pattern 12ss is coplanar with a lower surface of the semiconductor layer 9, as shown in Figs. 10-11. In light of the disclosures of Lee et al. as to varying the thicknesses of both the second insulation pattern 179 and the semiconductor layer 105, and of Iwamatsu that a lower surface of the second insulation pattern 12ss can be coplanar with a lower surface of the semiconductor layer 9, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a lower surface of the second insulation pattern (179) could have been coplanar with a lower surface of the semiconductor layer 105 in the known semiconductor device of Lee et al. This limitation is not deemed to patentably distinguish Applicant’s claimed device from the known device of Lee et al. in light of the disclosures of Lee et al. and Iwamatsu.
With respect to claim 12, in the semiconductor device of Lee et al., one or more of the first and second gate structures extends in a second direction D1 substantially parallel to the upper surface of the bulk substrate 100, as shown in Fig. 5, the semiconductor device further comprises: a first gate spacer ST1 on one or more of opposite sidewalls in a first direction D2 of the first gate electrode GE1, the first direction D2 being substantially parallel to the upper surface of the bulk substrate and crossing the second direction D1; and a second gate spacer ST2 on one or more of opposite sidewalls in the first direction D1 of the second gate electrode GE2, and the first gate insulation structure GI1 covers lower surfaces of the first gate electrode GE1 and the first gate spacer ST1, and the second gate insulation structure GI2 covers lower surfaces of the second gate electrode GE2 and the second gate spacer ST2, as shown in Fig. 5.
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US 2020/0303512, in view of Iwamatsu, US 2012/0146148, as applied to claim 1 above, further in view of Makiyama et al., US 2013/0087855, of record.
Lee et al. and Iwamatsu are applied as above. Lee et al. lack anticipation of the limitations of dependent claims 2 and 3 with respect to the widths and lengths of the gate electrodes.
With respect to claim 2, in the same filed of endeavor, Makiyama et al. disclose two SOI transistors in regions Rsn and Rsp and two bulk transistors in regions Rbn and Rbp, as shown in Fig. 17. Makiyama et al. disclose that the gate electrodes 24 of the SOI transistors have a width less than the width of the gate electrodes 33/34 of the bulk transistors, as shown in Fig. 17. In light of this teaching of Makiyama et al, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a width in a first direction of the first gate electrode is less than a width in the first direction of the second gate electrode, the first direction being substantially parallel to the upper surface of the bulk substrate and crossing the second direction.
With respect to claim 3, Makiyama et al. disclose that the gate length of an SOI type MISFET is e.g. 65 nm approximately, and that of a bulk type MISFET is e.g. 160 nm approximately, see paragraph [0069]. Since the gate insulating structure of each transistor underlies the entire gate electrode of the transistor, the length of the gate electrode of a transistor is equal to the length of the gate insulation structure of the transistor. Therefore, in light of this teaching of Makiyama et al, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a length in a first direction of the first gate insulation structure GI1 would be less than a length in the first direction of the second gate insulation structure GI2, the first direction being substantially parallel to the upper surface of the bulk substrate and crossing the second direction. The limitations of dependent claims 2 and 3 are not deemed to patentably distinguish Applicant’s claimed semiconductor device from that of Lee et al.
Claims 4, 5, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US 2020/0303512, in view of Iwamatsu, US 2012/0146148, as applied to claim 1 above, further in view of Maekawa et al., US 2018/0286850, of record.
Lee et al. and Iwamatsu are applied as above. Lee et al. lack anticipation of forming a third transistor in a third region, wherein a thickness of the third gate insulation structure is greater than the thickness of the first gate insulation structure and smaller than the thickness of the second gate insulation structure. In the same field of endeavor, Maekawa et al. disclose a high breakdown voltage in region 4A, as shown in Fig. 2. Maekawa et al. disclose the high breakdown voltage transistor Q4 is formed in the high breakdown voltage transistor region 4A, which is a MISFET formed in an I/O region and driven by a relatively high voltage, see paragraph [0051]. Lee et al. disclose that the first gate insulation structure has a relatively small thickness, see paragraph [0039]. Lee et al. show in Fig. 5 that the second gate insulation structure GI2 has a very large thickness, see also paragraphs [0047]-[0048]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the
bulk substrate could further includes a third region comprising a high breakdown voltage transistor, the semiconductor device further comprises: a third gate structure GI4/G4 disposed on the third region; and a third source/drain layer D4/E4 disposed at an upper portion of the bulk substrate adjacent to the third gate structure, the third gate structure includes: a third gate insulation structure GI4 disposed on the bulk substrate; and a third gate electrode G4 disposed on the third gate insulation structure GI4, and a thickness of the third gate insulation structure GI4 is greater than the thickness of the first gate insulation structure GI1 (which is relatively small) and smaller than the thickness of the second gate insulation structure GI2 (which is very thick).
With respect to claim 5, as shown in Fig. 2 of Maekawa et al., the upper surface of the gate structure G4 is lower than all the other gate structures on the substrate SB. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that an upper surface of the third gate structure could be lower than the upper surface of the first gate structure GI1/GE1 in the known semiconductor device of Lee et al..
With respect to claim 6, Lee et al. in view of Maekawa et al. disclose the first gate structure GI1/GE1 and the first source/drain layer 131/133 form a first transistor, the second gate structure GI2/GE2 and the second source/drain layer 136 form a second transistor, and the third gate structure GI4/G4 and the third source/drain layer D4/E4 form a third transistor. Although, Maekawa et al. recognize that different voltages may be applied to the different transistors in a device (see paragraph [0009]: “An operating method of a semiconductor device according to another embodiment, which includes a first transistor, a fourth transistor that is driven by a higher voltage than that of the first transistor…”) and the transistor Q4 formed in the I/O region is driven by a relatively high voltage, see paragraph [0051], neither Lee et al. or Maekawa et al. disclose a voltage applied to the third transistor is greater than a voltage applied to the first transistor and smaller than a voltage applied to the second transistor. However, the present claims are drawn to a semiconductor device. It has been well established that the manner of operating a device does not patentably differentiate the claimed device from a prior art device which is structurally the same. "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987) Requiring a voltage applied to the third transistor is greater than a voltage applied to the first transistor and smaller than a voltage applied to the second transistor is not deemed to patentably distinguish Applicant’s claimed device from the known device of Lee et al. in view of Maekawa et al.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US 2020/0303512, in view of Iwamatsu, US 2012/0146148, further in view of Maekawa et al., US 2018/0286850, as applied to claim 4 above, further in view of Baars et al., US 2016/0204128, of record.
Lee et al., Iwamatsu, and Maekawa et al. are applied as above. Lee et al. and Maekawa et al. clearly teach one or more of the first to third gate structures extends in a second direction substantially parallel to the upper surface of the bulk substrate. However, neither Lee et al. nor Maekawa et al, teach a width in a first direction of the third gate electrode is greater than a width in the first direction of the first gate electrode and smaller than a width in the first direction of the second gate electrode, the first direction being substantially parallel to the upper surface of the bulk substrate and crossing the second direction. In the same field of endeavor, Baars et al. disclose a semiconductor device comprising three transistors with the gate electrodes of each having a different width, as shown in Fig.6b, since the width of the gate electrode can influence the transistor performance, since narrower gates result in faster switching times, which translates to faster processing speeds. However, higher voltages can be applied to wider gates. Therefore, in light of the teaching of Baars et al. and those of Maekawa et al., in light of the desired use of the transistors in the semiconductor device of Lee et al. in view of Maekawa et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a width in a first direction of the third gate electrode is greater than a width in the first direction of the first gate electrode and smaller than a width in the first direction of the second gate electrode, the first direction being substantially parallel to the upper surface of the bulk substrate and crossing the second direction.
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US 2020/0303512, in view of Iwamatsu, US 2012/0146148, as applied to claim 1 above, further in view of Singh et al., US 2021/0375666, of record.
Lee et al. and Iwamatsu are applied as above. Lee et al. lack anticipation of the bulk substrate further including a third region, and the buried oxide layer and the semiconductor layer are stacked on the third region, the semiconductor device further comprises: a third gate structure on a portion of the semiconductor layer on the third region; and a third source/drain layer at an upper portion of the semiconductor layer adjacent to the third gate structure, the third gate structure includes: a third gate insulation structure on the portion of the semiconductor layer; and a third gate electrode on the third gate insulation structure, and a thickness of the third gate insulation structure is less than the thickness of the first gate insulation structure. In the same field of endeavor, Singh et al. disclose a hybrid semiconductor device for both storing and processing data within a single device, the device comprising a bulk substrate 4 further including a third region 100, and a buried oxide layer 6 and a semiconductor layer 10C stacked on the third region 100, the device further comprising: a third gate structure 52C/54C on a portion of the semiconductor layer 10C on the third region 100; and a third source/drain layer 31C/39C at an upper portion of the semiconductor layer 10C adjacent to the third gate structure 52C/54C, the third gate structure 52C/54C includes: a third gate insulation structure 52C on the portion of the semiconductor layer 10C; and a third gate electrode 54C on the third gate insulation structure, and a thickness of the third gate insulation structure 52C is less than the thickness of the first gate insulation structure 52B. In light of the device of Singh et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the device of Lee et al. could include a third gate structure on a portion of the semiconductor layer on a third region; and a third source/drain layer at an upper portion of the semiconductor layer adjacent to the third gate structure, the third gate structure includes: a third gate insulation structure on the portion of the semiconductor layer; and a third gate electrode on the third gate insulation structure, and a thickness of the third gate insulation structure is less than the thickness of the first gate insulation structure, thereby providing transistors with desired characteristics with reduced processing complexity.
With respect to claim 10, in the device of Singh et al., an upper surface of the third gate structure 52C/54C is lower than the upper surface of a first gate structure 52B/54B, as shown in Fig. 12B. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that an upper surface of the third gate structure 52C/54C could have been lower than the upper surface of the first gate structure GI1/GE1 in the known device of Lee et al..
With respect to claim 11, in the combination of Lee et al. and Singh et al., the first gate structure GI1/GE1 and the first source/drain layer131/133 form a first transistor, the second gate structure GI2/GE2 and the second source/drain layer 136 form a second transistor, and the third gate structure 52C/54C and the third source/drain layer 31C/39C form a third transistor. However, neither Lee et al. nor Singh et al. disclose a voltage applied to the third transistor is less than a voltage applied to the first transistor and smaller than a voltage applied to the second transistor. However, the present claims are drawn to a semiconductor device. It has been well established that the manner of operating a device does not patentably differentiate the claimed device from a prior art device which is structurally the same. "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987) Requiring a voltage applied to the third transistor is greater than a voltage applied to the first transistor and smaller than a voltage applied to the second transistor is not deemed to patentably distinguish Applicant’s claimed device from the known device of Lee et al. in view of Maekawa et al.
Allowable Subject Matter
Claims 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Although Lee et al. in view of Maekawa et al. or Singh et al. disclose a third transistor, none of the references of record teach or suggest one or more of the first to third gate structures extends in a second direction substantially parallel to the upper surface of the bulk substrate, and wherein a length in a first direction of the third gate insulation structure is greater than a length in the first direction of the first gate insulation structure and smaller than a length in the first direction of the second gate insulation structure, the first direction being substantially parallel to the upper surface of the bulk substrate and crossing the second direction.
Response to Arguments
Applicant’s arguments with respect to claims 1-12 have been considered but are moot in light of the new grounds of rejection based on Lee et al. in view of US 2012/0146148.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additionally cited references disclose semiconductor devices comprising a plurality of transistors.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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