DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
RE: the rejection of claim(s) 1, 20 under 35 USC 103, Applicant’s arguments and/or amendments have been fully considered but are moot as further search and consideration have prompted the new grounds of rejection presented herein.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 5, 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP2019016631A (“Nakatsubo”) in view of US 20150194584 A1 (“Higashiuchi”), further in view of US 20060124946 A1 (“Fujita”).
RE: Claim 1, Nakatsubo discloses A film package (10 in FIGs. 1 to 3, FIG. 9, with or without adhesive layer 16; FIG. 3 shows the 10 with 16; FIG. 9 shows a portion of 10 without adhesive layer 16, [0025], [0093]) comprising:
a film substrate (11, 12 in FIGs. 2-3, [0022], [0029]) having a first side (left side of 11 in FIG. 2) and a second side (right side of 11 in FIG. 2) opposing each other;
a semiconductor chip (combination of top left 2 and left solder 17 in FIGs. 2-3, hereafter “first chip”, [0026]) disposed on a top surface of the film substrate and having first side surfaces (In FIG. 2, vertical side surfaces of 2) extending in a first direction (vertical direction in FIG. 2) to face the first side and the second side and second side surfaces (In FIG. 2, horizontal side surfaces of 2) extending in a second direction (horizontal direction in FIG. 2), intersecting the first direction;
a wiring pattern (13 including 131, 132 in FIGs. 2-3, [0037]) electrically connected to the semiconductor chip and including an input pattern (131) extending toward the first side on the film substrate and an output pattern (132) extending toward the second side on the film substrate;
a protective layer (14 in FIG. 3, [0042]) disposed on the top surface of the film substrate to cover at least a portion of the wiring pattern and having a first opening (opening defined by 14 in which the first chip is disposed, hereafter “first opening”) in which the semiconductor chip is disposed, and a second opening (opening defined by 14 in which any other LED 2, e.g., LED 2 in top row adjacent to the top left LED 2 in FIG. 2, is disposed, hereafter “second opening”; the any other LED 2 is hereafter “second chip”) that is spaced apart from the first opening and that exposes a portion of the top surface of the film substrate (In FIG. 3, the opening defined by 14 exposes 11, 12; Accordingly, for each LED 2, each opening defined by 14 would expose 11, 12; In FIG. 2, each chip 2 is spaced from every other chip 2 in the top row; Accordingly, each opening of 14 would be spaced from every other opening of 14 in the top row); and
a thermally conductive film (15 is a reflector including reflective material
silver-deposited polyester, [0063], see also [0062]; As 15 includes silver, 15 is considered thermally conductive; Note the reference KR100813142B1 (“Gim”) discloses a silver-deposited polyester film reflector includes silver, pg. 3, lines 9-15; Accordingly, the silver-deposited polyester film 15 is understood as including silver; therefore, the film 15 is thermally conductive) disposed on a top surface of the protective layer.
Nakatsubo does not explicitly disclose:
a thermally conductive resin including a first resin disposed on the first opening to cover the semiconductor chip, and a second resin disposed on the second opening to cover the portion of the top surface of the film substrate that is exposed through the second opening;
the thermally conductive film having a first through-hole exposing at least a portion of the first resin and a second through-hole exposing at least a portion of the second resin.
However, in the same field of endeavor, Higashiuchi discloses The transparent sealing resin 40 seals the blue LED 30 and is filled into the internal space 22 formed by the reflector 20, [0045], see FIG. 1.
Higashiuchi discloses The transparent sealing resin 40 may further include an inorganic filling material diffusing light, [0045]. Accordingly, Higashiuchi teaches that the resin may not be completely transparent.
Higashiuchi further discloses As the transparent sealing resin 40, acrylic resin is preferably adopted, from the viewpoint of transparency, [0045].
FIG. 1 shows the resin 40 covering side surfaces of the chip 30, and the top surface of the chip 30.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to fill spaces between each LED element 2 and corresponding reflectors 15 with a transparent sealing resin, and to cover the top surface of the LED element 2 with the transparent sealing resin as taught by Higashiuchi in order to seal the LED element 2 and improve protection for the LED element 2.
In the same field of endeavor, Fujita discloses an optical transmitter 21 in FIG. 14, [0181].
Fujita further discloses The light-emitting element 3 and a driver IC 19 are encapsulated in the mold resin 9 and protected from outside air, [0181].
Fujita further discloses the resin for molding is preferably a resin containing a filler having a low linear expansivity such as silica. Such a resin can be a resin in black color (linear expansivity: 15 to 20 ppm/K, thermal conductivity: about 0.7 W/mK), which is generally used in packaging of ICs that require no optical properties. Such resins are in general use and thus available at a low cost. According to the present invention, the difference between each one of the light-emitting element 3 and bonding wire 33 and the mold resin 9 in linear expansivity can be significantly reduced, so that thermal stress created on the light-emitting element 3 and the bonding wire 33 can be reduced. Since the filler is contained, the thermal conductivity of the resin itself is increased with the result that heat dissipation of the light-emitting element 3 and of the driver IC 19 also can be improved, [0186].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a silica filler in the sealing resin as taught by Fujita in order to improve the thermal conductivity of the resin.
As a result, Nakatsubo modified by Higashiuchi, Fujita discloses:
a thermally conductive resin (sealing resin from Higashiuchi, with the silica filler from Fujita) including a first resin disposed on the first opening to cover the semiconductor chip (a first sealing resin would be on top and side surfaces of each LED chip 2 and therefore the first sealing resin would be on the first opening to at least partially cover the first chip as seen in Nakatsubo FIG. 3), and a second resin disposed on the second opening to cover the portion of the top surface of the film substrate that is exposed through the second opening (a second sealing resin would be on top and side surfaces of the second chip and therefore the second sealing resin would be on the second opening, thereby covering the portion of the top surface of 11, 12 exposed through the second opening from at least a top view);
the thermally conductive film (15) having a first through-hole (first through-hole defined by 15 for the first chip as seen in Nakatsubo FIG. 3) exposing at least a portion of the first resin (the first sealing resin would be on the top surface of the first chip which is exposed from 15, therefore the first through-hole of 15 would also expose the first sealing resin) and a second through-hole (second through-hole defined by 15 for the second chip) exposing at least a portion of the second resin (the second sealing resin would be on the top surface of the second chip which is exposed from 15, therefore the second through-hole of 15 would also expose the second sealing resin).
RE: Claim 2, Nakatsubo in view of Higashiuchi, Fujita discloses The film package of claim 1, wherein the first through-hole has a width equal to or greater than a width of the second side surfaces of the semiconductor chip in the second direction (As the gap in 13 is seen in FIG. 3, and the gap in 13/131,132 in FIG. 2 extends in the second direction, the horizontal direction in FIG. 3 is the second, i.e., horizontal direction in FIG. 2; Accordingly, FIG. 3 shows the first through-hole of 15 having a width equal to or greater than a width of the second side surfaces of the semiconductor chip in the second direction).
RE: Claim 5, Nakatsubo in view of Higashiuchi, Fujita discloses The film package of claim 1, wherein the second through-hole has a width greater than a width of the second opening (From Nakatsubo FIG. 3: 16 is further considered part of the claimed protective layer, the second opening would be defined by the combination of 14, 16; 16 is a heat-resistant acrylic adhesive [0073]; Accordingly, 16 would protect 13 and the chip 2 from outside heat and therefore correspond to part of the claimed protective film; FIG. 3 shows a through-hole defined by 15 is greater than a width of the opening defined by 16; Accordingly, the second-through-hole would have a width greater than a width of the second opening).
RE: Claim 13, Nakatsubo in view of Higashiuchi, Fujita discloses The film package of claim 1, wherein the first through-hole has a width smaller than a width of the first side surfaces of the semiconductor chip in the first direction (FIG. 6 shows the opening in 15 includes cuts 153 having a width smaller than a first width (“first width”) between opposing sidewalls 151 in the vertical direction and smaller than a second width (“second width”) between opposing sidewalls 151 in the horizontal direction, [0056]; Nakatsubo teaches a device without the adhesive 16, [0093]; Accordingly, without the adhesive 16, each sidewall 151 would be in direct contact with a respective side surface of the first chip; therefore, the first width would be the same as the width of the chip in the first/vertical direction, the second width would be the same as the width of the chip in the second/horizontal direction and therefore the width of the cuts 153 in the vertical direction in FIG. 6 would be smaller than the width of the first/vertical side surfaces of the first chip in the vertical direction, and the width of the cuts 153 in the horizontal direction in FIG. 6 would be smaller than the width of the second/horizontal side surfaces of the first chip in the horizontal direction; Note the term “cut” has been defined as “a product of cutting: such as a (1): an opening made with an edged instrument,” see definition 1a for the noun “cut” by Merriam-Webster available at < https://www.merriam-webster.com/dictionary/cut>; Accordingly, under a broad reasonable interpretation, a cut is an opening, and therefore the cuts 153 in 15 are considered part of the first through-hole).
Claim(s) 3, 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakatsubo, in view of Higashiuchi, Fujita as applied to claim 2 or 5 above, and further in view of US 20110309394 A1 (“Lai”).
RE: Claim 3, Nakatsubo in view of Higashiuchi, Fujita does not explicitly disclose The film package of claim 2, wherein the width of the first through-hole is about 800 μm or more.
In the same field of endeavor, Lai discloses Preferably, the LED die 32 has a width ranging from 100 μm to 5000 μm, [0023].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a width such as 900 μm or 5000 μm for the first chip as this would have been obvious to try since these are solutions for the width of an LED chip identified by Lai and this would have had a reasonable expectation of success, see MPEP 2143. As a result, since the first chip is in the first through hole of 15, the first through hole would have a width of 800 μm or more.
RE: Claim 6, Nakatsubo in view of Higashiuchi, Fujita does not explicitly disclose The film package of claim 5, wherein the width of the second opening is about 600 μm or more.
In the same field of endeavor, Lai discloses Preferably, the LED die 32 has a width ranging from 100 μm to 5000 μm, [0023].
In the same field of endeavor, Lai discloses Preferably, the LED die 32 has a width ranging from 100 μm to 5000 μm, [0023].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a width such as 700 μm or 5000 μm for the first and second chips as this would have been obvious to try since these are solutions for the width of an LED chip identified by Lai and this would have had a reasonable expectation of success, see MPEP 2143. As a result, since the second chip is in the second opening defined by 16, the second opening would have a width of 600 μm or more.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakatsubo, in view of Higashiuchi, Fujita as applied to claim 1 above, and further in view of US 20160254154 A1 (“Heo”).
RE: Claim 4, Nakatsubo in view of Higashiuchi, Fujita does not explicitly disclose The film package of claim 1, wherein the second opening is an alignment key for the thermally conductive film.
In the same field of endeavor, Heo discloses the eighth opening 2360P(or the fifth opening 2360) may be used as an alignment key for verifying or confirming an alignment status of the semiconductor substrate 2100 in an wafer processing apparatus such as an exposure apparatus, [0057].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the second opening in 14 as an alignment key as taught by Heo in order to confirm an alignment status of the LED chips 2 in Nakatsubo which would at least partially confirm an alignment status for the reflector 15.
Further the limitation “wherein the second opening is an alignment key for the thermally conductive film” is considered an intended use limitation as any opening could potentially be used as an alignment key. MPEP 2114 states that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus if the prior art apparatus teaches all the structural limitations of the claim.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakatsubo, in view of Higashiuchi, Fujita as applied to claim 1 above, and further in view of US 20200124786 A1 (“Heo-2”).
RE: Claim 7, Nakatsubo in view of Higashiuchi, Fujita discloses The film package of claim 1, wherein the thermally conductive resin covers entirely an upper surface of the semiconductor chip (As modified by Hagauchi, the transparent sealing resin would cover entirely the upper surface of the first chip in order to seal the first chip).
Alternatively, if Applicant considers Nakatsubo in view of Higashiuchi, Fujita does not explicitly disclose wherein the thermally conductive resin covers entirely an upper surface of the semiconductor chip:
In the same field of endeavor, Heo-2 discloses the resin part 30 completely covers the upper surface of the LED chip, [0090].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to completely (i.e., entirely) cover the upper surface of the first chip as taught by Heo-2 in order to seal the upper surface of the first chip, thereby protecting the upper surface of the first chip.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakatsubo, in view of Higashiuchi, Fujita, Heo as applied to claim 7 above, and further in view of US 6278193 B1 (“Coico”).
RE: Claim 8, Nakatsubo in view of Higashiuchi, Fujita, Heo does not explicitly disclose The film package of claim 7, wherein the semiconductor chip has a marking region located on the upper surface of the semiconductor chip, and the marking region is located within the first through-hole on a plane.
In the same field of endeavor, Coico discloses The upper side of the chip includes chip alignment marks 21 (e.g., indentations, slits, printed marks, etc.), Col. 3, lines 20-25, see FIG. 2.
FIG. 2 shows the alignment marks are on an upper surface of the chip 12.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include an indentation as an alignment mark on an upper surface of the first chip as taught by Coico in order to better align the first chip. As an indentation is defined as “the blank space produced by indenting,” see definition 1a by Merriam-Webster at <https://www.merriam-webster.com/dictionary/indentation> and indent is defined as “to force inward so as to form a depression,” see definition 1 for the verb “indent” by Merriam-Webster at <https://www.merriam-webster.com/dictionary/indent>. Accordingly, under a broad reasonable interpretation, the indentation would form a depression in the upper surface of the first chip 2. Accordingly, as the top surface of 2 is coplanar with the top surface of 15 in FIG. 3, the indentation would include a depressed or recessed surface within the first through hole, and this indentation would be on a plane of the bottom surface of the first chip 2.
Claim(s) 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakatsubo in view of Higashiuchi, further in view of Fujita as applied to claim 1, further in view of US20090262520A1 (“Park”).
RE: Claim 9, Nakatsubo in view of Higashiuchi, Fujita discloses The film package of claim 1, wherein the thermally conductive resin includes a transparent resin and a heat dissipation filler in the transparent resin (As modified the sealing resin includes transparent resin from Higashiuchi, containing the heat dissipation silica filler from Fujita).
Nakatsubo in view of Higashiuchi, Fujita does not explicitly disclose the silica filler is dispersed in the transparent resin.
In the same field of endeavor, Park discloses The thermoplastic resin board may further include a thermally conductive filler in a dispersed form, [0013].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the silica filler in the sealing resin in a dispersed form as taught by Park in order to more uniformly improve the thermal conductivity of the sealing resin.
RE: Claim 10, Nakatsubo in view of Higashiuchi, Fujita, Park discloses The film package of claim 9, wherein the transparent resin includes at least one of an epoxy resin, an acrylic resin, a polyamide-based resin, a urethane-based resin, a urea-based resin, a melamine-based resin, a polyester-based resin, a phenoxy resin, a phenol- based resin, a silicone-based resin, a polyethylene resin, a polypropylene resin, a polystyrene resin, a polyvinyl chloride resin, a chlorinated polyethylene resin, a polychlorinated butyral resin, or an ethylene vinyl acetate resin (As modified, the sealing resin includes acrylic resin from Higashiuchi, [0045]).
RE: Claim 11, Nakatsubo in view of Higashiuchi, Fujita, Park discloses The film package of claim 9, wherein the heat dissipation filler includes at least one of silicon carbide, magnesium oxide, titanium dioxide, aluminum nitride, silicon nitride, boron nitride, aluminum oxide, silica, zinc oxide, barium titanate, strontium titanate, beryllium oxide, manganese oxide, zirconia oxide, or boron oxide (As modified, the heat dissipation filler is silica from Fujita, [0186]).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakatsubo, in view of Higashiuchi, Fujita as applied to claim 1 above, and further in view of US 20130200413 A1 (“Kashiwagi”).
RE: Claim 12, Nakatsubo in view of Higashiuchi, Fujita discloses The film package of claim 1, further comprising: a connection bump (From Nakatsubo: righthand solder 17 in FIG. 3) that connects the semiconductor chip to the wiring pattern.
Nakatsubo in view of Higashiuchi, Fujita does not explicitly disclose:
an underfill resin that surrounds the connection bump in the first opening.
In the same field of endeavor, Kashiwagi discloses in FIG. 4B:
an underfill resin (8 is silicone resin, [0137]) that surrounds a connection bump (9).
Kashiwagi further discloses protection of the bump 9 and the element 3 is performed by injecting and curing the underfill resin, [0137].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to surround the bumps 17 with an underfill resin as taught by Kashiwagi in order to protect the bumps 17. Since the bumps 17 are in the first opening of protective layer 14, the underfill resin surrounding the bumps 17 would also be in the first opening.
Claim 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakatsubo in view of Higashiuchi, further in view of Fujita, further in view of Park.
RE: Claim 20 Nakatsubo discloses A film package (10 in FIGs. 1 to 3) comprising:
a film substrate (11, 12 in FIGs. 2-3, [0022], [0029]);
a semiconductor chip (combination of top left 2 and left solder 17 in FIGs. 2-3, hereafter “first chip”, [0026]) disposed on the film substrate;
a wiring pattern (13 including 131, 132 in FIGs. 2-3, [0037]) electrically connected to the semiconductor chip and extending to an edge of the film substrate (the word “to” is defined as “used as a function word to indicate direction toward,” see definition 1a for the adverb “to” by Merriam-Webster available at https://www.merriam-webster.com/dictionary/to, accessed on March 30, 2026; Accordingly, under a broad reasonable interpretation, the wiring pattern 13 extends to the left and right edges of 11 in FIG. 2 as the wiring pattern 13 extends toward the left and right edges of 11 in FIG. 2);
a protective layer (14 in FIG. 3, [0042]) disposed on the film substrate to cover at least a portion of the wiring pattern and having an opening (opening defined by 14 in which the first chip is disposed, hereafter “first opening”) in which the semiconductor chip is disposed;
a thermally conductive film (15 is a reflector including reflective material silver-deposited polyester, [0063], see also [0062]; As 15 includes silver, 15 is considered thermally conductive; Note the reference KR100813142B1 (“Gim”) discloses a silver-deposited polyester film reflector includes silver, pg. 3, lines 9-15; Accordingly, the silver-deposited polyester film 15 is understood as including silver; therefore, the film 15 is thermally conductive) having a through-hole vertically overlapping an upper surface of the semiconductor chip (FIG. 3 shows 15 has through-hole occupying the same area as the upper side surface of 2 in the vertical direction; “overlap” is not defined in the instant specification; however, “overlap” is defined as “to occupy the same area in part,” see definition 1 by Merriam-Webster available at <https://www.merriam-webster.com/dictionary/overlap>; Accordingly, under a broad reasonable interpretation, the through-hole of 15 vertically overlaps the upper side surface of the chip 2; this interpretation is consistent with the interpretation of “overlap” as used in the instant specification which discloses “The first through-hole 150H1 may overlap the marking region MR of the semiconductor chip 130. The second through-hole 150H2 may overlap the second opening 140H2. That is, on a plane, the marking region MR may be located within the first through-hole 150H1, and the second opening 140H2 may be located within the second through-hole 150H2,” [0037]; Alternatively, the through-hole defined by the uppermost surfaces of 15 overlaps at least a portion of the upper side surface of LED 2 in the vertical direction),
wherein the thermally conductive film is electrically insulated from the wiring pattern by the protective layer (14 is an insulating resin, [0022], rendering it electrically insulating; FIG. 3 shows 15 electrically insulated from 13 by 14).
Nakatsubo does not explicitly disclose:
a thermally conductive resin including a transparent resin covering the upper surface of the semiconductor chip and a heat dissipation filler dispersed in the transparent resin; and
the thermally conductive film covering the thermally conductive resin.
However, in the same field of endeavor, Higashiuchi discloses The transparent sealing resin 40 seals the blue LED 30 and is filled into the internal space 22 formed by the reflector 20, [0045], see FIG. 1.
Higashiuchi discloses The transparent sealing resin 40 may further include an inorganic filling material diffusing light, [0045]. Accordingly, Higashiuchi teaches that the resin may not be completely transparent.
Higashiuchi further discloses As the transparent sealing resin 40, acrylic resin is preferably adopted, from the viewpoint of transparency, [0045].
FIG. 1 shows the resin 40 covering upper side surfaces of the chip 30, and the top surface of the chip 30.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to fill spaces between each LED element 2 and corresponding reflectors 15 with a transparent sealing resin, and to cover the upper side and top surfaces of the LED element 2 with the transparent sealing resin as taught by Higashiuchi in order to seal the LED element 2 and improve protection for the LED element 2.
As a result, the through-hole of 15 would occupy the same area as an upper side surface of 2 covered by the sealing resin in the vertical direction. Alternatively, the through-hole defined by the uppermost surfaces of 15 would overlap at least a portion of an upper side surface of LED 2 covered by the sealing resin in the vertical direction.
In the same field of endeavor, Fujita discloses an optical transmitter 21 in FIG. 14, [0181].
Fujita further discloses The light-emitting element 3 and a driver IC 19 are encapsulated in the mold resin 9 and protected from outside air, [0181].
Fujita further discloses the resin for molding is preferably a resin containing a filler having a low linear expansivity such as silica. Such a resin can be a resin in black color (linear expansivity: 15 to 20 ppm/K, thermal conductivity: about 0.7 W/mK), which is generally used in packaging of ICs that require no optical properties. Such resins are in general use and thus available at a low cost. According to the present invention, the difference between each one of the light-emitting element 3 and bonding wire 33 and the mold resin 9 in linear expansivity can be significantly reduced, so that thermal stress created on the light-emitting element 3 and the bonding wire 33 can be reduced. Since the filler is contained, the thermal conductivity of the resin itself is increased with the result that heat dissipation of the light-emitting element 3 and of the driver IC 19 also can be improved, [0186].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a silica filler in the sealing resin as taught by Fujita in order to improve the thermal conductivity of the resin.
In the same field of endeavor, Park discloses The thermoplastic resin board may further include a thermally conductive filler in a dispersed form, [0013].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the silica filler in the sealing resin in a dispersed form as taught by Park in order to more uniformly improve the thermal conductivity of the sealing resin.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights