DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to communications filed on 02/10/2023. Claims 1-20 are pending and have been examined.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted was filed on 02/28/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claim(s) recite(s) an apparatus, a method, and a medium associated with receiving, generating, determining, generating, receiving, and generating.
The limitations as recited in claim 1 are each a process, under the broadest reasonable interpretation, covering performance of the limitations in the mind or by pen and paper (See Berkheimer v. HP, Inc., 881 F.3d 1360, 1366, 125 USPQ2d 1649 (Fed. Cir. 2018)) but for the recitation of generic computer components. That is, other than reciting “at least one hardware processor” and “executed by the at least one hardware processor”, the limitations are directed to mental steps. For example, the limitation “a graph convolutional message passing network analyzer…to: receive, for a floor plan that is to be generated, a layout graph for which user constraints are encoded as a plurality of room types, wherein the user constraints include spatial connections therebetween; and generate, based on the layout graph, embedding vectors for each room type of the plurality of room types” in the context of the claim encompasses the user making observations and determinations. The limitation “a space layout network analyzer…to: determine, for each room embedding from the layout graph, and based on an analysis of the embedding vectors for each room type of the plurality of room types, bounding boxes and segmentation masks; and generate, by combining the bounding boxes and the segmentation masks, a space layout” in the context of the claim encompasses the user making determinations and evaluations. The limitation “a cascaded alignment layer analyzer…to: receive an input boundary feature map; and generate, based on an analysis of the space layout and the input boundary feature map, the floor plan” in the context of the claim encompasses the user making observations and evaluations. If a claimed limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “mental processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. Accordingly, the claim recites an abstract idea.
This judicial exception is not integrated into a practical application. In particular, the claim recites additional elements. The claim recites “at least one hardware processor” and “executed by the at least one hardware processor”. The elements are recited at a high-level of generality, such that it amounts to no more than mere instructions to apply the exception using a generic computer component (e.g. See MPEP 2106.05(f)). Accordingly, the additional elements do not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements are no more than a generic computer component. Therefore, the claims are not patent eligible.
Claims 12-13 and 17-19 also recite similar corresponding claim language as claim 1, and thus have the same issues. It is noted, with respect to claims 12-13, that the claim recites “by at least one hardware processor”. The elements are recited at a high-level of generality, such that it amounts to no more than mere instructions to apply the exception using a generic computer component (e.g. See MPEP 2106.05(f)). It is noted, with respect to claims 17-19, that the claim further recites “a non-transitory computer readable medium having stored thereon machine readable instructions, the machine readable instructions, when executed by at least one hardware processor, cause the at least one hardware processor” to perform the method. The elements are recited at a high-level of generality, such that it amounts to no more than mere instructions to apply the exception using a generic computer component (e.g. See MPEP 2106.05(f)). Accordingly, the additional elements do not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
Regarding claim 2, the claim does not include any additional elements that integrate the abstract idea into a practical application or are sufficient to amount to significantly more than the judicial exception. For example, the claim merely further describes a floor plan parser to receive and parse a floor plan to determine a room layout, which amounts to mental steps (encompassing a user making observations and evaluations) and “executed by the at least one hardware processor” and “computer-aided design (CAD)” amounts to no more than mere instructions to apply the exception using a generic computer component (e.g. See MPEP 2106.05(f)) and/or generally linking the use of the judicial exception to a particular technological environment or field of use (e.g. see MPEP 2106.05(h)). This similarly applies to claim 14.
Regarding claim 3, the claim does not include any additional elements that are sufficient to amount to significantly more than the judicial exception. For example, the claim merely further describes extracting, upsampling, and determining, which amounts to mental steps (encompassing a user making observations, calculations, and evaluations) and “by an encoder”, “by a decoder”, and “by an attention component”, at most (note: a user can encode, decode and have attention), amounts to generally linking the use of the judicial exception to a particular technological environment or field of use (e.g. see MPEP 2106.05(h)). This similarly applies to claim 15.
Regarding claim 4, the claim does not include any additional elements that integrate the abstract idea into a practical application or are sufficient to amount to significantly more than the judicial exception. For example, the claim merely further describes determining by combining, which amounts to mental steps (encompassing a user making calculations and evaluations) and does not include any additional elements other than noted above.
Regarding claim 5, the claim does not include any additional elements that integrate the abstract idea into a practical application or are sufficient to amount to significantly more than the judicial exception. For example, the claim merely further describes determining by multiplying, which amounts to mental steps (encompassing a user making calculations and evaluations) and does not include any additional elements other than noted above. This similarly applies to claim 16.
Regarding claim 6, the claim does not include any additional elements that integrate the abstract idea into a practical application or are sufficient to amount to significantly more than the judicial exception. For example, the claim merely further describes a layout graph generator to generate, which amounts to mental steps (encompassing a user making evaluations) and does not include any additional elements other than noted above.
Regarding claim 7, the claim does not include any additional elements that integrate the abstract idea into a practical application or are sufficient to amount to significantly more than the judicial exception. For example, the claim merely further describes a loss analyze to analyze loss, which amounts to mental steps (encompassing a user making calculations) and does not include any additional elements other than noted above.
Regarding claim 8, the claim does not include any additional elements that integrate the abstract idea into a practical application or are sufficient to amount to significantly more than the judicial exception. For example, the claim merely further describes a similar floor plan identifier to identify and generate, which amounts to mental steps (encompassing a user making calculations and evaluations) and does not include any additional elements other than noted above.
Regarding claim 9, the claim does not include any additional elements that integrate the abstract idea into a practical application or are sufficient to amount to significantly more than the judicial exception. For example, the claim merely further describes generating vectors and utilizing layer to generate vectors, which amounts to mental steps (encompassing a user making evaluations) and does not include any additional elements other than noted above.
Regarding claim 10, the claim does not include any additional elements that integrate the abstract idea into a practical application or are sufficient to amount to significantly more than the judicial exception. For example, the claim merely further describes passing vectors to predict (encompassing a user making evaluations) and “a box regression network”, at most (note: a user can perform regression, which is math), amounts to generally linking the use of the judicial exception to a particular technological environment or field of use (e.g. see MPEP 2106.05(h))
Regarding claim 11, the claim does not include any additional elements that integrate the abstract idea into a practical application or are sufficient to amount to significantly more than the judicial exception. For example, the claim merely further describes multiplying, using interpolation, and generating, which amounts to mental steps (encompassing a user making calculations and evaluations) and does not include any additional elements other than noted above. This similarly applies to claim 20.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 6-7, 9-10, 12-14, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Nauata et al. (“House-GAN++: Generative Adversarial Layout Refinement Network towards Intelligent Computational Agent for Professional Architects” in Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, Year 2021, pp. 13632-13641 as cited in IDS dated 02/28/2023) in view of Hu et al. ("Graph2plan: Learning floorplan generation from layout graphs," ACM Transactions on Graphics (TOG), vol. 39, no. 4, Article 1, Publication date July 2020, 14 pages as cited in IDS dated 02/28/2023).
As per independent claim 1, Nauata stylization-based floor plan generation apparatus comprising:
at least one hardware processor (e.g. in page 13636, “a workstation with dual Xeon CPUs and dual NVIDIA Titan RTX GPU”);
a graph convolutional message passing network analyzer, executed by the at least one hardware processor (e.g. in page 13634, “Following House-GAN [24], our network backbone is a convolutional message passing network (Conv-MPN [32]), whose relational graph structure is defined by the bubble diagram”), to: receive, for a floor plan that is to be generated, a layout graph for which user constraints are encoded as a plurality of room types, wherein the user constraints include spatial connections therebetween (e.g. in page 13634, “architects incorporate constraints from clients into a sketch called a bubble-diagram, then convert it into a floorplan through design explorations and iterations… graph where a node encodes a room with its room type… an edge encodes a functional connection (“interior door” or “front door”)”); and generate, based on the layout graph, embedding vectors for each room type of the plurality of room types (e.g. in pages 13634-13635, “House-GAN has a 10-d one-hot vector, which encodes a room type and initializes a node feature vector. In our work, doors have two types, and we extend the one-hot vector to 12-d over the mix of 10 room types and 2 door types… initializes each node with a noise vector and a room-type, which is transformed into a 8 × 8 × 16 feature volume”);
a network analyzer, executed by the at least one hardware processor, to determine, for each room embedding from the layout graph, and based on an analysis of the embedding vectors for each room type of the plurality of room types, bounding boxes and segmentation masks and generate, by combining the bounding boxes and the segmentation masks, the floor plan (e.g. in pages 13634-13636, “initializes each node with a noise vector and a room-type, which is transformed into a 8 × 8 × 16 feature volume… provides the segmentation mask… feature volumes for a component r (i.e. either a room or a door) and Pool gs sum-pooling over feature volumes… a room is a neighbor of its connected rooms and the doors in-between…where the final segmentation mask is produced… generated room/edge masks… small doors need to be placed precisely at the room boundaries” and figure 3 showing combining bounding boxes and segmentation masks),
but does not specifically teach a space layout network analyzer, the floor plan being based on a space layout and a cascaded alignment layer analyzer, executed by the at least one hardware processor, to receive an input boundary feature map and generate, based on an analysis of the space layout and the input boundary feature map, the floor plan.
However, Hu teaches a floor plan being based on a space layout from a space layout network analyzer and a cascaded alignment layer analyzer to receive an input boundary feature map and generate, based on an analysis of the space layout and the input boundary feature map, the floor plan (e.g. in pages 1 and 3, “Graph2Plan, which converts a layout graph, along with a building boundary, into a floor plan that fulfills both the layout and boundary constraints” and figure 2d showing space layout network analysis prior to the final floorplan in figure 2e). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Nauata to include the teachings of Hu because one of ordinary skill in the art would have recognized the benefit of further accommodating relevant constraints.
As per claim 2, the rejection of claim 1 is incorporated and the combination further teaches a computer-aided design (CAD) floor plan parser, executed by the at least one hardware processor, to receive a CAD floor plan and parse the CAD floor plan to determine a room layout for the CAD floor plan (e.g. Nauata, in pages 13632-13634, “parsed the RPLAN dataset [30] to prepare 60k house layouts with the corresponding bubble-diagrams… where a node encodes a room with its room type (See Fig. 2)… an edge encoded spatial adjacency of two rooms”).
As per claim 6, the rejection of claim 1 is incorporated and the combination further teaches a layout graph generator, executed by the at least one hardware processor, to generate, from the room layout, the layout graph (e.g. Nauata, in pages 13632-13634, “parsed the RPLAN dataset [30] to prepare 60k house layouts with the corresponding bubble-diagrams… as a graph where a node encodes a room with its room type (See Fig. 2)… an edge encoded spatial adjacency of two rooms”).
As per claim 7, the rejection of claim 1 is incorporated and the combination further teaches a loss analyzer, executed by the at least one hardware processor, to analyze, for the generated floor plan, a cross-entropy loss (e.g. Hu, in page 6, “the image loss that is simply defined as the cross entropy of the generated floorplan image and the ground truth floorplan image”).
As per claim 9, the rejection of claim 1 is incorporated and the combination further teaches wherein the graph convolutional message passing network analyzer is executed by the at least one hardware processor to generate, based on the layout graph, the embedding vectors for each room type of the plurality of room types by utilizing a plurality of embedding layers to embed room types and relationships between rooms to generate vectors of a specified dimension (e.g. Nauata, in pages 13634-13635, “Following House-GAN [24], our network backbone is a convolutional message passing network (Conv-MPN [32]), whose relational graph structure is defined by the bubble diagram… we extend the one-hot vector to 12-d over the mix of 10 room types and 2 door types… initializes each node with a noise vector and a room-type, which is transformed into a 8 × 8 × 16 feature volume”)
As per claim 10, the rejection of claim 1 is incorporated and the combination further teaches wherein the space layout network analyzer is executed by the at least one hardware processor to determine, for each room embedding from the layout graph, and based on the analysis of the embedding vectors for each room type of the plurality of room types, the bounding boxes and the segmentation masks by: passing the embedding vectors to a box regression network to predict the bounding boxes (e.g. Hu, in page 6, “masks capture the pixels that are inside the boundary … the network predicts… initial boxes {B0i}, and refined boxes… loss function…is the regression loss”; Nauata, in pages 13633-13636, “an auto-regressive model is trained by masking… This paper takes the idea of masking and adversarial training to the task of 2D layout generation… initializes each node with a noise vector and a room-type, which is transformed into a 8 × 8 × 16 feature volume… provides the segmentation mask… feature volumes for a component r (i.e. either a room or a door) and Pool gs sum-pooling over feature volumes… a room is a neighbor of its connected rooms and the doors in-between…where the final segmentation mask is produced… generated room/edge masks… small doors need to be placed precisely at the room boundaries” and figure 3).
Claims 12-14 are the method claims corresponding to apparatus claims 1-2 and are rejected under the same reasons set forth.
Claims 17-19 are the medium claims corresponding to apparatus claim 1 and are rejected under the same reasons set forth and the combination further teaches a non-transitory computer readable medium having stored thereon machine readable instructions, the machine readable instructions, when executed by at least one hardware processor (e.g. Nauata, in page 13636, “a workstation with dual Xeon CPUs and dual NVIDIA Titan RTX GPU”; note: this CPU/GPU includes registers, cache, etc., i.e. non-transitory computer readable medium, to execute instructions).
Claims 3-5, 11, 15-16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Nauata et al. (“House-GAN++: Generative Adversarial Layout Refinement Network towards Intelligent Computational Agent for Professional Architects” in Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, Year 2021, pp. 13632-13641 as cited in IDS dated 02/28/2023) in view of Hu et al. ("Graph2plan: Learning floorplan generation from layout graphs," ACM Transactions on Graphics (TOG), vol. 39, no. 4, Article 1, Publication date July 2020, 14 pages as cited in IDS dated 02/28/2023) and further in view of Zeng et al. (“Deep Floor Plan Recognition Using a Multi-Task Network with Room-Boundary-Guided Attention”, IEEE/CVF International Conference on Computer Vision, 2019, pages 9095-9103).
As per claim 3, the rejection of claim 2 is incorporated, but the combination does not specifically teach extracting, by an encoder, a plurality of features from the CAD floor plan; upsampling, by a decoder, the extracted plurality of features to generate a segmentation image; and determining, by an attention component and from the segmentation image, semantic information and target features to generate the room layout for the CAD floor plan. However, Zeng teaches extracting, by an encoder, a plurality of features from a floor plan (e.g. in page 9097, “We have a VGG encoder to extract features from the input floor plan image”); upsampling, by a decoder, the extracted plurality of features to generate a segmentation image (e.g. in page 9098 and figure 4 showing “up-sample…by VGG decoder”); and determining, by an attention component and from the segmentation image, semantic information and target features to generate the room layout for the floor plan (e.g. in pages 9095 and 9098-9099, “automatically processing floor plans and recognizing layout semantics… spatial contextual module with the room-boundary-guided attention mechanism, which leverages the room-boundary features to learn the attention weights for room-type prediction… the output may...find connected regions bounded by the predicted room-boundary pixels to locate room regions”). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of the combination to include the teachings of Zeng because one of ordinary skill in the art would have recognized the benefit of facilitating recognizing of room layouts.
As per claim 4, the rejection of claim 3 is incorporated and the combination further teaches wherein the attention component determines the semantic information and the target features by combining low-level feature maps with high-level feature maps (e.g. Zeng, in page 9098 and figure 4 showing combining low level feature maps with high level room type features).
As per claim 5, the rejection of claim 4 is incorporated and the combination further teaches wherein the attention component determines the semantic information and the target features by multiplying the low-level feature maps by an attention vector (e.g. Zeng, in page 9098, “while “X” and “+” denote element-wise multiplication and addition” and figure 4 showing attention weights vector “X” low level feature maps).
As per claim 11, the rejection of claim 1 is incorporated and the combination further teaches wherein the space layout network analyzer is executed by the at least one hardware processor to generate, by combining the bounding boxes and the segmentation masks, the space layout by generate a plurality of masked embedding shapes, modify the masked embedding shapes to a position of associated bounding boxes to generate room layouts, and generating, based on a summation of the room layouts, the space layout (e.g. Nauata, in pages 13634-13636, “provides the segmentation mask… feature volumes for a component r (i.e. either a room or a door) and Pool gs sum-pooling over feature volumes… a room is a neighbor of its connected rooms and the doors in-between…where the final segmentation mask is produced… generated room/edge masks… small doors need to be placed precisely at the room boundaries” and figure 3 showing combining bounding boxes and segmentation masks), but does not specifically teach multiplying an embedding vector for each room type by an associated mask to generate a plurality of masked embedding shapes and utilizing bi-linear interpolation to modify. However, Zeng teaches multiplying an embedding vector for each room type by an associated mask to generate a plurality of masked embedding shapes and utilizing bi-linear interpolation to modify (e.g. in pages 9097-9098, ““X”…denote element-wise multiplication… we apply the first attention to the 2D feature map…by direction-aware kernels (horizontal, vertical… convolutions with the direction-aware kernels”, i.e. bi-directional interpolation, and figure 8 showing room-type embedding vector “X” room-boundary, i.e. mask). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of the combination to include the teachings of Zeng because one of ordinary skill in the art would have recognized the benefit of facilitating recognizing of room layouts.
Claims 15-16 are the method claims corresponding to apparatus claims 3-5 and are rejected under the same reasons set forth.
Claim 20 is the medium claim corresponding to apparatus claim 11 and is rejected under the same reasons set forth.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Nauata et al. (“House-GAN++: Generative Adversarial Layout Refinement Network towards Intelligent Computational Agent for Professional Architects” in Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, Year 2021, pp. 13632-13641 as cited in IDS dated 02/28/2023) in view of Hu et al. ("Graph2plan: Learning floorplan generation from layout graphs," ACM Transactions on Graphics (TOG), vol. 39, no. 4, Article 1, Publication date July 2020, 14 pages as cited in IDS dated 02/28/2023) and further in view of Yin et al. (US 20220092227 A1).
As per claim 8, the rejection of claim 1 is incorporated, but the combination does not specifically teach a similar floor plan identifier, executed by the at least one hardware processor, to: determine node similarity between the generated floor plan and a plurality of existing floor plans; generate, based on the determined node similarity between the generated floor plan and the plurality of existing floor plans, similarity scores; identify, from the generated similarity scores, a highest similarity score; and identify, based on the highest similarity score, a most similar existing floor plan. However, Yin teaches a similar floor plan identifier to determine node similarity between a generated floor plan and a plurality of existing floor plans (e.g. in abstract and paragraphs 12 and 96-97, “identifying building floor plans… compare the indicated initial building(s) to the other buildings… using their adjacency graphs”); generate, based on the determined node similarity between the generated floor plan and the plurality of existing floor plans, similarity scores (e.g. in paragraphs 96-97, “compare the indicated initial building(s) to the other buildings… using their adjacency graphs [to determine] a degree of similarity between the two buildings”); identify, from the generated similarity scores, a highest similarity score and identify, based on the highest similarity score, a most similar existing floor plan (e.g. in paragraph 97, “rank orders the multiple other buildings using the similarity degree values… selects one or more best matches to use as the identified target buildings”, i.e. most similar). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of the combination to include the teachings of Yin because one of ordinary skill in the art would have recognized the benefit of facilitating identification of other floor plans likely to satisfy constraints.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
For example,
Alimo et al. (US 20230035601 A1) teaches “each room is assumed to be a node and shared walls are assumed as edges” (e.g. in paragraph 114).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM WONG whose telephone number is (571)270-1399. The examiner can normally be reached Monday-Friday 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TAMARA KYLE can be reached at (571)272-4241. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/W.W/Examiner, Art Unit 2144 06/27/2026
/SHOURJO DASGUPTA/Primary Examiner, Art Unit 2144
Prosecution Insights