DETAILED ACTION
Claims 1-31 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/04/2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-4, 7-12, 14-15, 18, 26, 29, and 30-31 is/are rejected under 35 U.S.C. 102(a)(2) as being aniticpated by Durant et al. (US PG Pub No. 2013/0305009 A1).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1, Durant teaches a system comprising:
at least one first processor ([0049], “PPUs 202”) associated with a first portion of pooled volatile memory ([0051]), the pooled volatile memory comprising a second portion that, prior to allocation, is not allocated to and is not mapped to the at least one first processor ([0049], wherein “certain coprocessor devices, such as the PPUs 202, do not have the ability to allocate memory while threads on the PPUs 202 are executing code for an application program. Consequently, all memory to be used by the threads executing on the PPUs 202 must be allocated by the host processor, CPU 102 before execution begins on any of the PPUs 202”); and
a second processor to allocate at least a third portion of the second portion of the pooled volatile memory to the at least one first processor ([0052], wherein “when the pre-allocated memory runs out, a runtime handling the virtual memory structure implementation migrates some of the data stored in the pre-allocated memory to memory that is not accessible to the PPU(s) 202 that is dynamically allocated by the CPU 102 and accessible to the CPU 102, but not accessible to the PPU(s) 202”), and to update a memory map to map the at least one first processor to the third portion ([0056] wherein “The CPU 102 supports memory paging or swapping and is able to dynamically allocate memory and is able to allocate pageable or swappable memory in either the system memory 104 or the PP memory 204” and wherein memory paging is an implementation of a memory map), wherein the second portion and the third portion of the pooled volatile memory are not allocated to the second processor ([0054], wherein “the host processor, CPU 102 is able to allocate memory that is accessible to both the CPU 102 and the coprocessor, where the coprocessor is one or more PPUs 202. Memory that is accessible to both the CPU 102 and the coprocessor, such as the memory accessible to coprocessor 410 may be pinned system memory, i.e., a portion of the system memory 104. The system memory 104 may be directly coupled to the CPU 102 or coupled to the CPU 102 through the memory bridge 105. The system memory 104 is indirectly coupled to the parallel processing subsystem 112 through the communication path 113”).
Regarding claim 3, Durant teaches wherein the at least one first processor is to request access to data stored in the pooled volatile memory, and the second processor is to use the memory map to locate the data ([0056]).
Regarding claim 4, Durant teaches wherein the second processor is to allocate the third portion of the pooled volatile memory to the at least one first processor in response to a request to store data originating at least in part from an application being performed by the at least one first processor ([0052]).
Regarding claim 7, Durant teaches wherein further comprising: a device associated with the second portion of the pooled volatile memory and not including the at least one first processor (Fig 2, wherein multiple servers exist to utilize the pooled volatile memory pool).
Regarding claim 8, Durant teaches wherein further comprising: a third processor associated with the second portion of the pooled volatile memory (Fig 2, wherein multiple subsystems exist to utilize the pooled volatile memory pool).
Regarding claim 9, Durant teaches wherein the second processor is to manage input and output (“IO”) to and from the at least one first processor ([0049])
Regarding claim 10, Durant teaches wherein the second portion comprises volatile memory that is remote with respect to the at least one first processor ([0054-55]).
Regarding claim 11, Durant teaches wherein the first portion is to be utilized by at least one tenant, and the second processor is to allocate a fourth portion of the second portion of the pooled volatile memory to one or more tenants (Fig 2, wherein multiple subsystems exist to utilize the pooled volatile memory pool).
Regarding claims 12, 14-15 and 18, they are the processor claims of claims 1, 3-4 and 9 above. Therefore, they are rejected for the same reasons as claims 1, 3-4 and 9 above.
Regarding claim 26, Durant teaches a method comprising:
receiving, by a receiving processor, a request from a requesting processor to access data stored in at least a portion of aggregated volatile memory that is mapped to the requesting processor and is not directly accessible by the requesting processor or the receiving processor ([0052], wherein “when the pre-allocated memory runs out, a runtime handling the virtual memory structure implementation migrates some of the data stored in the pre-allocated memory to memory that is not accessible to the PPU(s) 202 that is dynamically allocated by the CPU 102 and accessible to the CPU 102, but not accessible to the PPU(s) 202”), wherein the portion of the aggregated volatile memory is not allocated to the receiving processor ([0049], wherein “certain coprocessor devices, such as the PPUs 202, do not have the ability to allocate memory while threads on the PPUs 202 are executing code for an application program. Consequently, all memory to be used by the threads executing on the PPUs 202 must be allocated by the host processor, CPU 102 before execution begins on any of the PPUs 202”);
using, by the receiving processor, a memory map of the aggregated volatile memory maintained by the receiving processor to locate the requested data ([0056] wherein “The CPU 102 supports memory paging or swapping and is able to dynamically allocate memory and is able to allocate pageable or swappable memory in either the system memory 104 or the PP memory 204”); and
causing, by the receiving processor, the data to be transferred from the portion of the aggregated volatile memory to the requesting processor ([0054], wherein “the host processor, CPU 102 is able to allocate memory that is accessible to both the CPU 102 and the coprocessor, where the coprocessor is one or more PPUs 202. Memory that is accessible to both the CPU 102 and the coprocessor, such as the memory accessible to coprocessor 410 may be pinned system memory, i.e., a portion of the system memory 104. The system memory 104 may be directly coupled to the CPU 102 or coupled to the CPU 102 through the memory bridge 105. The system memory 104 is indirectly coupled to the parallel processing subsystem 112 through the communication path 113”).
Regarding claim 29, Durant teaches wherein the receiving processor and the requesting processor are components of a distributed computing environment comprising a data center or a multi-cloud environment, and the receiving processor receives the request from the requesting processor through the distributed computing environment (Fig 2).
Regarding claim 30, Durant teaches wherein the at least one first processor is to use the memory map to access the third portion ([0056] wherein “The CPU 102 supports memory paging or swapping and is able to dynamically allocate memory and is able to allocate pageable or swappable memory in either the system memory 104 or the PP memory 204”, wherein memory paging is an implementation of a memory map).
Regarding claim 31, Durant teaches wherein the memory map comprises a virtual address used by the at least one first processor mapped to at least one physical address of the third portion ([0039]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 13, and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Durant et al. (US PG Pub No. 2013/0305009 A1) in view of Sindhu et al. (US PG Pub No. 2019/0012278 A1).
Regarding claim 2, Durant does not teach further comprising: a data processing unit (“DPU”) comprising the second processor.
Sindhu teaches a data processing unit (“DPU”) comprising the second processor ([0075]; [0089]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a DPU for implementing the allocation of memory. One would be motivated by the desire to support use a DPU to support specialized network-on-chip (NoC) fabrics for inter-processor communication as taught by Sindhu ([0075]).
Regarding claim 27, Sindhu teaches wherein the receiving processor is a data processing unit (“DPU”) ([0075]; [0089]).
Regarding claim 13, it is the processor claim of claim 2 above. Therefore, it is rejected for the same reasons as claim 2 above.
Claim(s) 5-6, 16-17, 19, 23-25, and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Durant et al. (US PG Pub No. 2013/0305009 A1) in view of Zhang et al. (US PG Pub No. 2022/0263913 A1).
Regarding claim 5, Durant does not teach further comprising: a subsystem comprising the second processor and a switch to transfer data from the third portion of the pooled volatile memory to the at least one first processor or a fourth portion of the pooled volatile memory.
Zhang teaches coupling multiple host systems together using a network switch where requests and responses are communicated with the data center cluster using the memory pool (abstract; [0134]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to utilize a switch to transfer data from the third portion of the pooled volatile memory to the first processor. One would be motivated by the desire to utilize commonly used networking components to enable multiple hosts to communicate with each other.
Regarding claim 6, Zhang teaches wherein the switch is a Compute Express Link (“CXL”) switch (abstract; [0134]).
Regarding claims 16-17, they are the processor claims of claims 5-6 above. Therefore, they are rejected for the same reasons as claims 5-6 above.
Regarding claim 19, Durant teaches a method comprising:
receiving, using a first processor, a request from a second processor to store data in at least a portion of aggregated volatile memory comprising a first portion ([0052], wherein “when the pre-allocated memory runs out, a runtime handling the virtual memory structure implementation migrates some of the data stored in the pre-allocated memory to memory that is not accessible to the PPU(s) 202 that is dynamically allocated by the CPU 102 and accessible to the CPU 102, but not accessible to the PPU(s) 202”) that, prior to allocation, is not allocated to and is not mapped to the second processor not directly accessible by the second processor ([0049], wherein “certain coprocessor devices, such as the PPUs 202, do not have the ability to allocate memory while threads on the PPUs 202 are executing code for an application program. Consequently, all memory to be used by the threads executing on the PPUs 202 must be allocated by the host processor, CPU 102 before execution begins on any of the PPUs 202”);
allocating, using the first processor, at least a second portion of the first portion of the aggregated volatile memory to the second processor in response to receiving the request, and updating a memory map to map the second processor to the second portion ([0056] wherein “The CPU 102 supports memory paging or swapping and is able to dynamically allocate memory and is able to allocate pageable or swappable memory in either the system memory 104 or the PP memory 204”), wherein the first portion and the second portion of the aggregated volatile memory are not allocated to the first processor wherein the second portion of the aggregated volatile memory is not associated with the first processor([0054], wherein “the host processor, CPU 102 is able to allocate memory that is accessible to both the CPU 102 and the coprocessor, where the coprocessor is one or more PPUs 202. Memory that is accessible to both the CPU 102 and the coprocessor, such as the memory accessible to coprocessor 410 may be pinned system memory, i.e., a portion of the system memory 104. The system memory 104 may be directly coupled to the CPU 102 or coupled to the CPU 102 through the memory bridge 105. The system memory 104 is indirectly coupled to the parallel processing subsystem 112 through the communication path 113”).
Durant does not teach causing a subsystem, using the first processor, comprising one or more circuits, and a switch to transfer the data from the second processor to the second portion of the aggregated volatile memory.
Zhang teaches coupling multiple host systems together using a network switch where requests and responses are communicated with the data center cluster using the memory pool (abstract; [0134]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to utilize a switch to transfer data from the third portion of the pooled volatile memory to the first processor. One would be motivated by the desire to utilize commonly used networking components to enable multiple hosts to communicate with each other.
Regarding claim 23, Durant teaches wherein updating the memory map comprises recording the allocation of the second portion of the aggregate volatile memory to the second processor ([0056]).
Regarding claim 24, Zhang teaches wherein the switch is a Compute Express Link (“CXL”) switch (abstract; [0134]).
Regarding claim 25, Durant teaches allocating at least a third portion of the aggregated volatile memory to different processor, wherein, prior to allocation, the third portion is not allocated to and is not mapped to the different third processor (Fig 2, wherein multiple subsystems exist to utilize the pooled volatile memory pool).
Regarding claim 28, Durant and Zhang do not teach wherein the receiving processor causes a Compute Express Link (“CXL”) switch to transfer the data.
Zhang teaches coupling multiple host systems together using a network switch, such as a Compute Express Link (“CXL”) switch, where requests and responses are communicated with the data center cluster using the memory pool (abstract; [0134]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to utilize a switch to transfer data from the third portion of the pooled volatile memory to the first processor. One would be motivated by the desire to utilize commonly used networking components to enable multiple hosts to communicate with each other.
Claim(s) 20-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Durant et al. (US PG Pub No. 2013/0305009 A1) in view of Zhang et al. (US PG Pub No. 2022/0263913 A1), further in view of Sindhu et al. (US PG Pub No. 2019/0012278 A1).
Regarding claim 20, Durant and Zhang do not teach wherein the receiving, allocating, and causing are performed by a data processing unit.
Sindhu teaches a data processing unit (“DPU”) comprising the second processor ([0075]; [0089]). It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a DPU for implementing the allocation of memory. One would be motivated by the desire to support use a DPU to support specialized network-on-chip (NoC) fabrics for inter-processor communication as taught by Sindhu ([0075]).
Regarding claim 21, Sindhu teaches the DPU comprises the subsystem ([0075]; [0089]).
Regarding claim 22, the combination of Durant and Sindhu teaches wherein the DPU receives the request from the requesting processor through a data center or a multi-cloud environment (Durant Fig 2).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-31 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/Eric C Wai/Primary Examiner, Art Unit 2195
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