Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
The information disclosure statements filed 2/11/23 have been considered.
Oath/Declaration
Oath/Declaration filed on 2/11/23 has been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The limitations “twenty first metal bumps”, “twenty second metal bumps”, “twenty third metal bumps” and “twenty fourth metal bumps” are not support in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1-2, 4-9, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over TSAI et al. (U.S. Patent Publication No. 2020/0343198).
Referring to figures 1-6, TSAI et al. teaches a method for fabricating an interconnection bridge comprising:
providing a silicon wafer (102, see paragraph# 17) with a plurality of first scribe lines (13, see figure extending in a first direction, a plurality of second scribe lines extending in a second direction perpendicular to the first direction and a plurality of portions each between neighboring two of the plurality of first scribe lines and between neighboring two of the plurality of second scribe lines (see figures 2a-3a), wherein each of the plurality of portions comprises plurality first metal bumps (134/136/138) at a first side of a top surface of said each of the plurality of portions and plurality second metal bumps (134/136/138) at a second side, opposite to the first side, of the top surface of said each of the plurality of portions, wherein each of the plurality first and second metal bumps (134/136/138) comprises a first copper layer (see paragraph# 21, 38) protruding from the top surface of said each of the plurality of portions, wherein the plurality first metal bumps are arranged in a first line in the first direction and the plurality second metal bumps are arranged in a second line in the first direction, wherein said each of the plurality of portions comprises twenty first metal interconnects (133/137) each coupling one of the plurality first metal bumps to one of the plurality second metal bumps(134/136/138), wherein said one of the plurality first metal bumps and said one of the plurality second metal bumps are aligned in a third line in the second direction (see figures 2-3); and
cutting the silicon wafer along the plurality of first and second scribe lines to form one of plurality of portions as the interconnection bridge in a separated unit (see paragraph# 61), wherein the interconnection bridge (106/112/114) is configured to bond with a plurality of semiconductor integrated-circuit (IC) chips for coupling the plurality of semiconductor integrated-circuit (IC) chips (see figures 1-3).
However, the reference doesnot clearly teach the specific number of metal bumps.
It would be obvious to one ordinary skill in the art to form the specific number of metal bumps with the same process as using in the first oxide layer to form a thicker oxide
layer since it is well-known in the art to repeat the same process for multiple effect. See St.
Regis paper, Co. V. Bemis Co. Inc. 193 USPQ 8, 11 (7th circuit 1977).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a specific number of metal bumps in TSAI et al. because it is known in the semiconductor art to improve electrical connectivity.
Regarding to claim 2, wherein said each of the plurality of portions comprises plurality third metal bumps (134/136/138) arranged at the first side and in a fourth line in the first direction and between the first and second lines and twenty fourth metal bumps (134/136/138) arranged at the second side and in a fifth line in the first direction and between the second and fourth lines, wherein said each of the plurality of portions further comprises plurality second metal interconnects each coupling one of the plurality third metal bumps to one of the plurality fourth metal bumps, wherein said one of the plurality third metal bumps and said one of the plurality fourth metal bumps are aligned in the third line with said one of the plurality first metal bumps and said one of the plurality second metal bumps (see figures 2-3).
Regarding to claim 4, the interconnection bridge has no transistor therein (see figures 2-3).
Regarding to claim 5, the interconnection bridge comprises a passive device therein (110, rdl, see paragraph# 19).
Regarding to claim 6, wherein said each of the twenty first and second metal bumps comprises a tin-containing solder over the first copper layer thereof (see paragraph# 19).
Regarding to claim 8, wherein said each of the plurality first and second metal bumps comprises an adhesion layer at a bottom of the first copper layer thereof but not at a sidewall of the first copper layer thereof (see paragraphs# 21, 38).
Regarding to claim 9, the silicon wafer comprises a silicon substrate (see paragraph# 17) and an interconnection scheme (110) on the silicon substrate, wherein the interconnection scheme comprises a first interconnection metal layer (110) over the silicon substrate, a second interconnection metal layer (110) over the first interconnection metal layer, a first insulating dielectric layer (108) between the first and second interconnection metal layers and a second insulating dielectric layer (108) on the second interconnection metal layer, wherein the first interconnection metal layer comprises a second copper layer (see paragraphs# 19, 21) and a first adhesion layer (103) at a bottom and sidewall of the second copper layer, wherein the plurality first metal interconnects are provided by the interconnection scheme (see figures 2, 3).
Regarding to claim 11, the silicon wafer comprises a third scribe line extending in the second direction and between neighboring two of the plurality of second scribe lines, wherein while said cutting the silicon wafer along the plurality of first and second scribe lines, the silicon wafer is not cut along the third scribe line, wherein the third scribe line is reserved in the interconnection bridge (see figures 2a-2c).
Claim 1-9, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (U.S. Patent Publication No. 2020/0161242).
Referring to figures 1-31, Lin et al. teaches a method for fabricating an interconnection bridge comprising:
providing a silicon wafer (2, see paragraph# 17) with a plurality of first scribe lines (2023) extending in a first direction, a plurality of second scribe lines extending in a second direction perpendicular to the first direction and a plurality of portions each between neighboring two of the plurality of first scribe lines and between neighboring two of the plurality of second scribe lines (see figures 8), wherein each of the plurality of portions comprises plurality first metal bumps (570) at a first side of a top surface of said each of the plurality of portions and plurality second metal bumps (34) at a second side, opposite to the first side, of the top surface of said each of the plurality of portions, wherein each of the plurality first and second metal bumps comprises a first copper layer (32, see paragraph# 376) protruding from the top surface of said each of the plurality of portions, wherein the plurality first metal bumps are arranged in a first line in the first direction and the plurality second metal bumps are arranged in a second line in the first direction, wherein said each of the plurality of portions comprises plurality first metal interconnects (20) each coupling one of the plurality first metal bumps(570) to one of the plurality second metal bumps(34), wherein said one of the plurality first metal bumps and said one of the plurality second metal bumps are aligned in a third line in the second direction (see figures 14-15); and
cutting the silicon wafer along the plurality of first and second scribe lines to form one of plurality of portions as the interconnection bridge in a separated unit (684, see figure 31), wherein the interconnection bridge (684) is configured to bond with a plurality of semiconductor integrated-circuit (IC) chips for coupling the plurality of semiconductor integrated-circuit (IC) chips (see figures 14, 31).
However, the reference does not clearly teach the specific number of metal bumps.
It would be obvious to one ordinary skill in the art to form the specific number of metal bumps with the same process as using in the first oxide layer to form a thicker oxide
layer since it is well-known in the art to repeat the same process for multiple effect. See St.
Regis paper, Co. V. Bemis Co. Inc. 193 USPQ 8, 11 (7th circuit 1977).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a specific number of metal bumps in TSAI et al. because it is known in the semiconductor art to improve electrical connectivity.
Regarding to claim 2, wherein said each of the plurality of portions comprises plurality third metal bumps (34) arranged at the first side and in a fourth line in the first direction and between the first and second lines and twenty fourth metal bumps (570) arranged at the second side and in a fifth line in the first direction and between the second and fourth lines, wherein said each of the plurality of portions further comprises plurality second metal interconnects each coupling one of the plurality third metal bumps to one of the plurality fourth metal bumps, wherein said one of the plurality third metal bumps and said one of the plurality fourth metal bumps are aligned in the third line with said one of the plurality first metal bumps and said one of the plurality second metal bumps (see figures 14-15).
Regarding to claim 3, wherein a space between said one of the plurality third metal bumps and said one of the plurality fourth metal bumps is greater than a space between said one of the plurality first metal bumps and said one of the plurality third metal bumps and greater than a space between said one of the plurality second metal bumps and said one of the plurality fourth metal bumps (see figure 14c) .
Regarding to claim 4, the interconnection bridge has no transistor therein (see figures 2-31).
Regarding to claim 5, the interconnection bridge comprises a passive device therein (see paragraph# 363, 542).
Regarding to claim 6, wherein said each of the plurality first and second metal bumps comprises a tin-containing solder over the first copper layer thereof (see paragraph# 368-369).
Regarding to claim 7, the first copper layer (32) has a thickness between 1 and 60 micrometers (see paragraph# 376).
Regarding to claim 8, wherein said each of the plurality first and second metal bumps comprises an adhesion layer (26a/b) at a bottom of the first copper layer thereof but not at a sidewall of the first copper layer thereof (see paragraphs# 368).
Regarding to claim 9, the silicon wafer comprises a silicon substrate (see paragraph# 362) and an interconnection scheme (20/29) on the silicon substrate, wherein the interconnection scheme comprises a first interconnection metal layer (20) over the silicon substrate, a second interconnection metal layer (29) over the first interconnection metal layer, a first insulating dielectric layer (12) between the first and second interconnection metal layers and a second insulating dielectric layer (42) on the second interconnection metal layer, wherein the first interconnection metal layer comprises a second copper layer (see paragraphs# 364) and a first adhesion layer (18) at a bottom and sidewall of the second copper layer, wherein the plurality first metal interconnects are provided by the interconnection scheme (see figures 14, 15).
Regarding to claim 11, the silicon wafer comprises a third scribe line extending in the second direction and between neighboring two of the plurality of second scribe lines, wherein while said cutting the silicon wafer along the plurality of first and second scribe lines, the silicon wafer is not cut along the third scribe line, wherein the third scribe line is reserved in the interconnection bridge (see paragraph# 271, figures 8).
Allowable Subject Matter
Claim 10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 12-21 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
None of the prior art teaches or suggests the second interconnection metal layer comprises a bulk metal layer and a second adhesion layer at a bottom of the bulk metal layer thereof but not at a sidewall, over the first insulating dielectric layer, of the bulk metal layer thereof, wherein the second adhesion layer is on the first insulating dielectric layer, wherein the second insulating dielectric layer contacts the sidewall of the bulk metal layer and is over a top of the bulk metal layer, wherein the second interconnection metal layer comprises a plurality of metal pads each at a bottom of one of a plurality of openings in the second insulating dielectric layer, wherein each of the plurality first and second metal bumps is on a metal pad of the plurality of metal pads and over an opening of the plurality of openings and couples to the metal pad through the opening.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893