DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/16/2025 has been entered.
Election/Restrictions
Applicant’s election without traverse of claims 1-19 in the reply filed on 3/7/2025 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5 and 10-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. US 2007/0257299.
Re claim 1, Chen teaches a non-volatile memory device (fig1), comprising at least one memory cell (fig2), wherein the at least one memory cell comprises:
a substrate (19, fig2, [21]) comprising a first doped region (21, fig2, [49]) and a second doped region (13, fig2, [46]);
an assist gate (17, fig2, [21]) disposed on the substrate and adjacent to the second doped region (13, fig2, [46]);
a byte select gate (WL 14, fig2, [22]) disposed on the substrate and adjacent to the first doped region (21, fig2, [49]);
a floating gate (11 FG, fig2, [21]) disposed on the substrate and between the assist gate (17, fig2, [21]) and byte select gate (14, fig2, [22]),
wherein the floating gate (11, fig2, [24]) comprising an upper edge (top two edge of FG 11 facing CG16, fig2, [22]) higher than top surfaces of the assist gate (17, fig2, [22]) and the byte select gate (14, fig2, [22]); and
an upper gate (16, fig2, [22]) covering the assist gate (17, fig2, [22]) and the floating gate (11, fig2, [24]),
wherein the upper gate (16, fig2, [22]) is laterally spaced apart (16 and 14 only partially overlap with each other with right side of 16 laterally spaced apart from 14, fig2) from the byte select gate (14, fig2, [22]), and the upper edge of the floating gate (top two edge of FG 11 facing CG16, fig2, [22]) is embedded in the upper gate (16, fig2, [22]).
wherein the byte select gate is configured to turn on or turn off a channel region in the substrate under the byte select gate (word line 14 turn on or off channel region between 21 and source line 13, fig2 and 3).
Re claim 2, Chen teaches the non-volatile memory device of claim 1, wherein the assist gate has the same composition as the byte select gate (14 and 17 formed by etching polysilicon 44, fig4D-4H, [40]).
Re claim 3, Chen teaches the non-volatile memory device of claim 1, wherein the assist gate (17, fig2, [21]) is laterally spaced apart from the byte select gate (14, fig2, [21]).
Re claim 5, Chen teaches the non-volatile memory device of claim 1, wherein the assist gate (17, fig2, [21]), the byte select gate (WL 14, fig2, [22]), and the upper gate (16, fig2, [22]) extend along a same direction (14, 16 and 17 along SL in fig1).
Re claim 10, Chen teaches the non-volatile memory device of claim 1, wherein the at least one memory cell comprises two adjacent memory cells arranged in a same column and having a mirror image of each other (fig1-3).
Re claim 11, Chen teaches the non-volatile memory device of claim 10, wherein the second doped regions (13, fig2 and 3, [46]) of the two adjacent memory cells arranged in the same column are configured to be electrically connected to each other (fig1-3).
Re claim 12, Chen teaches the non-volatile memory device of claim 10, wherein the byte select gates (WL 14, fig2, [22]) of the two adjacent memory cells arranged in the same column are spaced apart from each other.
Allowable Subject Matter
Claims 14-15 and 17-19 are allowed.
Claims 4, 6-9 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
Specifically, the limitations are material to the inventive concept of the application in hand to improve the erase efficiency and reduce power leakage of the memory device.
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812