Office Action Predictor
Last updated: April 15, 2026
Application No. 18/108,733

CHIP-ON-FILM PACKAGE

Non-Final OA §103
Filed
Feb 13, 2023
Examiner
BAIG, ANEESA RIAZ
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Chipbond Technology Corporation
OA Round
2 (Non-Final)
96%
Grant Probability
Favorable
2-3
OA Rounds
3y 3m
To Grant
99%
With Interview

Examiner Intelligence

Grants 96% — above average
96%
Career Allow Rate
26 granted / 27 resolved
+28.3% vs TC avg
Minimal +5% lift
Without
With
+4.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
27 currently pending
Career history
54
Total Applications
across all art units

Statute-Specific Performance

§103
47.0%
+7.0% vs TC avg
§102
27.6%
-12.4% vs TC avg
§112
24.6%
-15.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 27 resolved cases

Office Action

§103
Attorney’s Docket Number: 7017.373 Filing Date: 02/13/2023 Claimed Priority Date: 04/07/2022 (TW 111113338) Applicants: Wu et al Examiner: Aneesa Baig DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments The Response filed on 09/19/2025, responding to the Office action mailed on 07/08/2025, has been entered. Applicant arguments regarding rejections under 35 U.S.C. §102 and 35 U.S.C. §103 are found to be persuasive. Accordingly, new rejections are presented below, and pending in this application are claims 1-12. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1,8,11 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon (US20200266164, Hereinafter Kwon) in view of Pendse (US 20140145340 A1, Hereinafter Pendse). Regarding claim 1, Kwon (e.g., Fig 5A-5E, 6A and 6B [0015]-[0045]) shows most aspects of a chip-on-film package (e.g., Fig 5E) comprising: a chip (102) including a body, a plurality of bond pads (e.g., conductive pad 104), a protective layer (e.g., passivation pattern 106) and a plurality of composite bumps (e.g., Fig 6B), the plurality of bond pads are arranged on the body (Fig 6B), a surface of the body is covered by the protective layer, the protective layer includes a plurality of openings, each of the plurality of openings is configured to expose one of the plurality of bond pads (Fig 5E shows openings which place the bond pads), each of the plurality of composite bumps includes a first raising strip (e.g., 120a), a under bump metallization (UBM) layer (e.g., 152a and 154a) and a bonding layer (e.g., 156a), the first raising strip is located on the protective layer and covered by the UBM layer, the UBM layer of each of the plurality of composite bumps is electrically connected to one of the plurality of bond pads (See Fig 5E), covered by the bonding layer and includes a first rib located on the first raising strip (e.g., first rib of 25 on the stop portion of bump), the bonding layer includes a first bonding rib located on the first rib along a first direction parallel to the surface of the body (e.g., Fig 6B shows the wiring pattern on the first raising strip and on the surface of the body). While Kwon shows a structure of a complaint bumps and bond pads, it does not show the following : a substrate including a plurality of leads; and the first bonding rib of the bonding layer of each of the plurality of composite bumps is configured to be inserted into one of the plurality of leads to allow each of the plurality of leads to include a first restricted rib located above each of the plurality of bond pads Pendse (e.g., Figs 3A, 3B [0014]-[0015] [0017]- [0028]and []), on the other hand and in a related field of complaint bump bonding, shows a substrate (32) including leads (First members each include leads comprised of metal [0021]) and a second member including complaint bumps (34) that are configured to be inserted into the leads of the first substrate). This bonding method allows to mechanically interlock the first and second surfaces through plastic deformation to allow for a robust connection between the metal surfaces. Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the complaint composite bump to be inserted inside a lead structure, as taught by Pendse, to form a robust connection with low failure rates. Regarding Claim 8, Kwon (e.g., Fig 5E) shows, the UBM layers (152a and 154a ) and the bonding layer (156a ) are covering the gap between the bond pads and the first raising strip, and the height of the layer on the first raising strip are is greater than the height on the layers on the surface of the bond pad (104). Regarding Claim 11, Kwon (e.g., Fig 6B) sows the first raising strips to be connected in the first direction. Allowable Subject Matter Claims 2-7, 9-10,12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited disclose devices with composite bumps. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANEESA RIAZ BAIG whose telephone number is (571)272-0249. The examiner can normally be reached Monday-Friday 8am-5pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANEESA RIAZ BAIG/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
Read full office action

Prosecution Timeline

Feb 13, 2023
Application Filed
Jul 03, 2025
Non-Final Rejection — §103
Sep 19, 2025
Response Filed
Jan 03, 2026
Non-Final Rejection — §103
Mar 26, 2026
Response Filed

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12598991
LIQUID CIRCULATING COOLING PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Apr 07, 2026
Patent 12593490
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 31, 2026
Patent 12575101
VERTICAL NON-VOLATILE MEMORY WITH LOW RESISTANCE SOURCE CONTACT
2y 5m to grant Granted Mar 10, 2026
Patent 12568830
SEMICONDUCTOR DEVICE WITH X-SHAPED DIE PAD TO REDUCE THERMAL STRESS AND ION MIGRATION FROM BONDING LAYER
2y 5m to grant Granted Mar 03, 2026
Patent 12557306
CONVEX SHAPE TRENCH IN RDL FOR STRESS RELAXATION
2y 5m to grant Granted Feb 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

2-3
Expected OA Rounds
96%
Grant Probability
99%
With Interview (+4.8%)
3y 3m
Median Time to Grant
Moderate
PTA Risk
Based on 27 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in for Full Analysis

Enter your email to receive a magic link. No password needed.

Free tier: 3 strategy analyses per month