DETAILED ACTION
This Notice is responsive to communication filed on 07/16/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/16/2026 has been entered.
Response to Amendment
The amendment filed on 07/16/2026 under 37 C.F.R. 1.111 has been entered. Claims 1-18, and 20 remain pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference(s).
Claims 1-4, 7, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sano et al. (JP 2010219324 A), and further in view of Hisanaga et al. (US 20210192414).
Regarding claim 1, Sano teaches a semiconductor assembly, comprising:
a substrate Fig. 1: 50 having a mounting surface (top surface of Fig. 1: 50);
a retaining wall Fig. 1: 55 disposed on the mounting surface and having an inner surface;
wherein an accommodation space (i.e. recess between retaining walls 55) is defined by the inner surface and the mounting surface (shown in Fig. 1);
a light emitting unit Fig. 1: 10+20+30 disposed in the accommodation space and disposed on the mounting surface (shown in Fig. 1);
wherein the light emitting unit Fig. 1: 10+20+30 is configured to generate a UV light beam (para. 0025), and has an upper light emitting surface Fig. 1: 90 and a side light emitting surface (para. 0016, “emitted light from the light emitting element 10 is usually radiated not only from the emitting surface but also from the side surface”); and
a reflective resin layer Fig. 1: 40 disposed in the accommodation space and disposed between the inner surface (inner surface of wall 55) and the side light emitting surface (side surface of light emitting elements);
wherein the reflective resin layer Fig. 1: 40 contains:
a based resin,
an organic UV absorber, and
reflective particles Fig. 1: 45 (para. 0033 teaches a based resin material; para. 0034 teaches reflective material including a low-absorbing particle, and para. 0025 teaches the light emitting element emits UV light).
Hisanaga discloses the following claim limitations not disclosed by Sano:
an organic UV absorber.
Hisanaga teaches a laminate that includes a light reflecting layer and a light absorbing layer. The light absorbing layer is a copper complex compound (para. 0079) containing an ultraviolet absorber (para. 0360) which includes a hydroxyphenyltriazine compound (i.e. organic material UV absorber) which allows the UV shielding property to be improved (para. 0376).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Sano with Hisanaga and use an organic UV absorber in order to improve ultraviolet shielding property (para. 0376).
Regarding claim 2, Sano teaches the semiconductor assembly according to claim 1, wherein, relative to the mounting surface, a height of the reflective resin layer Fig. 1: 40 near the side light emitting surface (side surface of) Fig. 1: 20 is lower than or equal to a height of the upper light emitting surface Fig. 1: 90.
Regarding claim 3, Sano teaches the semiconductor assembly according to claim 1, wherein the reflective resin layer Fig. 1: 40 contacts the side light emitting surface and the inner surface, but fails to explicitly teach in this embodiment wherein relative to the mounting surface, a height of the reflective resin layer near the side light emitting surface is lower than a height of the reflective resin layer near the inner surface.
However, in a different embodiment (i.e. Fig. 9), Sano teaches wherein relative to the mounting surface (annotated below), a height of the reflective resin layer Fig. 9: 41 near the side light emitting surface (side surface of Fig. 9: 24) is lower than a height of the reflective resin layer Fig. 9: 41 near the inner surface (see annotated Fig. 9 below).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to include the different heights in the first embodiment to suppress the light diffusion in recess and reduce light absorption by the mounting base/substrate (para. 0066-0067).
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Regarding claim 4, Sano teaches the semiconductor assembly according to claim 1, wherein the reflective resin layer Fig. 1: 40 has a listric surface or a concave surface between the retaining wall Fig. 1: 55 and the light emitting unit Fig. 1: 10+20+30 (shown in Fig. 1).
Regarding claim 7, Sano teaches the semiconductor assembly according to claim 1, wherein, based on a total weight of the based resin being 100 phr, an amount of the reflective particles Fig. 1: 45 ranges from 5 phr to 75 phr. Para. 0035 teaches a weight percent concentration of 20% or more, which falls within the claimed range.
Regarding claim 20, Hisanaga discloses the semiconductor assembly according to claim 1, wherein the organic UV absorber (as described in claim 1) is 2-(2,4-dihydroxyphenyl)-4,6-bis(2,4-dimethyl-phenyl)-1,3,5-triazine (para. 0385).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Sano et al. (JP 2010219324 A) and Hisanaga et al. (US 20210192414) as applied to claim 1 above, and further in view of Ozeki et al. (US 11,121,297).
Regarding claim 5, Ozeki teaches the following claim limitations not disclosed by Sano: the semiconductor assembly according to claim 1:
wherein relative to the mounting surface, a thickness of the reflective resin layer Fig. 1B: 30+40 near the side light emitting surface ranges from 180 µm to 300 µm (col. 7, lines 43-44 discloses a range of 10-200µm which includes the claimed range).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Sano with Ozeki for the purpose of facilitating the formation of the reflecting layer and improving the effect achieved by disposing the reflecting material layer, reducing surface tension induced creeping up to the resin onto the lateral surfaces of the light emitting element (col. 7, lines 45-50).
Claims 6, 8, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Sano et al. (JP 2010219324) and Hisanaga et al. (US 20210192414) as applied to claim 1 above, and further in view of Morita (US 20170254936 A1).
Regarding claim 6, Morita teaches the following claim limitations not disclosed by Sano or Hisanaga: the semiconductor assembly according to claim 1:
wherein, based on a total weight of the based resin being 100 phr, an amount of the organic UV absorber ranges from 0.1 phr to 15 phr.
In para. 0014 Morita teaches a buffer layer that includes a UV absorbing monomer with a 5 mass% or more before molding and 3 mass% or less after molding, which includes the range taught in claim 6. It is acknowledged that phr based on a total weight of the based resin being 100 phr will be equivalent to a percent mass.
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Sano and Hisanaga with Morita for the purpose of enhancing the buffering property and also to suppress external stress and prevent deterioration of optical reflectance (para. 0121-0122).
Regarding claim 8, Morita teaches the following claim limitations not disclosed by Sano or Hisanaga: the semiconductor assembly according to claim 1:
wherein the reflective resin layer (i.e. light reflecting film) further contains a hindered amine light stabilizer.
Para. 0014 discloses the light reflecting film containing at least one UV stable monomer, and para. 0124 discloses the UV stable monomer including a hindered amine light stabilizer.
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Sano and Hisanaga with Morita to include a HALS for the purpose of increasing self-restoring and scratch resistance properties of the light reflecting film and also enhancing light resistance (para. 0123).
Regarding claim 9, Morita teaches the following claim limitations not disclosed by Sano or Hisanaga: the semiconductor assembly according to claim 8:
wherein based on a total weight of the based resin being 100 phr, an amount of the hindered amine light stabilizer ranges from 0.1 phr to 15 phr.
In para. 0014, Morita discloses a buffer layer that includes a UV stable monomer with a 5 mass% or more before molding and 3 mass% or less after molding, which includes the range taught by claim 9.
It would be obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Sano and Morita to include a HALS for the purpose of enhancing the buffering property and also to suppress external stress and prevent deterioration of optical reflectance (para. 0121-0122).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Sano et al. (JP 2010219324) and Hisanaga et al. (US 20210192414) as applied to claim 1 above, and further in view of Miura et al. (US 11,934,003 B2).
Regarding claim 10, Miura teaches following claim limitations not disclosed by Sano or Hisanaga: the semiconductor assembly according to claim 1 further comprising:
a first light transmitting layer Fig. 4: 22 disposed between the substrate Fig. 4: 50 and the reflective resin layer Fig. 4: 40,
wherein the first light transmitting layer Fig. 4: 22 contains a first based resin and a UV absorber (col. 5, lines 27-50).
Miura teaches a light adjusting member 40 (i.e. reflective layer) that includes a resin, zirconia (a UV absorber) and light scattering particles (col. 8, lines 22-33).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Sano (including the reflective resin layer) and Hisanaga with Miura and include a transmitting layer for the purpose of protecting the upper and lateral surfaces of the light emitting element, while performing wavelength conversion and light diffusion functions (col. 5, lines 20-26).
Claims 11, 12, 14, 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Sano et al. (JP 2010219324), Hisanaga et al. (US 20210192414) and Miura et al. (US 11,934,003 B2), and further in view of Kumano et al. (US 20230155084 A1).
Regarding claim 11, Kumano teaches following claim limitations not disclosed by Sano: the semiconductor assembly according to claim 10, wherein:
based on a total weight of the first based resin Fig. 1: 31 being 100 phr, an amount of the UV absorber Fig. 1: 9 ranges from 0.1 phr to 2 phr.
Kumano teaches a diffusion layer Fig. 1: 3 (i.e. first transmitting layer) containing a resin Fig. 1: 31 and a diffusion material Fig. 1: 9 (i.e. titanium oxide, para. 0092) wherein the diffusion material Fig. 1: 9 based on the resin Fig. 1: 31 had a concentration of 0.1 mass% to 20 mass% (para. 0084), which includes the range taught in claim 11.
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Sano, Hisanaga, and Miura, with Kumano for the purpose of suppressing a decrease in luminous flux while exhibiting a desired light diffusion effect (para. 0084).
Regarding claim 12, Kumano teaches the following claim limitations not disclosed by Sano: the semiconductor assembly according to claim 10:
wherein, relative to the mounting surface, a thickness of the first light transmitting layer Fig. 1: 3 (i.e. diffusion layer) near the side light emitting surface ranges from 50 µm to 100 µm.
Kumano teaches a portion the diffusion layer Fig. 1:3 (i.e. first light transmitting layer) overlapping in a side surface direction of the light emitting element Fig. 1: 2, having a thickness in a range from 20 µm to 100 µm (para. 0093), which includes the range taught in claim 12.
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Sano, Miura, and Kumano for the purpose of further improving the luminance of the light-emitting device (para. 0102).
Regarding claim 14, Sano, Hisanga, and Miura disclose the semiconductor assembly according to claim 10, wherein further comprising:
a second light transmitting layer Fig. 4: 30 (Miura) disposed between the reflective resin layer Fig. 4: 40 (Miura) and the first light transmitting layer Fig. 4: 22 (Miura),
wherein the second light transmitting layer Fig. 4: 30 contains a second based resin and a UV absorber (col. 7, lines 55-61, 65-67 “phosphor”),
an amount of the UV absorber in the second light transmitting layer is larger than an amount of the UV absorber in the first light transmitting layer.
Kumano teaches the following claim limitations not disclosed by Sano:
an amount of the UV absorber Fig. 1: 9 (i.e. diffusion material) in the second light transmitting layer Fig. 1: 3 (i.e. diffusion layer) is larger than an amount of the UV absorber in the first light transmitting layer Fig. 1: 4.
Kumano teaches a light transmitting body Fig. 1: 4 (i.e. first transmitting layer) that does not include a UV absorber, and a diffusion layer (i.e. second light transmitting layer) that includes a UV absorber. Hence, an amount of the UV absorber in the second light transmitting layer would be larger than an amount in the first light transmitting layer.
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Sano, Hisanaga, Miura with Kumano for the purpose of reducing illumination unevenness in a light emitting device (para. 0013) and controlling the optical characteristics including directional chromaticity of the light-emitting device (para. 0083).
Regarding claim 15, Kumano teaches the following claim limitations not disclosed by Sano: the semiconductor assembly according to claim 14,
wherein, based on a total weight of the second based resin Fig. 1: 31 being 100 phr, an amount of the UV absorber Fig. 1: 9 ranges from 0.1 phr to 2 phr.
Kumano teaches a diffusion layer Fig. 1: 3 (i.e. second transmitting layer, using Fig. 1: 4 as the first transmitting layer) containing a resin Fig. 1: 31 and a diffusion material Fig. 1: 9 (i.e. titanium oxide, para. 0092) wherein the diffusion material Fig. 1: 9 based on the resin Fig. 1: 31 had a concentration of 0.1 mass% to 20 mass% (para. 0084), which includes the range taught in claim 15.
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Sano, Hisanaga, Miura with Kumano for the purpose of suppressing a decrease in luminous flux while exhibiting a desired light diffusion effect (para. 0084).
Regarding claim 16, Kumano teaches the following claim limitations not disclosed by Sano: the semiconductor assembly according to claim 14,
wherein, relative to the mounting surface, a thickness of the second light transmitting layer Fig. 1: 3 (i.e. diffusion layer) near the side light emitting surface ranges from 50 µm to 100 µm.
Kumano teaches a portion the diffusion layer Fig. 1:3 (i.e second transmitting layer, using Fig. 1: 4 as the first transmitting layer) overlapping in a side surface direction of the light emitting element Fig. 1: 2, having a thickness in a range from 20 µm to 100 µm (para. 0093), which includes the range taught in claim 16.
It would have obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Sano, Miura, and Kumano for the purpose of further improving the luminance of the light-emitting device (para. 0102).
Claims 13, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Sano et al. (JP 2010219324), Hisanaga et al. (US 20210192414), and Miura et al. (US 11,934,003 B2) as applied to claim 10 above, and further in view of Chae (US 20220259349 A1).
Regarding claim 13, Chae teaches following claim limitations not disclosed by Sano: the semiconductor assembly according to claim 10,
wherein the first light transmitting layer Fig. 3: 420 (i.e. resin layer) further contains a hindered amine light stabilizer (para. 0008), and based on a total weight of the first based resin being 100 phr, an amount of the hindered amine light stabilizer ranges from 0.1 phr to 15 phr (para. 0058).
Chae teaches a resin layer Fig. 3: 420 with an optical resin, including an oligomer and monomer, and a light stabilizer content of 0.5-2 wt% based on the resin (oligomer and monomer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Sano, Hisanaga, and Miura, with Chae for the purpose of suppressing decomposition and discoloration of the resin (para. 0008) and increasing the speed of curing the resin (para. 0028).
Regarding claim 17, Chae teaches following claim limitations not disclosed by Sano: the semiconductor assembly according to claim 10:
wherein the second light transmitting layer Fig. 3: 420 (i.e. resin layer, using Fig. 1: 415 as the first transmitting layer) further contains a hindered amine light stabilizer (para. 0008), and
based on a total weight of the second based resin being 100 phr, an amount of the hindered amine light stabilizer ranges from 0.1 phr to 15 phr (para. 0058).
Chae teaches a resin layer Fig. 3: 420 with an optical resin, including an oligomer and monomer, and a light stabilizer content of 0.5-2 wt% based on the resin (oligomer and monomer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Sano, Hisanaga, and Miura, with Chae for the purpose of suppressing decomposition and discoloration of the resin (para. 0008) and increasing the speed of curing the resin (para. 0028).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Sano et al. (JP 2010219324) and Hisanaga et al. (US 20210192414) as applied to claim 1 above, and further in view of Chae (US 20220259349 A1).
Regarding claim 18, Chae teaches the following claim limitations not disclosed by Sano: the semiconductor assembly according to claim 1,
wherein the based resin is a methyl silicon resin, a methyl phenyl vinyl silicon resin, or a combination thereof (para. 0028).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Sano and Hisanaga with Chae for the purpose of using heat resistant materials to withstand heat conducted through the substrate and light-emitting device (para. 0028).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-18, and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
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/Nkechinyere Esiaba/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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