DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The present application, 18109212 filed 02/13/2023 is a Continuation of 16459080, filed 07/01/2019, now U.S. Patent # 11609743, 16459080 is a Continuation of 16014737, filed 06/21/2018, now U.S. Patent # 10387120 16014737 is a Continuation of 15450531, filed 03/06/2017, now U.S. Patent # 10031723 15450531 Claims Priority from Provisional Application 62305065, filed 03/08/2016.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/14/2023 and 07/27/2023 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
A. A system comprising: a plurality of cryptographic modules each configured to process packets, wherein the packet processing includes encrypting a packet based on a security key associated with the packet as specified in claim 31
B. a first interface coupled to the plurality of cryptographic modules and configured to receive an incoming packet, associate a first security key with the incoming packet, select one of the plurality of cryptographic modules, and route the incoming packet to the selected cryptographic module as specified in claim 33
C. A system comprising: a plurality of programmable cryptographic devices, each cryptographic device configured to receive the random number value as specified in claim 36
D. A system comprising: at least one programmable input/output interface configured to route each of a plurality of incoming packets to one of the cryptographic devices for encryption as specified in claim 36
E. wherein each of the plurality of programmable cryptographic devices comprises at least one of a programmable systolic packet input engine, a programmable systolic cryptographic engine, or a programmable systolic packet output engine as specified in claim 38
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “122” has been used to designate both register and output of shift register 110 in Figure 1.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to under 37 C.F.R. 1.57(d) which states that "Essential material" may be incorporated by reference, but only by way of an incorporation by reference to a U.S. patent or U.S. patent application publication, however, the incorporation by reference in paragraph [0044] is by the application serial number (14/177,392).
Claim Objections
The numbering of claims is not in accordance with 37 CFR 1.126 which requires the original numbering of the claims to be preserved throughout the prosecution. When claims are canceled, the remaining claims must not be renumbered. When new claims are presented, they must be numbered consecutively beginning with the number next following the highest numbered claims previously presented (whether entered or not).
Misnumbered claims 21-40 been renumbered 26-45 respectively.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
plurality of cryptographic modules recited in claim 31
first interface recited in claim 33
plurality of programmable cryptographic devices first recited in claim 36
at least one programmable input/output interface first recited in claim 36
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
cryptographic modules/programmable cryptographic devices: see of 14177392 Fig. 3 and paragraphs [0048-0049]; the cryptographic modules/programmable cryptographic devices includes the components of Fig. 3
first interface/programmable input/output interface: see 14177392 paragraph [0031] programmable I/O interface 106 (implemented using an FPGA I/O systolic array); paragraph [0034] The I/O interface incorporates functional blocks (e.g., 100 Gbs Ethernet, PCI-express, Fibre channel, SAS, Infiniband, SCSI, or any other high speed interface protocols) that are incorporated; paragraphs [0041-0042, 0050]
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21-35 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 recites “the systolic array” in line 7. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this is interpreted as the at least two-dimensional array instead. Claim 25 recites a similar limitation in lines 2-3 and is rejected for the same reason. Claims 22-30 inherit the same deficiency as claim 21 by reason of dependence.
Claim 31 recites “the packet processing” in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this is interpreted as processing of the packets instead. Claims 32-35 inherit the same deficiency as claim 31 by reason of dependence.
Claim 35 recites “the memory” in line 3. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, claim 35 is interpreted to depend on claim 32 which introduces the memory.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21 and 23-24 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 8 U.S. Patent No. US 10,031,723 B1. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 21 and 23-24 under examination are anticipated by claim 8 of the reference patent. Every limitation in the application under examination claims is recited in the conflicting reference patent claims as shown in the table below.
18109212
US 10,031,723 B1
21. A random number generator comprising:
8. A random number generator comprising:
a plurality of cells configured in an at least two-dimensional array, each cell comprising an oscillator, wherein the at least two-dimensional array is arranged to provide a random number output;
a plurality of cells arranged in at least a two-dimensional systolic array, each cell comprising an oscillator, the systolic array to receive a plurality of first inputs in first and second sides of the array, and the systolic array to provide a random number output;
a physical unclonable function configured to provide input to the at least two-dimensional array; and
at least one memory configured to provide the first inputs to the systolic array; and wherein the memory provides a physical unclonable function for the random number generator
a shift register configured to receive the random number output from the systolic array and to provide a feedback signal to the physical unclonable function for selecting the input.
a shift register configured to receive the random number output, and further configured to address the memory to select the first inputs to provide to the systolic array.
Regarding claims 23-24, they are anticipated by claims 8 and 1 respectively of the reference patent. Mapping for these claims are not being shown for the purpose of brevity.
Claims 21-30 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-16 of U.S. Patent No. US 10,031,723 B1 (the reference patent) in view of Maes et al. (US 20180241557 A1), hereinafter Maes.
Regarding claim 21, claim 1 of the reference patent teaches all the limitations of claim 21 as shown below except for the limitations that are struck-through.
18109212
US 10,031,723 B1
21. A random number generator comprising:
1. A random number generator comprising:
a plurality of cells configured in an at least two-dimensional array, each cell comprising an oscillator, wherein the at least two-dimensional array is arranged to provide a random number output;
a plurality of cells arranged in at least a two-dimensional systolic array, each cell comprising an oscillator, the systolic array to receive a plurality of first inputs in first and second sides of the array, and the systolic array to provide a random number output;
at least one memory configured to provide the first inputs to the systolic array; and
a shift register configured to receive the random number output from the systolic array and to provide a feedback signal to the physical unclonable function for selecting the input.
a shift register configured to receive the random number output, and further configured to address the memory to select the first inputs to provide to the systolic array.
Claim 1 of the reference patent does not explicitly teach a physical unclonable function configured to provide input to the at least two-dimensional array.
However, on the same field of endeavor, Maes discloses a physical unclonable function configured to provide input to a random number generator (Maes Fig. 1 and paragraphs [0098, 0101, 0114-0115, 0117]; at least one memory – SRAM PUF 110).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the reference patent using and configure the at least one memory as an SRAM PUF that is configured to provide the first inputs to the systolic array in order to further increase the randomness of the random number by using a PUF output to generate a seed for the systolic array (Maes paragraph [0096-0098]).
Therefore, the combination of the reference patent as modified in view of Maes teaches a physical unclonable function configured to provide input to the at least two-dimensional array.
Regarding claims 22-24 and 26-30, they are anticipated by claims 10, 1/8, 1, 2, 5, 6, 13, and 9 respectively of the reference patent. Mapping for these claims are not being shown for the purpose of brevity.
Regarding claim 25, claim 1 of the reference patent as modified in view of Maes teaches all the limitations of claim 21 as stated above. Further, the reference patent as modified in view of Maes teaches wherein the physical unclonable function, as directed by the shift register, is used to seed the oscillators in the systolic array (Maes paragraphs [0101, 0114-0115, 0117]).
Claims 31-37 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 16 of U.S. Patent No. US 10,031,723 B1 (the reference patent) in view of Salinger et al. (US 20140108782 A1), hereinafter Salinger, and Maes.
Regarding claim 31, claim 16 of the reference patent teaches all the limitations of claim 21 as shown below except for the limitations that are struck-through.
18109212
US 10,031,723 B1
31. A system comprising:
16. A random number generator comprising:
a systolic array configured to receive a plurality of inputs, and to provide a random number output to
16. a plurality of cells arranged in at least a two-dimensional systolic array, each cell comprising an oscillator, the systolic array to receive a plurality of first inputs in first and second sides of the array, and the systolic array to provide a random number output; wherein the second output register provides the random number output to a host processor.
Claim 16 of the reference patent does not explicitly teach a plurality of cryptographic modules each configured to process packets, wherein the packet processing includes encrypting a packet based on a security key associated with the packet; and a systolic array configured to receive a plurality of inputs, and to provide a random number output to one or more of the plurality of cryptographic modules.
However, on the same field of endeavor, Salinger discloses a plurality of cryptographic modules each configured to process packets, wherein the packet processing includes encrypting a packet based on a security key associated with the packet (Salinger Fig. 2A-2B and paragraphs [0026, 0028-0032] plurality of cryptographic modules – 220; packets – content data packets; security key - encryption key).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the reference patent and configure the host processor to include a plurality of cryptographic modules receiving the random number output and using the random number output to generate the encryption keys (Maes paragraphs [0113, 0115 and 0122]) used for encrypting the packets.
Therefore, the combination of the reference patent as modified in view of Salinger and Maes teaches a plurality of cryptographic modules each configured to process packets, wherein the packet processing includes encrypting a packet based on a security key associated with the packet; and a systolic array configured to receive a plurality of inputs, and to provide a random number output to one or more of the plurality of cryptographic modules.
Regarding claims 32 and 34-35, they are anticipated by claims 16, 16, and 16 respectively of the reference patent. Mapping for these claims are not being shown for the purpose of brevity.
Regarding claim 33, claim 16 of the reference patent as modified in view of Salinger and Maes teaches all the limitations of claim 31 as stated above.
The reference patent does not explicitly teach further comprising: a first interface coupled to the plurality of cryptographic modules and configured to receive an incoming packet, associate a first security key with the incoming packet, select one of the plurality of cryptographic modules, and route the incoming packet to the selected cryptographic module.
However, on the same field of endeavor, Salinger discloses further comprising: a first interface coupled to the plurality of cryptographic modules and configured to receive an incoming packet, associate a first security key with the incoming packet, select one of the plurality of cryptographic modules, and route the incoming packet to the selected cryptographic module (Salinger Fig. 2A and paragraphs [0022-0024]; first interface – 204 and/or 206).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the reference patent and further include a first interface coupled to the plurality of cryptographic modules and configured to receive an incoming packet, associate a first security key with the incoming packet, select one of the plurality of cryptographic modules, and route the incoming packet to the selected cryptographic module in order to communicate with other devices over a larger network (Salinger paragraph [0020]).
Therefore, the combination of the reference patent as modified in view of Salinger and Maes teaches further comprising: a first interface coupled to the plurality of cryptographic modules and configured to receive an incoming packet, associate a first security key with the incoming packet, select one of the plurality of cryptographic modules, and route the incoming packet to the selected cryptographic module.
Regarding claim 36, claim 16 of the reference patent teaches all the limitations of claim 36 as shown below except for the limitations that are struck-through.
18109212
US 10,031,723 B1
36. A system comprising:
a random number generator comprising:
16. A random number generator comprising:
a systolic array configured to provide a random number value, wherein the systolic array comprises a plurality of cells, and each cell comprises an oscillator;
16. a plurality of cells arranged in at least a two-dimensional systolic array, each cell comprising an oscillator, the systolic array to receive a plurality of first inputs in first and second sides of the array, and the systolic array to provide a random number output; wherein the second output register provides the random number output to a host processor.
Claim 16 of the reference patent does not explicitly teach a plurality of programmable cryptographic devices, each cryptographic device configured to receive the random number value; and at least one programmable input/output interface configured to route each of a plurality of incoming packets to one of the cryptographic devices for encryption.
However, on the same field of endeavor, Salinger discloses a plurality of programmable cryptographic devices (Salinger Fig. 2A-2B and paragraphs [0026, 0028-0032] plurality of cryptographic modules – 220); and at least one programmable input/output interface configured to route each of a plurality of incoming packets to one of the cryptographic devices for encryption (Salinger Fig. 2A and paragraphs [0022-0024]; at least one programmable input/output interface – 204 and/or 206).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the reference patent and configure the host processor to include a plurality of programmable cryptographic devices, each configured to receive the random number value and use the random number value to generate encryption keys (Maes paragraphs [0113, 0115 and 0122]). Further, include at least one programmable input/output interface configured to route each of a plurality of incoming packets to one of the cryptographic devices for encryption in order to communicate with other devices over a larger network (Salinger paragraph [0020]).
Therefore, the combination of the reference patent as modified in view of Salinger and Maes teaches a plurality of programmable cryptographic devices, each cryptographic device configured to receive the random number value; and at least one programmable input/output interface configured to route each of a plurality of incoming packets to one of the cryptographic devices for encryption.
Regarding claim 37, claim 16 of the reference patent as modified in view of Salinger and Maes teaches all the limitations of claim 36 as stated above. Further, the reference patent as modified in view of Salinger and Maes teaches wherein: the programmable input/output interface is programmable to support different interface protocols, and each of the plurality of cryptographic devices is programmable to support different encryption protocols (Salinger paragraphs [0015-0017, 0021, 0026, 0028, 0038, 0040, 0059]).
Claim 38 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 16 of U.S. Patent No. US 10,031,723 B1 (the reference patent) in view of Salinger and Maes as applied to claim 36 above, and further in view of Leung et al. (US 20070195951 A1), hereinafter Leung.
Regarding claim 38, claim 16 of the reference patent as modified in view of Salinger and Maes teaches all the limitations of claim 36 as stated above.
Claim 16 of the reference patent does not explicitly teach wherein each of the plurality of programmable cryptographic devices comprises at least one of a programmable systolic packet input engine, a programmable systolic cryptographic engine, or a programmable systolic packet output engine.
However, on the same field of endeavor, Leung discloses a cryptographic devices comprising at least one of a programmable systolic packet input engine, a programmable systolic cryptographic engine, or a programmable systolic packet output engine (Leung Fig. 2 and paragraph [0026]).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify each programmable cryptographic device to include at least one of a programmable systolic packet input engine, a programmable systolic cryptographic engine, or a programmable systolic packet output engine in order to increase throughput encrypt functions because a systolic array allows multiple packets to be processed in a parallel manner (Leung paragraph [0026]).
Therefore, the combination of the reference patent as modified in view of Salinger, Maes and Leung teaches wherein each of the plurality of programmable cryptographic devices comprises at least one of a programmable systolic packet input engine, a programmable systolic cryptographic engine, or a programmable systolic packet output engine.
Claims 39-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 16 of U.S. Patent No. US 10,031,723 B1 (the reference patent) in view of Salinger and Maes applied to claim 36 above, and further in view of Carlson et al. (US 20050055391 A1), hereinafter Carlson.
Regarding claim 39, claim 16 of the reference patent as modified in view of Salinger and Maes teaches all the limitations of claim 36 as stated above.
Claim 16 of the reference patent does not explicitly teach wherein the oscillator is a free-running asynchronous oscillator.
However, on the same field of endeavor, Carlson discloses a random number generator that includes a free-running asynchronous oscillator (Carlson Figs. 1-2 and paragraphs [0008, 0024-0025]).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the oscillator in each cell as a free-running asynchronous oscillator in order to reduce power consumption as the oscillator design uses small size transistors (Carlson paragraph [0024]).
Therefore, the combination of the reference patent as modified in view of Salinger, Maes and Carlson teaches wherein the oscillator is a free-running asynchronous oscillator.
Regarding claim 40, claim 16 of the reference patent as modified in view of Salinger and Maes teaches all the limitations of claim 36 as stated above.
Claim 16 of the reference patent does not explicitly teach wherein each cell further comprises a flip-flop that receives an input signal from the oscillator.
However, on the same field of endeavor, Carlson discloses a random number generator that includes a flip-flop that receives an input signal from an oscillator (Carlson Fig. 1 and paragraph [0019]] flip-flop - sampling device 110A-110N).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify each cell to include a flip-flop after the oscillator for synchronously sampling each oscillator output and latching the random bit generated by the corresponding oscillator (Carlson paragraph [0019]).
Therefore, the combination of the reference patent as modified in view of Salinger, Maes and Carlson teaches wherein each cell further comprises a flip-flop that receives an input signal from the oscillator.
Claims 21-24 and 26-30 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-16 of U.S. Patent No. US 10,387,120 B2 (the reference patent) in view of Chuang et al. (US 6240432 B1), hereinafter Chuang, and Van Der Sluis et al. (US 20150234751 A1), hereinafter VDS. Chuang is cited in the IDS submitted on 02/14/2023.
Regarding claim 21, claim 1 of the reference patent teaches all the limitations of claim 21 as shown below except for the limitations that are struck-through.
18109212
US 10,387,120 B2
21. A random number generator comprising:
1. A random number generator comprising:
a plurality of cells
a systolic array comprising a plurality of cells, wherein each cell comprises an oscillator, and the systolic array is configured to provide a random number output;
memory configured to provide inputs to the systolic array,
wherein a feedback signal based on the random number output is used to address the memory to select the inputs.
Claim 1 of the reference patent does not explicitly teach a plurality of cells configured in an at least two-dimensional array; a physical unclonable function configured to provide input to the at least two-dimensional array; and a shift register configured to receive the random number output from the systolic array and to provide a feedback signal to the physical unclonable function for selecting the input.
However, on the same field of endeavor, Chuang discloses a random number generator comprising a plurality of cells configured in an at least two-dimensional array (Chuang Fig. 1).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the systolic array as a two-dimensional array in order to provide a more compact random number generator by reducing the length of wiring connections among the random number generator circuit components such as the feedback path (Chuang Fig. 1).
Therefore, the combination of the reference patent as modified in view of Chuang teaches teach a plurality of cells configured in an at least two-dimensional array.
Claim 1 of the reference patent does not explicitly teach a physical unclonable function configured to provide input to the at least two-dimensional array; and a shift register configured to receive the random number output from the systolic array and to provide a feedback signal to the physical unclonable function for selecting the input.
However, on the same field of endeavor, VDS discloses a physical unclonable function; and a shift register configured to provide an address signal to the physical unclonable function for addressing the physical unclonable function (VDS Fig. 1a and paragraphs [0086, 0088, 0093] physical unclonable function – memory 110; shift register - address scrambler 140).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the reference patent and configure the one memory as an SRAM PUF and include a shift register to receive the random number output from the systolic array and to provide a feedback signal to the physical unclonable function for selecting the input in order to reduce side channel leakage by scrambling the transfer of the content of the PUF (VDS paragraph [0017, 0024, 0028]).
Therefore, the combination of the reference patent as modified in view of Chuang and VDS teaches a physical unclonable function configured to provide input to the at least two-dimensional array; and a shift register configured to receive the random number output from the systolic array and to provide a feedback signal to the physical unclonable function for selecting the input.
Regarding claim 22, claim 1 of the reference patent as modified in view of Chuang and VDS teaches all the limitations of claim 21 as stated above. Further, the reference patent as modified in view of Chuang and VDS teaches wherein the oscillator in each cell is a ring oscillator (Chuang Fig. 2 and col 3 lines 27-30).
Regarding claims 23-24 and 26-29, they are anticipated by claims 5, 1-4 and 6 respectively of the reference patent. Mapping for these claims are not being shown for the purpose of brevity.
Regarding claim 30, claim 1 of the reference patent as modified in view of Chuang and VDS teaches all the limitations of claim 21 as stated above. Further, the reference patent as modified in view of Chuang and VDS teaches wherein the shift register comprises a linear feedback shift register (VDS paragraph [0093]).
Claim 25 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. US 10,387,120 B2 (the reference patent) in view of Chuang and VDS as applied to claim 21 above, and further in view of Maes.
Regarding claim 25, claim 1 of the reference patent as modified in view of Chuang and VDS teaches all the limitations of claim 21 as stated above.
Claim 1 of the reference patent does not explicitly teach wherein the physical unclonable function, as directed by the shift register, is used to seed the oscillators in the systolic array.
However, on the same field of endeavor, Maes discloses a physical unclonable function that is used to seed a random number generator (Maes paragraphs [0101, 0114-0115, 0117]).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the reference patent using and configure the physical unclonable function to seed the oscillators in the systolic array to further increase the randomness of the random number by using the PUF output to generate a seed for the systolic array (Maes paragraph [0096-0098]).
Therefore, the combination of the reference patent as modified in view of Chuang, VDS and Maes teaches wherein the physical unclonable function, as directed by the shift register, is used to seed the oscillators in the systolic array.
Claims 31-37 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. US 10,387,120 B2 (the reference patent) in view of Salinger and Maes.
Regarding claim 31, claim 1 of the reference patent teaches all the limitations of claim 31 as shown below except for the limitations that are struck-through.
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31. A system comprising:
1. A random number generator comprising:
a systolic array configured to receive a plurality of inputs, and to provide a random number output
a systolic array comprising a plurality of cells, wherein each cell comprises an oscillator, and the systolic array is configured to provide a random number output;
Claim 1 of the reference patent does not explicitly teach a plurality of cryptographic modules each configured to process packets, wherein the packet processing includes encrypting a packet based on a security key associated with the packet; and a systolic array configured to receive a plurality of inputs, and to provide a random number output to one or more of the plurality of cryptographic modules.
However, on the same field of endeavor, Salinger discloses a plurality of cryptographic modules each configured to process packets, wherein the packet processing includes encrypting a packet based on a security key associated with the packet (Salinger Fig. 2A-2B and paragraphs [0026, 0028-0032] plurality of cryptographic modules – 220; packets – content data packets; security key - encryption key).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the reference patent and configure the host processor to include a plurality of cryptographic modules receiving the random number output and using the random number output to generate the encryption keys (Maes paragraphs [0113, 0115 and 0122]) used for encrypting the packets.
Therefore, the combination of the reference patent as modified in view of Salinger and Maes teaches a plurality of cryptographic modules each configured to process packets, wherein the packet processing includes encrypting a packet based on a security key associated with the packet; and a systolic array configured to receive a plurality of inputs, and to provide a random number output to one or more of the plurality of cryptographic modules.
Regarding claims 32 and 34-35, they are anticipated by claims 1, 1, and 10 respectively of the reference patent. Mapping for these claims are not being shown for the purpose of brevity.
Regarding claim 33, claim 1 of the reference patent as modified in view of Salinger and Maes teaches all the limitations of claim 31 as stated above.
The reference patent does not explicitly teach further comprising: a first interface coupled to the plurality of cryptographic modules and configured to receive an incoming packet, associate a first security key with the incoming packet, select one of the plurality of cryptographic modules, and route the incoming packet to the selected cryptographic module.
However, on the same field of endeavor, Salinger discloses further comprising: a first interface coupled to the plurality of cryptographic modules and configured to receive an incoming packet, associate a first security key with the incoming packet, select one of the plurality of cryptographic modules, and route the incoming packet to the selected cryptographic module (Salinger Fig. 2A and paragraphs [0022-0024]; first interface – 204 and/or 206).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the reference patent and further include a first interface coupled to the plurality of cryptographic modules and configured to receive an incoming packet, associate a first security key with the incoming packet, select one of the plurality of cryptographic modules, and route the incoming packet to the selected cryptographic module in order to communicate with other devices over a larger network (Salinger paragraph [0020]).
Therefore, the combination of the reference patent as modified in view of Salinger and Maes teaches further comprising: a first interface coupled to the plurality of cryptographic modules and configured to receive an incoming packet, associate a first security key with the incoming packet, select one of the plurality of cryptographic modules, and route the incoming packet to the selected cryptographic module.
Regarding claim 36, claim 1 of the reference patent teaches all the limitations of claim 36 as shown below except for the limitations that are struck-through.
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36. A system comprising:
a random number generator comprising:
1. A random number generator comprising:
a systolic array configured to provide a random number value, wherein the systolic array comprises a plurality of cells, and each cell comprises an oscillator;
a systolic array comprising a plurality of cells, wherein each cell comprises an oscillator, and the systolic array is configured to provide a random number output;
Claim 1 of the reference patent does not explicitly teach a plurality of programmable cryptographic devices, each cryptographic device configured to receive the random number value; and at least one programmable input/output interface configured to route each of a plurality of incoming packets to one of the cryptographic devices for encryption.
However, on the same field of endeavor, Salinger discloses a plurality of programmable cryptographic devices (Salinger Fig. 2A-2B and paragraphs [0026, 0028-0032] plurality of cryptographic modules – 220); and at least one programmable input/output interface configured to route each of a plurality of incoming packets to one of the cryptographic devices for encryption (Salinger Fig. 2A and paragraphs [0022-0024]; at least one programmable input/output interface – 204 and/or 206).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the reference patent and configure the host processor to include a plurality of programmable cryptographic devices, each configured to receive the random number value and use the random number value to generate encryption keys (Maes paragraphs [0113, 0115 and 0122]). Further, include at least one programmable input/output interface configured to route each of a plurality of incoming packets to one of the cryptographic devices for encryption in order to communicate with other devices over a larger network (Salinger paragraph [0020]).
Therefore, the combination of the reference patent as modified in view of Salinger and Maes teaches a plurality of programmable cryptographic devices, each cryptographic device configured to receive the random number value; and at least one programmable input/output interface configured to route each of a plurality of incoming packets to one of the cryptographic devices for encryption.
Regarding claim 37, claim 1 of the reference patent as modified in view of Salinger and Maes teaches all the limitations of claim 36 as stated above. Further, the reference patent as modified in view of Salinger and Maes teaches wherein: the programmable input/output interface is programmable to support different interface protocols, and each of the plurality of cryptographic devices is programmable to support different encryption protocols (Salinger paragraphs [0015-0017, 0021, 0026, 0028, 0038, 0040, 0059]).
Claim 38 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. US 10,387,120 B2 (the reference patent) in view of Salinger and Maes as applied to claim 36 above, and further in view of Leung.
Regarding claim 38, claim 1 of the reference patent as modified in view of Salinger and Maes teaches all the limitations of claim 36 as stated above.
Claim 1 of the reference patent does not explicitly teach wherein each of the plurality of programmable cryptographic devices comprises at least one of a programmable systolic packet input engine, a programmable systolic cryptographic engine, or a programmable systolic packet output engine.
However, on the same field of endeavor, Leung discloses a cryptographic devices comprising at least one of a programmable systolic packet input engine, a programmable systolic cryptographic engine, or a programmable systolic packet output engine (Leung Fig. 2 and paragraph [0026]).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify each programmable cryptographic device to include at least one of a programmable systolic packet input engine, a programmable systolic cryptographic engine, or a programmable systolic packet output engine in order to increase throughput encrypt functions because a systolic array allows multiple packets to be processed in a parallel manner (Leung paragraph [0026]).
Therefore, the combination of the reference patent as modified in view of Salinger, Maes and Leung teaches wherein each of the plurality of programmable cryptographic devices comprises at least one of a programmable systolic packet input engine, a programmable systolic cryptographic engine, or a programmable systolic packet output engine.
Claims 39-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. US 10,387,120 B2 (the reference patent) in view of Salinger and Maes applied to claim 36 above, and further in view of Carlson.
Regarding claim 39, claim 1 of the reference patent as modified in view of Salinger and Maes teaches all the limitations of claim 36 as stated above.
Claim 1 of the reference patent does not explicitly teach wherein the oscillator is a free-running asynchronous oscillator.
However, on the same field of endeavor, Carlson discloses a random number generator that includes a free-running asynchronous oscillator (Carlson Figs. 1-2 and paragraphs [0008, 0024-0025]).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the oscillator in each cell as a free-running asynchronous oscillator in order to reduce power consumption as the oscillator design uses small size transistors (Carlson paragraph [0024]).
Therefore, the combination of the reference patent as modified in view of Salinger, Maes and Carlson teaches wherein the oscillator is a free-running asynchronous oscillator.
Regarding claim 40, it is anticipated by claim 2 of the reference patent. Mapping for the claim is not being shown for the purpose of brevity.
Claims 21-24 and 29-30 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 7 of U.S. Patent No. US 11,609,743 B2 (the reference patent) in view of Chuang and VDS.
Regarding claim 21, claim 7 of the reference patent teaches all the limitations of claim 21 as shown below except for the limitations that are struck-through.
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21. A random number generator comprising:
7. A random number generator comprising:
a plurality of cells configured
a systolic array configured to provide a random number output,
a physical unclonable function configured to provide input to the at least two-dimensional array; and
further comprising a memory configured for use as a physical unclonable function, wherein the physical unclonable function provides inputs to the systolic array
a shift register configured to
further comprising a shift register, wherein a clock signal is coupled to the shift register to control providing an address to the memory.
Claim 7 of the reference patent does not explicitly teach a plurality of cells configured in an at least two-dimensional array, each cell comprising an oscillator, wherein the at least two-dimensional array is arranged to provide a random number output; and a shift register configured to receive the random number output from the systolic array and to provide a feedback signal to the physical unclonable function for selecting the input.
However, on the same field of endeavor, Chuang discloses a random number generator comprising a plurality of cells configured in an at least two-dimensional array, each cell comprising an oscillator, wherein the at least two-dimensional array is arranged to provide a random number output (Chuang Fig. 1; col 2 lines 56-67).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the systolic array as a two-dimensional array in order to provide a more compact random number generator by reducing the length of wiring connections among the random number generator circuit components such as the feedback path (Chuang Fig. 1). Furthermore, configure each cell to include an oscillator in order to produce a high amount of randomness (Chuang col 2 lines 56-67).
Therefore, the combination of the reference patent as modified in view of Chuang teaches a plurality of cells configured in an at least two-dimensional array, each cell comprising an oscillator, wherein the at least two-dimensional array is arranged to provide a random number output.
Claim 7 of the reference patent does not explicitly teach a shift register configured to receive the random number output from the systolic array and to provide a feedback signal to the physical unclonable function for selecting the input.
However, on the same field of endeavor, VDS discloses a physical unclonable function; and a shift register configured to provide an address signal to the physical unclonable function for addressing the physical unclonable function (VDS Fig. 1a and paragraphs [0086, 0088, 0093] physical unclonable function – memory 110; shift register - address scrambler 140).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the reference patent and configure shift register to receive the random number output and to provide a feedback signal to address the memory selecting the input the array in order to reduce side channel leakage by scrambling the transfer of the content of the PUF (VDS paragraph [0017, 0024, 0028]).
Therefore, the combination of the reference patent as modified in view of Chuang and VDS teaches a shift register configured to receive the random number output from the systolic array and to provide a feedback signal to the physical unclonable function for selecting the input.
Regarding claim 22, claim 7 of the reference patent as modified in view of Chuang and VDS teaches all the limitations of claim 21 as stated above. Further, the reference patent as modified in view of Chuang and VDS teaches wherein the oscillator in each cell is a ring oscillator (Chuang Fig. 2 and col 3 lines 27-30).
Regarding claims 23-24 and 29, they are anticipated by claims 7, 7 and 7 respectively of the reference patent. Mapping for these claims are not being shown for the purpose of brevity.
Regarding claim 30, claim 7 of the reference patent as modified in view of Chuang and VDS teaches all the limitations of claim 21 as stated above. Further, the reference patent as modified in view of Chuang and VDS teaches wherein the shift register comprises a linear feedback shift register (VDS paragraph [0093]).
Claim 25 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 7 of U.S. Patent No. US 11,609,743 B2 (the reference patent) in view of Chuang, VDS and Maes.
Regarding claim 25, claim 7 of the reference patent as modified in view of Chuang and VDS teaches all the limitations of claim 21 as stated above.
Claim 7 of the reference patent does not explicitly teach wherein the physical unclonable function, as directed by the shift register, is used to seed the oscillators in the systolic array.
However, on the same field of endeavor, Maes discloses a physical unclonable function that is used to seed a random number generator (Maes paragraphs [0101, 0114-0115, 0117]).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the reference patent using and configure the physical unclonable function to seed the oscillators in the systolic array to further increase the randomness of the random number by using the PUF output to generate a seed for the systolic array (Maes paragraph [0096-0098]).
Therefore, the combination of the reference patent as modified in view of Chuang, VDS and Maes teaches wherein the physical unclonable function, as directed by the shift register, is used to seed the oscillators in the systolic array.
Claims 26-28 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 7 of U.S. Patent No. US 11,609,743 B2 (the reference patent) in view of Chuang, VDS and Carlson.
Regarding claim 26, claim 7 of the reference patent as modified in view of Salinger and Maes teaches all the limitations of claim 21 as stated above. Further, the reference patent as modified in view of Salinger and Maes teaches wherein each cell further comprises a flip-flop configured to (the reference patent claim 1).
The reference patent does not explicitly teach wherein each cell further comprises a flip-flop configured to receive an output from the oscillator.
However, on the same field of endeavor, Carlson discloses a random number generator that includes a flip-flop that receives an input signal from an oscillator and provides an input to an exclusive OR gate (Carlson Fig. 1 and paragraph [0019] flip-flop - sampling device 110A-110N; exclusive OR gate - 120).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify each cell to include a flip-flop in between the oscillator and the exclusive OR gate for synchronously sampling each oscillator output and latching the random bit generated by the corresponding oscillator (Carlson paragraph [0019]).
Therefore, the combination of the reference patent as modified in view of Salinger, Maes and Carlson teaches wherein each cell further comprises a flip-flop configured to receive an output from the oscillator and to provide an input to an exclusive OR gate.
Regarding claims 27-28, they are anticipated by claims 7 and 7 respectively of the reference patent. Mapping for these claims are not being shown for the purpose of brevity.
Claims 31-33 and 35-37 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 4 and 16 of U.S. Patent No. US 11,609,743 B2 (the reference patent) in view of Salinger and Maes.
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31. A system comprising:
4. A random number generator comprising:
a systolic array configured to receive a plurality of inputs, and to provide a random number output
a systolic array configured to provide a random number output, further comprising a memory configured for use as a physical unclonable function, wherein the physical unclonable function provides inputs to the systolic array
Claim 4 of the reference patent does not explicitly teach a plurality of cryptographic modules each configured to process packets, wherein the packet processing includes encrypting a packet based on a security key associated with the packet; and a systolic array configured to receive a plurality of inputs, and to provide a random number output to one or more of the plurality of cryptographic modules.
However, on the same field of endeavor, Salinger discloses a plurality of cryptographic modules each configured to process packets, wherein the packet processing includes encrypting a packet based on a security key associated with the packet (Salinger Fig. 2A-2B and paragraphs [0026, 0028-0032] plurality of cryptographic modules – 220; packets – content data packets; security key - encryption key).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the reference patent and include a plurality of cryptographic modules to receive the random number output and use the random number output to generate the encryption keys (Maes paragraphs [0113, 0115 and 0122]) used for encrypting the packets.
Therefore, the combination of the reference patent as modified in view of Salinger and Maes teaches a plurality of cryptographic modules each configured to process packets, wherein the packet processing includes encrypting a packet based on a security key associated with the packet; and a systolic array configured to receive a plurality of inputs, and to provide a random number output to one or more of the plurality of cryptographic modules.
Regarding claim 32, claim 4 of the reference patent as modified in view of Salinger and Maes teaches all the limitations of claim 31 as stated above. Further, the reference patent as modified in view of Salinger and Maes teaches further comprising: memory configured to provide the inputs to the systolic array, and further coupled to receive a signal (the reference patent claim 7).
However, on the same field of endeavor, VDS discloses a memory configured as a physical unclonable function; and a shift register configured to provide an address signal based on a random number output to the physical unclonable function for addressing the physical unclonable function (VDS Fig. 1a and paragraphs [0086, 0088, 0093] physical unclonable function – memory 110; shift register - address scrambler 140).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the reference patent and configure the shift register to receive the random number output and to provide a feedback signal to address the memory for selecting the input to the array in order to reduce side channel leakage by scrambling the transfer of the content of the PUF (VDS paragraph [0017, 0024, 0028]).
Therefore, the combination of the reference patent as modified in view of Chuang and VDS teaches further comprising: memory configured to provide the inputs to the systolic array, and further coupled to receive a signal based on the random number output, wherein the signal is used for selecting the inputs provided to the systolic array.
Regarding claim 33, claim 4 of the reference patent as modified in view of Salinger and Maes teaches all the limitations of claim 31 as stated above.
The reference patent does not explicitly teach further comprising: a first interface coupled to the plurality of cryptographic modules and configured to receive an incoming packet, associate a first security key with the incoming packet, select one of the plurality of cryptographic modules, and route the incoming packet to the selected cryptographic module.
However, on the same field of endeavor, Salinger discloses further comprising: a first interface coupled to the plurality of cryptographic modules and configured to receive an incoming packet, associate a first security key with the incoming packet, select one of the plurality of cryptographic modules, and route the incoming packet to the selected cryptographic module (Salinger Fig. 2A and paragraphs [0022-0024]; first interface – 204 and/or 206).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the reference patent and further include a first interface coupled to the plurality of cryptographic modules and configured to receive an incoming packet, associate a first security key with the incoming packet, select one of the plurality of cryptographic modules, and route the incoming packet to the selected cryptographic module in order to communicate with other devices over a larger network (Salinger paragraph [0020]).
Therefore, the combination of the reference patent as modified in view of Salinger and Maes teaches further comprising: a first interface coupled to the plurality of cryptographic modules and configured to receive an incoming packet, associate a first security key with the incoming packet, select one of the plurality of cryptographic modules, and route the incoming packet to the selected cryptographic module.
Regarding claim 35, it is anticipated by claim 7 of the reference patent. Mapping for the claim is not being shown for the purpose of brevity.
Regarding claim 36, claim 16 of the reference patent teaches all the limitations of claim 36 as shown below except for the limitations that are struck-through.
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36. A system comprising:
a random number generator comprising:
16. An apparatus configured to provide a random number output, the apparatus comprising:
a systolic array configured to provide a random number value, wherein the systolic array comprises a plurality of cells, and each cell comprises an oscillator;
a systolic array including a first cell and a second cell, wherein each cell further comprises an oscillator
Claim 16 of the reference patent does not explicitly teach a plurality of programmable cryptographic devices, each cryptographic device configured to receive the random number value; and at least one programmable input/output interface configured to route each of a plurality of incoming packets to one of the cryptographic devices for encryption.
However, on the same field of endeavor, Salinger discloses a plurality of programmable cryptographic devices (Salinger Fig. 2A-2B and paragraphs [0026, 0028-0032] plurality of cryptographic modules – 220); and at least one programmable input/output interface configured to route each of a plurality of incoming packets to one of the cryptographic devices for encryption (Salinger Fig. 2A and paragraphs [0022-0024]; at least one programmable input/output interface – 204 and/or 206).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the reference patent and configure the host processor to include a plurality of programmable cryptographic devices, each configured to receive the random number value and use the random number value to generate encryption keys (Maes paragraphs [0113, 0115 and 0122]). Further, include at least one programmable input/output interface configured to route each of a plurality of incoming packets to one of the cryptographic devices for encryption in order to communicate with other devices over a larger network (Salinger paragraph [0020]).
Therefore, the combination of the reference patent as modified in view of Salinger and Maes teaches a plurality of programmable cryptographic devices, each cryptographic device configured to receive the random number value; and at least one programmable input/output interface configured to route each of a plurality of incoming packets to one of the cryptographic devices for encryption.
Regarding claim 37, claim 16 of the reference patent as modified in view of Salinger and Maes teaches all the limitations of claim 36 as stated above. Further, the reference patent as modified in view of Salinger and Maes teaches wherein: the programmable input/output interface is programmable to support different interface protocols, and each of the plurality of cryptographic devices is programmable to support different encryption protocols (Salinger paragraphs [0015-0017, 0021, 0026, 0028, 0038, 0040, 0059]).
Claim 34 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 4 of U.S. Patent No. US 11,609,743 B2 (the reference patent) in view of Salinger and Maes as applied to claim 31 above, and further in view of Chuang.
Regarding claim 34, claim 4 of the reference patent as modified in view of Salinger and Maes teaches all the limitations of claim 36 as stated above. Further, the reference patent as modified in view of Salinger and Maes teaches wherein the systolic array comprises a plurality of cells, (the reference patent claim 1).
The reference patent does not explicitly teach wherein the systolic array comprises a plurality of cells, each cell including an oscillator.
However, on the same field of endeavor, Chuang discloses a random number generator comprising a plurality of cells, each cell comprising an oscillator (Chuang Fig. 1; col 2 lines 56-67).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify each cell to include an oscillator in order to produce a high amount of randomness (Chuang col 2 lines 56-67).
Therefore, the combination of the reference patent as modified in view of Chuang teaches wherein the systolic array comprises a plurality of cells, each cell including an oscillator.
Claim 38 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 16 of U.S. Patent No. US 11,609,743 B2 (the reference patent) in view of Salinger and Maes as applied to claim 36 above, and further in view of Leung.
Regarding claim 38, claim 16 of the reference patent as modified in view of Salinger and Maes teaches all the limitations of claim 36 as stated above.
Claim 16 of the reference patent does not explicitly teach wherein each of the plurality of programmable cryptographic devices comprises at least one of a programmable systolic packet input engine, a programmable systolic cryptographic engine, or a programmable systolic packet output engine.
However, on the same field of endeavor, Leung discloses a cryptographic devices comprising at least one of a programmable systolic packet input engine, a programmable systolic cryptographic engine, or a programmable systolic packet output engine (Leung Fig. 2 and paragraph [0026]).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify each programmable cryptographic device to include at least one of a programmable systolic packet input engine, a programmable systolic cryptographic engine, or a programmable systolic packet output engine in order to increase throughput encrypt functions because a systolic array allows multiple packets to be processed in a parallel manner (Leung paragraph [0026]).
Therefore, the combination of the reference patent as modified in view of Salinger, Maes and Leung teaches wherein each of the plurality of programmable cryptographic devices comprises at least one of a programmable systolic packet input engine, a programmable systolic cryptographic engine, or a programmable systolic packet output engine.
Claims 39-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 16 of U.S. Patent No. US 11,609,743 B2 (the reference patent) in view of Salinger and Maes applied to claim 36 above, and further in view of Carlson.
Regarding claim 39, claim 16 of the reference patent as modified in view of Salinger and Maes teaches all the limitations of claim 36 as stated above.
Claim 16 of the reference patent does not explicitly teach wherein the oscillator is a free-running asynchronous oscillator.
However, on the same field of endeavor, Carlson discloses a random number generator that includes a free-running asynchronous oscillator (Carlson Figs. 1-2 and paragraphs [0008, 0024-0025]).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the oscillator in each cell as a free-running asynchronous oscillator in order to reduce power consumption as the oscillator design uses small size transistors (Carlson paragraph [0024]).
Therefore, the combination of the reference patent as modified in view of Salinger, Maes and Carlson teaches wherein the oscillator is a free-running asynchronous oscillator.
Regarding claim 40, it is anticipated by claim 16 of the reference patent. Mapping for the claim is not being shown for the purpose of brevity.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 31, 33-34, 36-37 and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Salinger in view of Chuang and Maes.
Regarding claim 31, Salinger teaches a system comprising:
a plurality of cryptographic modules each configured to process packets, wherein the packet processing includes encrypting a packet based on a security key associated with the packet (Salinger Fig. 2A-2B and paragraphs [0026, 0028-0032] plurality of cryptographic modules – 220; packets – content data packets; security key - encryption key);
.
Salinger does not explicitly teach a systolic array configured to receive a plurality of inputs, and to provide a random number output to one or more of the plurality of cryptographic modules.
However, on the same field of endeavor, Chuang discloses a systolic array configured to receive a plurality of inputs, and to provide a random number output (Chuang Fig. 1 and col 2 lines 29-55; systolic array – eight stage LFSR; plurality of inputs – input to each flip-flops 10-17; random number output – output 26).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Salinger using Chuang and configure the system to include a systolic array configured to receive a plurality of inputs, and to provide a random number output to one or more of the plurality of cryptographic modules such that the random number output can be used to generate the encryption keys (Maes paragraphs [0113, 0115 and 0122]).
Therefore, the combination of Salinger, Chuang and Maes teaches a system comprising: a plurality of cryptographic modules each configured to process packets, wherein the packet processing includes encrypting a packet based on a security key associated with the packet; and a systolic array configured to receive a plurality of inputs, and to provide a random number output to one or more of the plurality of cryptographic modules.
Regarding claim 33, Salinger as modified in view of Chuang and Maes teaches all the limitations of claim 31 as stated above. Further Salinger as modified in view of Chuang and Maes teaches further comprising: a first interface coupled to the plurality of cryptographic modules and configured to receive an incoming packet, associate a first security key with the incoming packet, select one of the plurality of cryptographic modules, and route the incoming packet to the selected cryptographic module (Salinger Fig. 2A and paragraphs [0022-0024]; first interface – switch 206).
Regarding claim 34, Salinger as modified in view of Chuang and Maes teaches all the limitations of claim 31 as stated above. Further Salinger as modified in view of Chuang and Maes teaches wherein the systolic array comprises a plurality of cells, each cell including an oscillator (Chuang Fig. 1 and col 2 lines 56-59; plurality of cells – oscillator/XOR/flip-flop circuit pairs).
Regarding claim 36, Salinger teaches a system comprising:
;
a plurality of programmable cryptographic devices, (Salinger Fig. 2A-2B and paragraphs [0026, 0028-0032] plurality of cryptographic modules – 220); and
at least one programmable input/output interface configured to route each of a plurality of incoming packets to one of the cryptographic devices for encryption (Salinger Fig. 2A and paragraphs [0022-0024]; at least one programmable input/output interface – network cards 204 and/or switch 206; packets – content data packets).
Salinger does not explicitly teach a random number generator comprising: a systolic array configured to provide a random number value, wherein the systolic array comprises a plurality of cells, and each cell comprises an oscillator; and a plurality of programmable cryptographic devices, each cryptographic device configured to receive the random number value.
However, on the same field of endeavor, Chuang discloses a random number generator comprising: a systolic array configured to provide a random number value, wherein the systolic array comprises a plurality of cells, and each cell comprises an oscillator (Chuang Fig. 1 and col 2 lines 29-59; random number generator - Fig. 1; systolic array – eight stage LFSR; random number value – output 26; plurality of cells – oscillator/XOR circuit pairs).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Salinger using Chuang and configure the system to include a random number generator comprising: a systolic array configured to provide a random number value, wherein the systolic array comprises a plurality of cells, and each cell comprises an oscillator; and provide the random number value to each cryptographic device such that the random number value can be used to generate the encryption keys (Maes paragraphs [0113, 0115 and 0122]).
Therefore, the combination of Salinger, Chuang and Maes teaches a system comprising: a random number generator comprising: a systolic array configured to provide a random number value, wherein the systolic array comprises a plurality of cells, and each cell comprises an oscillator; a plurality of programmable cryptographic devices, each cryptographic device configured to receive the random number value; and at least one programmable input/output interface configured to route each of a plurality of incoming packets to one of the cryptographic devices for encryption.
Regarding claim 37, Salinger as modified in view of Chuang and Maes teaches all the limitations of claim 36 as stated above. Further Salinger as modified in view of Chuang and Maes teaches wherein: the programmable input/output interface is programmable to support different interface protocols, and each of the plurality of cryptographic devices is programmable to support different encryption protocols (Salinger paragraphs [0015-0017, 0021, 0026, 0028, 0038, 0040, 0059]).
Regarding claim 39, Salinger as modified in view of Chuang and Maes teaches all the limitations of claim 36 as stated above. Further Salinger as modified in view of Chuang and Maes teaches wherein the oscillator is a free-running asynchronous oscillator (Chuang Fig. 2 and col 3 lines 28-39).
Claim 38 is rejected under 35 U.S.C. 103 as being unpatentable over Salinger in view of Chuang and Maes as applied to claim 36 above, and further in view of Leung et al. (US 20070195951 A1), hereinafter Leung.
Regarding claim 38, Salinger as modified in view of Chuang and Maes teaches all the limitations of claim 36 as stated above.
Salinger does not explicitly teach wherein each of the plurality of programmable cryptographic devices comprises at least one of a programmable systolic packet input engine, a programmable systolic cryptographic engine, or a programmable systolic packet output engine.
However, on the same field of endeavor, Leung discloses a cryptographic devices comprising at least one of a programmable systolic packet input engine, a programmable systolic cryptographic engine, or a programmable systolic packet output engine (Leung Fig. 2 and paragraph [0026]).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify each programmable cryptographic device to include at least one of a programmable systolic packet input engine, a programmable systolic cryptographic engine, or a programmable systolic packet output engine in order to increase throughput encrypt functions because a systolic array allows multiple packets to be processed in a parallel manner (Leung paragraph [0026]).
Therefore, the combination of Salinger, Chuang, Maes and Leung teaches wherein each of the plurality of programmable cryptographic devices comprises at least one of a programmable systolic packet input engine, a programmable systolic cryptographic engine, or a programmable systolic packet output engine.
Claim 40 is rejected under 35 U.S.C. 103 as being unpatentable over Salinger in view of Chuang and Maes as applied to claim 39 above, and further in view of Carlson et al. (US 20050055391 A1), hereinafter Carlson.
Regarding claim 40, Salinger as modified in view of Chuang and Maes teaches all the limitations of claim 39 as stated above. Further Salinger as modified in view of Chuang and Maes teaches wherein each cell further comprises a flip-flop that receives an input signal (Chuang Fig. 2; flip-flop – flip flops 10-17).
Salinger does not explicitly teach wherein each cell further comprises a flip-flop that receives an input signal from the oscillator.
However, on the same field of endeavor, Carlson discloses a random number generator that includes a flip-flop that receives an input signal from an oscillator (Carlson Fig. 1 and paragraph [0019]] flip-flop - sampling device 110A-110N).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify each cell of Chuang to include a flip-flop in between the oscillator and the XOR gate for synchronously sampling each oscillator output and latching the random bit generated by the corresponding oscillator (Carlson paragraph [0019]).
Therefore, the combination of Salinger, Chuang, Maes and Carlson teaches wherein each cell further comprises a flip-flop that receives an input signal from the oscillator.
Allowable Subject Matter
Claims 21-30 would be allowable if rewritten to overcome the 35 U.S.C. 112(b) and nonstatutory double patenting rejections discussed above.
Claims 32 and 35 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if rewritten to overcome the 35 U.S.C. 112(b) and nonstatutory double patenting rejections discussed above.
The following is a statement of reasons for the indication of allowable subject matter:
The reasons for the indication of allowable subject matter are the same reasons provided in the notice of allowance for the parent application (15450531) submitted on 04/05/2018.
Conclusion
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/Carlo Waje/Examiner, Art Unit 2151 (571)272-5767
