DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in Korean Patent Application No. 10-2022-0057076, filed on 5/10/2022.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 2/14/2023, 1/11/2024, and 12/8/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Election/Restriction
It has been acknowledged that the applicant has elected without traverse Invention (Species 11) per the response dated on 12/27/2024. None of the claims has been canceled by the Applicant, and therefore, currently claims 1-20 are present for examination.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The title of the invention has been suggested as, “SEMICONDUCTOR DEVICE COMPRISING A LOWER NANOSHEET STACK, AN UPPER NANOSHEET STACK AND AN ISOLATION LAYER BETWEEN THE LOWER AND UPPER NANOSHEET STACKS, WHEREIN SIDEWALLS OF THE ISOLATION LAYER HAS A CURVED SHAPE”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-11, 18, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin (US 2023/0307456 A1).
Regarding claim 1, Lin teaches a semiconductor device (integrated circuit 100, Figs. 3B, [0114]) comprising:
an active pattern (semiconductor layer 133, Figs. 3B (see Figs. 1D for the label and three-dimensional illustration), [0064]) on a substrate (substrate 101, Figs. 3B (see Figs. 1D for the label and three-dimensional illustration), [0064]) and extending in a first direction (X direction, Figs. 1D and 3B);
a plurality of lower nanosheets (semiconductor nanostructures 107, Fig. 3B, [0064]) spaced apart from each other in a second direction (Z direction, Figs. 3B) intersecting the first direction (X direction, Fig. 3B) and on the active pattern (semiconductor layer 133, Figs. 3B (see Figs. 1D for the label and three-dimensional illustration));
an isolation layer (dielectric layer 129, Fig. 3B, [0086]) on the plurality of lower nanosheets (semiconductor nanostructures 107, Fig. 3B) and spaced apart from the plurality of lower nanosheets (semiconductor nanostructures 107, Fig. 3B) in the second direction (Z direction, Fig. 3B);
a plurality of upper nanosheets (semiconductor nanostructures 106, Fig. 3B, [0064]) spaced apart from each other in the second direction (Z direction, Fig. 3B) and on the isolation layer (dielectric layer 129, Fig. 3B); and
a gate electrode (comprising gate metal 112 and gate metal 113, Fig. 3B, [0064] and [0122]: “… second gate metal surrounding the second semiconductor nanostructure and in contact with the first gate metal at a position lateral from the dielectric layer.”, and therefore, gate metal 112 and gate metal 113 form a gate electrode) on the substrate (substrate 101, Figs. 3B (see Figs. 1D for the label and three-dimensional illustration)) and surrounding each of the plurality of lower nanosheets (semiconductor nanostructures 107, Fig. 3B), the isolation layer (dielectric layer 129, Fig. 3B), and the plurality of upper nanosheets (semiconductor nanostructures 106, Fig. 3B),
wherein a sidewall of the isolation layer (dielectric layer 129, Fig. 3B) has a curved shape (Fig. 3B, [0089]: “the dielectric layer 129 may include concave sidewalls”).
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Regarding claim 2, Lin teaches the semiconductor device of claim 1, wherein a width (see width W in Illustrative Fig. 1, which is an annotated version of Fig. 3B) of the isolation layer (dielectric layer 129, Illustrative Fig. 1) decreases when moving in the second direction (Z direction, Illustrative Fig. 1) toward a point (point P, Illustrative Fig. 1) located halfway between a stack of the plurality of lower nanosheets (semiconductor nanostructures 107, Illustrative Fig. 1) and a stack of the plurality of upper nanosheets (semiconductor nanostructures 106, Illustrative Fig. 1, [0089]: “the dielectric layer 129 may include concave sidewalls”, and therefore the width of the isolation layer 129 along the X direction decreases when moving in the Z direction toward a point located halfway between a stack of the plurality of lower and a stack of the plurality of upper nanosheets).
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Regarding claim 3, Lin teaches the semiconductor device of claim 1, wherein a width (see width W in Illustrative Fig. 2 which is an annotated version of Fig. 1D) of the isolation layer (dielectric layer 129 shown as the isolation structure 126, Illustrative Fig. 2) increases when moving in the second direction (Z direction, Illustrative Fig. 2) toward a point located halfway between a stack of the plurality of lower nanosheets (semiconductor nanostructures 107, Illustrative Fig. 2) and a stack of the plurality of upper nanosheets (semiconductor nanostructures 106, Illustrative Fig. 2: the width is smallest on the top and bottom surfaces of the isolation structure 126 because of round corners).
Regarding claim 4, Lin teaches the semiconductor device of claim 1, wherein an inclination angle (angle α, Illustrative Fig. 1) of the sidewall of the isolation layer (dielectric layer 129, Illustrative Fig. 1), with respect to a top face (top face, Illustrative Fig. 1) of the isolation layer (dielectric layer 129, Illustrative Fig. 1), continuously decreases as the isolation layer (dielectric layer 129, Illustrative Fig. 1) extends in the second direction (Z direction, Illustrative Fig. 1) from an area adjacent to the plurality of upper nanosheets (semiconductor nanostructures 106, Illustrative Fig. 1) to an area adjacent to the plurality of lower nanosheets (semiconductor nanostructures 107, Illustrative Fig. 1).
Regarding claim 5, Lin teaches the semiconductor device of claim 1, wherein an inclination angle (angle β, Illustrative Fig. 1) of the sidewall of the isolation layer (dielectric layer 129, Illustrative Fig. 1), with respect to a top face (top face, Illustrative Fig. 1) of the isolation layer (dielectric layer 129, Illustrative Fig. 1), continuously increases as the isolation layer (dielectric layer 129, Illustrative Fig. 1) extends in the second direction (Z direction, Illustrative Fig. 1) from an area adjacent to the plurality of upper nanosheets (semiconductor nanostructures 106, Illustrative Fig. 1) to an area adjacent to the plurality of lower nanosheets (semiconductor nanostructures 107, Illustrative Fig. 1).
Regarding claim 6, Lin teaches the semiconductor device of claim 1, wherein the sidewall of the isolation layer (dielectric layer 129, Fig. 3B) has a concave shape (Fig. 3B, [0089]: “the dielectric layer 129 may include concave sidewalls”).
Regarding claim 7, Lin teaches the semiconductor device of claim 1, wherein the sidewall of the isolation layer (dielectric layer 129, Fig. 3B) has a convex shape (Fig. 3B: when viewed from inside the isolation layer towards the outside the isolation layer, the sidewall has a convex shape.).
Regarding claim 8, Lin teaches the semiconductor device of claim 1, further comprising:
a lower source/drain region (source/drain region 117, Fig. 3B, [0037]) on the active pattern (semiconductor layer 133, Figs. 3B) and sidewalls of the plurality of lower nanosheets (semiconductor nanostructures 107, Fig. 3B); and
an upper source/drain region (source/drain region 116, Fig. 3B, [0037]) on sidewalls of the plurality of upper nanosheets (semiconductor nanostructures 106, Fig. 3B) and spaced apart from the lower source/drain region (source/drain region 117, Fig. 3B) in the second direction (Z direction, Fig. 3B),
wherein each of the lower source/drain region (source/drain region 117, Fig. 3B) and the upper source/drain region (source/drain region 116, Fig. 3B) does not contact the isolation layer (dielectric layer 129, Fig. 3B).
Regarding claim 9, Lin teaches the semiconductor device of claim 8, wherein the plurality of lower nanosheets (source/drain region 117, Fig. 3B) and the gate electrode (gate metal 113 as part of the gate electrode, Fig. 3B) are alternately stacked with each other to constitute a lower structure (transistor 105, Fig. 3B, [0030]),
wherein the plurality of upper nanosheets (semiconductor nanostructures 106, Fig. 3B) and the gate electrode (gate metal 112 as part of the gate electrode, Fig. 3B) are alternately stacked with each other to constitute an upper structure (transistor 104, Fig. 3B, [0030]), and
wherein a thickness of the lower structure (semiconductor nanostructures 107, Fig. 3B) in the second direction (Z direction, Fig. 3B) is different from a thickness of the upper structure (semiconductor nanostructures 106, Fig. 3B) in the second direction (Z direction, Fig. 3B: the lower structure (comprising four gate layers) is thicker than the upper structure (comprising three gate layers)).
Regarding claim 10, Lin teaches the semiconductor device of claim 1, further comprising a source/drain region (source/drain region 116, Fig. 3B, [0037]) on the active pattern (semiconductor layer 133, Figs. 3B) and sidewalls of the plurality of upper nanosheets (semiconductor nanostructures 106, Fig. 3B).
Regarding claim 11, Lin teaches the semiconductor device of claim 10, wherein the active pattern (semiconductor layer 133, Figs. 3B (see Figs. 1D for the label and three-dimensional illustration), [0064]) constitutes a lower structure (the portion of the semiconductor layer 133 protruding on the surface of the substrate 101, Fig. 1D),
wherein the plurality of upper nanosheets (semiconductor nanostructures 107, Fig. 1D) and the gate electrode (comprising gate metal 112 and gate metal 113, Fig. 1D) are alternately stacked with each other to constitute an upper structure (transistor 104, Fig. 1D, [0030]), and
wherein a thickness (height of the structures in the Z direction) of the lower structure (the portion of the semiconductor layer 133 protruding on the surface of the substrate 101, Fig. 1D) in the second direction (Z direction, Fig. 1D) is different from a thickness of the upper structure (transistor 104, Fig. 1D) in the second direction (Z direction, Fig. 1D).
Regarding claim 18, Lin teaches a semiconductor device (integrated circuit 100, Figs. 3B, [0114]) comprising:
a substrate (substrate 101, Figs. 3B (see Figs. 1D for the label and three-dimensional illustration), [0064]);
an active pattern (semiconductor layer 133, Figs. 3B (see Figs. 1D for the label and three-dimensional illustration), [0064]) on the substrate (substrate 101, Figs. 1D and 3B) and extending in a first horizontal direction (X direction, Figs. 1D and 3B), wherein the active pattern (semiconductor layer 133, Figs. 1D and 3B) protrudes from the substrate (substrate 101, Figs. 1D and 3B) in a vertical direction (Z direction, Figs. 1D and 3B);
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a first plurality of lower nanosheets (semiconductor nanostructures 107 shown as first plurality of lower nanosheets in Illustrative Fig. 3, which is an annotated version of Figs. 1D and 3B, [0064]) spaced apart from each other in the vertical direction (Z direction, Illustrative Fig. 3) and on the active pattern (semiconductor layer 133, Illustrative Fig. 3);
a second plurality of lower nanosheets (semiconductor nanostructures 107 shown as second plurality of lower nanosheets in Illustrative Fig. 3, which is an annotated version of Figs. 1D and 3B, [0064]) spaced apart from each other in the vertical direction (Z direction, Illustrative Fig. 3) and on the active pattern (semiconductor layer 133, Illustrative Fig. 3), wherein the first plurality of lower nanosheets (first plurality of lower nanosheets, Illustrative Fig. 3) are spaced apart from the second plurality of lower nanosheets (second plurality of lower nanosheets, Illustrative Fig. 3) in the first horizontal direction (X direction, Illustrative Fig. 3);
a first plurality of upper nanosheets (semiconductor nanostructures 106 shown as first plurality of upper nanosheets in Illustrative Fig. 3, [0064]) spaced apart from each other in the vertical direction (Z direction, Illustrative Fig. 3) and on the first plurality of lower nanosheets (first plurality of lower nanosheets, Illustrative Fig. 3), wherein the first plurality of upper nanosheets (first plurality of upper nanosheets, Illustrative Fig. 3) are spaced apart from the first plurality of lower nanosheets (first plurality of lower nanosheets, Illustrative Fig. 3) in the vertical direction (Z direction, Illustrative Fig. 3);
a second plurality of upper nanosheets (semiconductor nanostructures 106 shown as second plurality of upper nanosheets in Illustrative Fig. 3) spaced apart from each other in the vertical direction (Z direction, Illustrative Fig. 3) and on the second plurality of lower nanosheets (second plurality of lower nanosheets, Illustrative Fig. 3), wherein the second plurality of upper nanosheets (second plurality of upper nanosheets, Illustrative Fig. 3) are spaced apart from the second plurality of lower nanosheets (second plurality of lower nanosheets, Illustrative Fig. 3) in the vertical direction (Z direction, Illustrative Fig. 3);
a first isolation layer (dielectric layer 129 shown as first isolation layer in Illustrative Fig. 3, [0086]) between the first plurality of lower nanosheets (first plurality of lower nanosheets, Illustrative Fig. 3) and the first plurality of upper nanosheets (first plurality of upper nanosheets, Illustrative Fig. 3);
a second isolation layer (dielectric layer 129 shown as second isolation layer in Illustrative Fig. 3, [0086]) between the second plurality of lower nanosheets (second plurality of lower nanosheets, Illustrative Fig. 3) and the second plurality of upper nanosheets (second plurality of upper nanosheets, Illustrative Fig. 3), wherein the first isolation layer (first isolation layer, Illustrative Fig. 3) and the second isolation layer (second isolation layer, Illustrative Fig. 3) are spaced apart from each other in the first horizontal direction (X direction, Illustrative Fig. 3);
a first gate electrode (comprising gate metal 112 and gate metal 113 shown as first gate electrode in Illustrative Fig. 3, [0064]) on the active pattern (semiconductor layer 133, Illustrative Fig. 3) and extending in a second horizontal direction (Y direction, Illustrative Fig. 3) different from the first horizontal direction (X direction, Illustrative Fig. 3), wherein the first gate electrode (first gate electrode, Illustrative Fig. 3) surrounds each of the first plurality of lower nanosheets (first plurality of lower nanosheets, Illustrative Fig. 3), the first isolation layer (first isolation layer, Illustrative Fig. 3), and the first plurality of upper nanosheets (first plurality of upper nanosheets, Illustrative Fig. 3); and
a second gate electrode (comprising gate metal 112 and gate metal 113 shown as second gate electrode in Illustrative Fig. 3, [0064]) on the active pattern and extending in the second horizontal direction, wherein the second gate electrode is spaced apart from the first gate electrode in the first horizontal direction, wherein the second gate electrode surrounds each of the second plurality of lower nanosheets (second plurality of lower nanosheets, Illustrative Fig. 3), the second isolation layer (second isolation layer, Illustrative Fig. 3), and the second plurality of upper nanosheets (second plurality of upper nanosheets, Illustrative Fig. 3),
wherein an inclination angle (the inclination angle of first sidewall at the top surface of the first isolation layer, Illustrative Fig. 3) of a sidewall (first sidewall, Illustrative Fig. 3) of the first isolation layer (first isolation layer, Illustrative Fig. 3) is different from an inclination angle (the inclination angle of second sidewall at the middle of the second isolation layer, Illustrative Fig. 3) of a sidewall (second sidewall, Illustrative Fig. 3) of the second isolation layer (second isolation layer, Illustrative Fig. 3).
Regarding claim 20, Lin teaches the semiconductor device of claim 18, wherein the first isolation layer (first isolation layer, Illustrative Fig. 3) has a largest width (width in the X direction, Illustrative Fig. 3) at a first vertical level (at the level of the bottom surface of the first isolation layer, Illustrative Fig. 3) thereof closest to a stack of the first plurality of lower nanosheets (first plurality of lower nanosheets, Illustrative Fig. 3) and/or at a second vertical level thereof closest to a stack of the first plurality of upper nanosheets, and
wherein the second isolation layer (second isolation layer, Illustrative Fig. 3) has a smallest width (width in the Y direction as seen in Fig. 1D portion of Illustrative Fig. 3) at a third vertical level (at the level of the bottom surface of the first isolation layer which is seen as isolation layer 126, Illustrative Fig. 3) thereof closest to a stack of the second plurality of lower nanosheets (first plurality of lower nanosheets, Illustrative Fig. 3) and/or at a fourth vertical level thereof closest to a stack of the second plurality of upper nanosheets.
Claims 12-17 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Lilak (US 2020/0266218 A1).
Regarding claim 12, Lilak teaches a semiconductor device (IC structure 100, Figs. 18, [0048]: “FIG. 18 is a depiction of the IC structure 100 of FIG. 1 (sharing the perspective of FIG. 1A) that includes some of the rounding and tapering that is likely to occur when the IC structure 100 is practically manufactured.”, and therefore, the IC structure in Figs. 1A and 1B will be also referred below when required) comprising:
an active pattern (base of the fins 146, Figs. 3A-B corresponding the processing steps of the IC structure 100 of Fig. 18, [0033]) on a substrate (base 102, Figs. 3A-B and 18 [0019]) and extending in a first horizontal direction (left-right in Figs. 1B and 3B);
a plurality of lower nanosheets (channel material 106-1, Fig. 18, [0020]) spaced apart from each other in a vertical direction (vertical direction in Fig. 18) from the substrate (base 102, Fig. 18) and on the active pattern (base on the fins 146, Figs. 3A-B and 18);
an isolation layer (dielectric material 108, Figs. 1A-B and 18, [0026]) on the plurality of lower nanosheets (channel material 106-1, Figs. 1A-b and 18) and spaced apart from the plurality of lower nanosheets (channel material 106-1, Figs. 1A-b and 18) in the vertical direction (vertical direction in Figs. 1A-B and 18);
a plurality of upper nanosheets (channel material 106-2, Figs. 1A-B and 18, [0020]) spaced apart from each other in the vertical direction (vertical direction in Figs. 1A-B and 18) and on the isolation layer (dielectric material 108, Figs. 1A-B and 18); and
a gate electrode (comprising gate metal 124-1 and gate metal 124-2, Figs. 1A-B and 18, [0024]) on the substrate (base 102, Figs. 1A-B and 18) and extending in a second horizontal direction (left-right direction in Figs. 1A and 18 and into the page in Fig. 1B, [0020]) intersecting the first horizontal direction (left-right in Fig. 1B), wherein the gate electrode (comprising gate metal 124-1 and gate metal 124-2, Figs. 1A-B and 18) surrounds each of the plurality of lower nanosheets (channel material 106-1, Figs. 1A-B and 18), the isolation layer (dielectric material 108, Figs. 1A-B and 18), and the plurality of upper nanosheets (channel material 106-2, Figs. 1A-B and 18),
wherein a width of the isolation layer (the width of the isolation layer 108 in Fig. 18) in the second horizontal direction (left-right direction in Figs. 1A and 18 and into the page in Fig. 1B) is the smallest (smallest) or largest at a first vertical level thereof closest to a stack of the plurality of lower nanosheets and/or at a second vertical level (the vertical level aligned with the top surface of the dielectric layer 108 in Fig. 18) thereof closest to a stack of the plurality of upper nanosheets (channel material 106-2, Figs. 1A-B and 18).
Regarding claim 13, Lilak teaches the semiconductor device of claim 12, wherein the width of the isolation layer (the width of the isolation layer 108 in Fig. 18) decreases when moving in the vertical direction (in the vertical direction starting from the bottom surface of the dielectric layer 108 and moving towards the top surface of the dielectric layer 108, Fig. 18) toward a point located halfway between the stack of the plurality of lower nanosheets (channel material 106-1, Fig. 18) and the stack of the plurality of upper nanosheets (channel material 106-2, Fig. 18).
Regarding claim 14, Lilak teaches the semiconductor device of claim 12, wherein the width of the isolation layer (the width of the isolation layer 108 in Fig. 18) increases when moving in the vertical direction (in the vertical direction starting from the top surface of the dielectric layer 108 and moving towards the bottom surface of the dielectric layer 108, Fig. 18) toward a point located halfway between the stack of the plurality of lower nanosheets (channel material 106-1, Fig. 18) and the stack of the plurality of upper nanosheets (channel material 106-2, Fig. 18).
Regarding claim 15, Lilak teaches the semiconductor device of claim 12, further comprising:
a lower source/drain region (S/D material 118-1, Fig. 1B, [0021]) on the active pattern (base of the fins 146, Figs. 3A-B corresponding the processing steps of the IC structure 100 of Fig. 18) and on sidewalls of the plurality of lower nanosheets (channel material 106-1, Fig. 1B); and
an upper source/drain region (S/D material 118-2, Fig. 1B, [0021]) on sidewalls of the plurality of upper nanosheets (channel material 106-2, Fig. 1A) and spaced apart from the lower source/drain region (S/D material 118-1, Fig. 1B) in the vertical direction (vertical direction in Fig. 1B).
Regarding claim 16, Lilak teaches the semiconductor device of claim 12, further comprising:
a source/drain region (S/D material 118-2, Fig. 1B, [0021]) on the active pattern (base of the fins 146, Figs. 3A-B corresponding the processing steps of the IC structure 100 of Fig. 18) and on sidewalls of the plurality of upper nanosheets (S/D material 118-2, Fig. 1B); and
an insulating layer (S/D material 118-2, Fig. 1B, [0021]) interposed between the source/drain region (S/D material 118-2, Fig. 1B) and the active pattern (base of the fins 146, Figs. 3A-B corresponding the processing steps of the IC structure 100 of Fig. 18).
Regarding claim 17, Lilak teaches the semiconductor device of claim 12, further comprising a gate insulating film (gate dielectric 122, Figs. 1A-B and 18) between the gate electrode (comprising gate metal 124-1 and gate metal 124-2, Figs. 1A-B and 18) and the plurality of lower nanosheets (channel material 106-1, Figs. 1A-B and 18), between the gate electrode and the plurality of upper nanosheets (channel material 106-2, Figs. 1A-B and 18), and between the gate electrode (comprising gate metal 124-1 and gate metal 124-2, Figs. 1A-B and 18) and the isolation layer (dielectric material 108, Figs. 1A-B and 18).
Allowable Subject Matter
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 19, disclosing: “the sidewall of the first isolation layer has a concave shape, and … the sidewall of the second isolation layer has a convex shape”, would be allowable if the corresponding shapes of the sidewall of the first isolation layer and the sidewall of the second isolation layer are incorporated with independent claim 18 or disclosed in a claim in an independent form.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Smith (US 20190172828 A1) teaches a semiconductor device comprising a plurality of lower nanosheets and a plurality of upper nanosheets separated by an isolation layer, which is relevant to all claims.
Thomas (US 2023/0037957 A1) teaches a semiconductor device comprising a plurality of lower nanosheets and a plurality of upper nanosheets separated by an isolation layer, which is relevant to all claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812