DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Final Action
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Response to Arguments
Applicant's arguments filed 11/14/2025 have been fully considered but they are not persuasive.
Applicant argues:
Argument 1: Applicant submits that “First, in contrast to Examiner's interpretation, the circuit of Panseri (see annotated Fig. 8 of Panseri) does NOT include a 3-stacked amplifier. While the circuit may present a visual appearance of three transistors per module, the transistors designated "Mpsw" and "Mnsw" serve actually as power-down/up switches-they do not perform any amplifying functions.”
Argument 2: Applicant submits that “ Second, a person skilled in the art will also not be able to extend Koroglu's circuit to a 3-stacked (or higher-stacked) RF power amplifier configuration without creative work. Adding more stacked transistor for RF power amplifiers is not straightforward. There are a lot of challenges and trade-offs. For example, a key technical barrier to such scaling stems from inherent impedance and signal swing dynamics in RF amplifier design”.
Examiner respectfully disagrees all of the allegations as argued. Examiner, in his previous office action, gave detail explanation of claimed limitation and pointed out exact locations in the cited prior art.
Examiner is entitled to give claim limitations their broadest reasonable interpretation in light of the specification.
Interpretation of Claims-Broadest Reasonable Interpretation During patent examination, the pending claims must be ‘given the broadest reasonable interpretation consistent with the specification.’ Applicant always has the opportunity to amend the claims during prosecution and broad interpretation by the examiner reduces the possibility that the claim, once issued, will be interpreted more broadly than is justified.
In response to applicant's argument, examiner respectfully submits that:
With respect to the argument 1, the examiner respectfully disagrees.
The reference (US 20210126587 A1) of Panseri does disclose an amplifier circuit that includes amplifier PA 20 of Fig. 1 and where Fig. 8 discloses PA 20 includes PA slice 20A, paragraph [0069] which states “the PA slice 20A includes a stack of p-type MOSFETs coupled to a stack of n-type MOSFETs. The node between the two stacks provides the PA output signal, Out. The p-type stack includes transistors Mpsw, Mp, and Mpcasc (cascode transistor) coupled in series. Similarly, the n-type stack includes transistors Mnsw, Mn, and Mncasc (cascode transistor) coupled in series”. Thus, it is clearly that Panseri does disclose the amplifier circuit which includes stack of transistors as shown in Fig. 8, transistors Mpsw , MP and MPcasc and Mnw, Mn and Mncasc, Paragraph [0067-0069] which discloses amplifier PA 20, where the amplifier PA 20 would perform amplifying function.
With respect to the argument 2:
With respect to the argument 1, the examiner respectfully disagrees.
Koroglu and Panseri are analogous art because they are from the same field of endeavor, power amplifier.
Fig. 6 of Koroglu discloses an amplifier circuit comprising differential portions 610n, 610p wherein each differential portion includes transistors M2p and M4p and transistors M3P and M1P are configured in stack and similarly for transistors M2n, M4n and M3n, M1n. Since Panseri does disclose commonly well-known in the art where transistor stack includes three transistors and Since Panseri further discloses in paragraphs [0035] and [0038], efficiency improvement. Therefore, it would have been obvious to one having ordinary skill in the art to have modified the reference of Koroglu with the teaching of Panseri.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5 & 7 are rejected under 35 U.S.C. 103 as being unpatentable over Koroglu (US 10,110,177 B1, of record) in view of Panseri et al. (US 2021/0126587 A1, of record), hereinafter called “Panseri”.
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Annotated Fig. 6 of Koroglu for ease reference.
Regarding claim 1, Koroglu (annotated Fig. 6) discloses main amplification circuit (Fig. 6), applied to an RF power amplifier (differential power amplifier having differential portions 610n, 610.p), wherein the main amplification circuit comprises:
two PMOS amplification modules (PMOS1 includes transistors M2p , M4p and second PMOS2 includes transistors M2n, M4n) and
two NMOS amplification modules (NMOS1 includes transistors M1p, M3p and second NMOS2 includes M1n , M3n),
wherein each PMOS amplification module (PMOS1, PMOS2) comprises a common-source-common-gate (CSCG) structure formed by a stack of K PMOS transistors (as seen Fig. 6, each PMOS1, PMOS2 included two transistors), and each NMOS transistor amplification module (NMOS1, NMOS2) comprises a CSCG structure formed by a stack of K NMOS transistors (as seen from Fig. 6, each NMOS1, NMOS2 included two transistors),
wherein a first PMOS amplification module (PMOS1) and a first NMOS amplification module (NMOS1) are connected in series between a supply voltage (VDD) and ground (ground / VSS); and
wherein a gate of a main amplification transistor (gate of transistor M2p) of the first PMOS amplification module (PMOS1) and a gate of a main amplification transistor(M1p) of the first NMOS amplification module (NMOS1) are connected to a non-inverting input (node 605p) of the main amplification circuit, and
a connection node (annotated, N1) of the first PMOS amplification module (PMOS1) and the first NMOS amplification module (NMOS1) is connected to an inverting output (e.g., node 623) of the main amplification circuit;
wherein a second PMOS amplification module (PMOS2 includes transistors M2n and M4n) and a second NMOS amplification module (NMO2) are connected in series between the supply voltage (VDD) and ground (ground / VSS); wherein a gate of a main amplification transistor (M2n) of the second PMOS amplification module (PMOS2) and a gate of a main amplification transistor (transistor M1n) of the second NMOS amplification module (NMOS2) are connected to an inverting input (605n) of the main amplification circuit;
wherein a connection node (annotated N2) of the second PMOS amplification module (PMOS2) and the second NMOS amplification module (NMOS2) is connected to a non-inverting output (e.g., node 629) of the main amplification circuit; wherein gates of the transistors in the PMOS amplification modules and the NMOS amplification modules are connected to corresponding bias voltages respectively (gate of transistors M2p connected to resistor R1p and receives bias voltage and gate of transistors M2n connected to resistor R1n and receives bias voltage, gate of M1p connected to resistor R2p and receives bias voltage and transistor M1n connected to resistor R2n and receives bias voltage).
Koroglu (annotated Fig. 6) does not disclose each PMOS1, PMOS2, NMOS1 and NMOS2 includes at least 3 transistors.
Panseri (annotated Fig. 8) discloses a circuit having PMOS Module includes transistors Mpsw, Mp & Mpcasc and NMOS Module includes transistors Mnsw, Mn & Mncasc.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify PMOS1, PMOS2, NMOS1 and NMOS2 of Koroglu to add another same type transistor to each PMOS1, PMOS, NMOS1 and NMOS2 in order to provide the benefits of improving efficiency and linearity, stability and performance (see paragraphs [0035] and [0038]).
As a consequence of the combination, the combination (Koroglu in view of Panseri) further discloses wherein K being a natural number greater than or equal to 3 and less than or equal to 5.
Regarding claim 5, the combination (Koroglu in view of Panseri) discloses wherein K is 3.
Regarding claim 7, the combination (Koroglu in view of Panseri) discloses wherein each CSCG structure comprises a main amplification transistor (PMOS1 includes a main transistor M2p; PMOS 2 includes a main transistor M2n; NMOS1 includes a main transistor M1p; and NMOS includes a main transistor M1n) which has a gate (gate terminal of transistor M2p; gate terminal of M2n; gate terminal of M1p; and gate terminal of M1n) connected to a corresponding input of the main amplification circuit via an input capacitor ( C1p, C1n, c2p and C2n).
Allowable Subject Matter
Claims 2-4, 6 & 8-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)270-3941. The examiner can normally be reached Mon-Fri 8:00 AM-5:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ANDREA J LINDGREN BALTZELL can be reached at (571)272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843