Prosecution Insights
Last updated: April 19, 2026
Application No. 18/110,233

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

Final Rejection §102§103
Filed
Feb 15, 2023
Examiner
HIBBERT, DANIEL JOHNATHAN
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
2 (Final)
83%
Grant Probability
Favorable
3-4
OA Rounds
3y 6m
To Grant
99%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
10 granted / 12 resolved
+15.3% vs TC avg
Strong +33% interview lift
Without
With
+33.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
29 currently pending
Career history
41
Total Applications
across all art units

Statute-Specific Performance

§101
2.1%
-37.9% vs TC avg
§103
37.3%
-2.7% vs TC avg
§102
32.6%
-7.4% vs TC avg
§112
28.0%
-12.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 12 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments/Amendments Applicant’s arguments with respect to the 35 U.S.C. 102(a)(1) rejections claims 1-6 and 8-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant amended the claims further to incorporate the limitation of, more or less, in a/first direction the moisture blocking structure, the crack stopper, and the trench are all adjacent to each other with the crack stopper centered between. Examiner finds that this will successfully overcome the disclosure of the prior art made of record, however, after further searching, a new rejection is being made which is necessitated by the amendment. Applicant’s arguments, see Pages 8-9 of “Applicant Arguments/Remarks Made in an Amendment”, filed 12/02/2025, with respect to the 35 U.S.C. 112(b) rejections of claims 1, 6-7, 11, and 20 have been fully considered and are persuasive. Claims 1, 11, 13, 16, and 20 were rejected for being indefinite regarding the usage of “the trench having a predetermined depth”. Applicant argues that the specification provides a clear objective standard for the term predetermined in instant applications paragraphs [0036] and [0100]. Examiner agrees that there is in fact support from the specification thus the rejection is no longer proper. Claims 6 and 7 were rejected because of the confusion as to what applicant is explicitly claiming as the substrate. This confusion stemmed from the line “trench extending along an edge of the substrate” when the trench doesn’t enter any part of the labeled substrate, less an edge of the substrate. Applicant has amended the claim to replace the above limitation new limitations that make the location of the surface of the substrate clear and explicit. Examiner agrees that there is at least support from the drawings for this amendment as well as it makes the location of the surface of the substrate clear. Finally, applicant fixes some antecedent basis rejections of claims 13 and 16 through amendment. The 35 U.S.C. 112(b) rejections of claims 1, 6-7, 11, 13, 16, and 20 has been withdrawn. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 4, 8, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by United States Patent by Hotta et al. (US 8513808 B2; Hotta). Regarding Claim 1, Hotta discloses a semiconductor device, comprising: A substrate (1) having a circuit region (Element formation region) and a protection region (The region including GR – Guard ring) surrounding the circuit region (Col. 5, Lines 40-43, “A guard ring (sealing) GR is formed to surround the element formation region”); a plurality of insulating layers (29, 22, 20a, 19a, and other mutiple side-to-side insulating layers in Fig. 12) sequentially stacked on the substrate (Fig. 12); a moisture blocking structure (GR) extending in the plurality of insulating layers in the protection region of the substrate (Fig. 12, The moisture blocking structure GR extends vertically in the plurality of insulating layers) and surrounding the circuit region (Col. 5, Lines 40-43, “A guard ring (sealing) GR is formed to surround the element formation region”), the moisture blocking structure comprising: a first plurality of wiring layers (Fig. 12, Left column wiring layers under GR - 11, 12, M1-6, 18a, 21a) vertically stacked on a surface of the substrate (Fig. 12), wherein an uppermost wiring layer of the first plurality of wiring layers comprises a first via (Left under GR, contact plug under M5), and a metal wiring provided on the first via (Left under GR, M5); a crack stopper (Fig. 12, right column wiring layers under GR - 11, 12, M1-6, 18a, 21a) extending in the plurality of insulating layers in the protection region of the substrate and surrounding the moisture blocking structure (As the crack stopper [right column wiring layers under GR] is closer to the edge of the IC, the crack stopper is surrounding the moisture blocking structure), the crack stopper comprising a second plurality of wiring layers vertically stacked on the surface of the substrate, wherein an uppermost wiring layer of the second plurality of wiring layers comprises a second via (Left under GR, contact plug under M5); and a trench (SL) surrounding the crack stopper (Col. 5, Lines 40-43, “A slit (such as a trench or a trench pattern) SL is formed to surround the circumference of the guard ring GR”), the trench having a predetermined depth from an upper surface of the plurality of insulating layers (Col. 8, Lines 47-50, “The slit SL is made in the interlayer dielectric 23 laid between the fifth-layer interconnection M5 and the sixth-layer interconnection M6”), wherein, in a first direction, the moisture blocking structure is adjacent to the crack stopper, and the crack stopper is adjacent to the trench which is spaced apart from the moisture blocking structure with the crack stopper therebetween (In at least 1 direction the crack stop is between the moisture blocking structure and the trench). Regarding Claim 4, Hotta discloses the semiconductor device of claim 1, wherein a wiring layer (M4) under the uppermost wiring layer of the second plurality of wiring layers comprises a third via (Contact plug under M4), and the second via of the uppermost wiring layer of the second plurality of wiring layers is provided on the third via (Fig. 12, Where the contact plug below M4 is below the contact plug for M5. While the via’s are not necessarily touching as in the instant application, under broadest reasonable interpretation, the second via is on the third via). Regarding Claim 8, Hotta discloses the semiconductor device of claim 1, wherein the trench has a width of about 3 m to about 4 m (Col. 8, lines 50-51). Regarding Claim 10, Hotta discloses the semiconductor device of claim 1, wherein the second via comprises a linear type via structure extending in one direction within the protection region (Fig. 12, where the via structure is linear). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable as obvious by Hotta in view of United States Patent Application Publication by Tsai et al. (US 20210050307 A1; Tsai). Regarding claim 2, Hotta fails to disclose wherein second via of the uppermost wiring layer of the second plurality of wiring layers of the crack stopper comprises tungsten. In [0018], however, Tsai discloses wherein the semiconductor device including plurality of wiring layers with material such as tungsten. Accordingly, before the effective filling date of the invention, it would have been obvious to one having ordinary skill in the art to select a known wiring layer material such as tungsten, as shown by Tsai [0018], since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. See MPEP § 2144.07 (citing In re Leshin, 277 F.2d 197 (C.C.P.A. 1960)). One would be motivated to choose tungsten over other materials depending on manufacturing considerations such as cost of materials or time it takes to process the layer. Regarding claim 3, Hotta fails to disclose wherein second via of the uppermost wiring layer of the second plurality of wiring layers of the crack stopper comprises tungsten. In [0018], however, Tsai discloses wherein the metal wiring of the uppermost wiring layer of the first plurality of wiring layers of the moisture blocking structure comprises aluminum. Accordingly, before the effective filling date of the invention, it would have been obvious to one having ordinary skill in the art to select a known wiring layer material such as aluminum, as shown by Tsai [0018], since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. See MPEP § 2144.07 (citing In re Leshin, 277 F.2d 197 (C.C.P.A. 1960)). One would be motivated to choose aluminum over other materials depending on manufacturing considerations such as cost of materials or time it takes to process the layer. Allowable Subject Matter Claim 11-20 allowed. Claims 5-7, and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 11, Tsai discloses a semiconductor device (Abs. and Fig. 2), comprising: a substrate (10) comprising a circuit region (CR); a plurality of insulating layers (18 including 12, 14, 16) sequentially stacked on the substrate (Fig. 1F, where layers 12, 14, and 16, are stacked on substrate 10); a first protection structure (SR2/ R2 in Fig. 1F) comprising a first plurality of wiring layers (SR2 – including at least 230, 222a/b, 220, 212a/b, 210, 206a/b, in Fig. 1F) vertically stacked in the plurality of insulating layers on a surface of the substrate (Fig. 1F, where the first plurality of wiring layers are stacked in insulating layers 18), the first protection structure extending along an edge of the substrate and surrounding the circuit region (Fig. 2, where the first protection region SR2/R2 is extending around the circuit region CR); a second protection structure (SR1) comprising a second plurality of wiring layers (SR1 – including at least 130, 122, 120, 112, 110, 106 in Fig. 1F) vertically stacked in the plurality of insulating layers on the surface of the substrate (Fig. 1F, where the second plurality of wiring layers are stacked in insulating layers 18), the second protection structure surrounding the first protection structure (Fig. 2, where the second protection region SR1 is extending around the circuit region CR); and a trench (28/30) surrounding the second protection structure (Fig. 1F, where trench 30 extends on upper edge of substrate and around the second protection structure SR1), the trench having a predetermined depth from an upper surface of the plurality of insulating layers, However, Tsai (and other reference hotta), fails to disclose wherein the first plurality of wiring layers of the first protection structure has a first height from the surface of the substrate, the second plurality of wiring layers of the second protection structure has a second height from the surface of the substrate, and the second height is less than the first. Furthermore, there is no other prior art reference that can either anticipate or be in an obvious combination which would disclose this limitation at the time of filing this instant application. It is for at least these reasons that claim 11 is found contain allowable subject matter. Similarly, claims 5-7, 9, 20 are found to contain allowable subject matter for their similar limitations. Claims 12-19 are found to be allowable based on their dependency on claim 11. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. United States Patent Application Publication by Lee et al. (US 20090096104 A1) United States Patent Application Publication by Angyal et al. (US 20100200958 A1) Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J HIBBERT whose telephone number is (703)756-1562. The examiner can normally be reached Monday - Friday 8am-5pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL J HIBBERT/Examiner, Art Unit 2899 /ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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Prosecution Timeline

Feb 15, 2023
Application Filed
Sep 15, 2025
Non-Final Rejection — §102, §103
Oct 21, 2025
Interview Requested
Oct 30, 2025
Applicant Interview (Telephonic)
Oct 31, 2025
Examiner Interview Summary
Dec 02, 2025
Response Filed
Feb 26, 2026
Final Rejection — §102, §103
Mar 25, 2026
Interview Requested

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
83%
Grant Probability
99%
With Interview (+33.3%)
3y 6m
Median Time to Grant
Moderate
PTA Risk
Based on 12 resolved cases by this examiner. Grant probability derived from career allow rate.

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