DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-11 and 25-26 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (PG Pub. No. US 2022/0157956 A1) in view of Chang et al. (PG Pub. No. US 2022/0052157 A1) and Su et al. (PG Pub. No. US 2021/0351079 A1).
Regarding claim 1, Chen teaches a field-effect transistor structure (¶ 0036 & fig. 4A: 400A) comprising:
a backside interlayer dielectric (ILD) structure (¶ 0022: 120);
a channel structure (¶ 0039: 402) on the backside ILD structure (fig. 4A: 402 disposed on 120);
a 1st source/drain region (¶ 0037: 106b) and a 2nd source/drain region (106a) connected to each other through the channel structure (fig. 4A: 106b connected to 106a through 402);
a 1st contact plug (¶ 0037: 404), on a top surface of the 1st source/drain region (fig. 4A: 404 disposed on top surface of 106b) and connected to a back-end-of-line (BEOL) structure (¶¶ 0021, 0037 & fig. 4A: 404 electrically connected to interconnect structure 117); and
a 2nd contact plug (¶ 0038: 122a), on a bottom surface of the 2nd source/drain region (fig. 4A: 122a disposed on bottom surface of 106a), extending in the backside ILD structure (fig. 4A: 122a extends in ILD 120), and connected a backside power rail (¶ 0039: 122a electrically connected to voltage line VS1),
wherein the 1st source/drain region and the 2nd source/drain region have a substantially same height (fig. 4A: 106b and 106a comprise substantially equal heights).
Chen does not teach the field-effect transistor structure further comprising a blocking layer between the backside ILD structure and the 1st source/drain region, the blocking layer comprising at least one of silicon nitride or a non-dielectric material that includes silicon and is substantially free of germanium, wherein the blocking layer is spaced apart from a 2nd contact plug.
Chang teaches a field-effect transistor structure (¶ 0020 & fig. 1F: 100) comprising a blocking layer (¶ 0023: stop layer 144) between a backside ILD structure (¶ 0023: 148, similar to 122a of Chen) and a 1st source/drain region (¶ 0027, fig. 1B: 144 disposed between 148 and 110B, similar to 106b of Chen), the blocking layer comprising at least one of silicon nitride or a non-dielectric material that includes silicon (¶ 0040: 144 comprises non-dielectric silicon material), wherein the blocking layer is spaced apart from a 2nd contact plug (fig. 1F: 144 spaced apart from 142, similar to 122a of Chen).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the transistor of Chen with the blocking layer of Chang, as a means to reduce or prevent the diffusion of oxygen atoms from the ILD layer (Chang, ¶ 0040) and/or protect S/D region 110B during the formation of back S/D contact structure (Chang, ¶ 0039).
Chen in view of Chang does not teach the blocking layer is substantially free of germanium.
Su teaches a field-effect transistor structure (fig. 19C among others) including a blocking layer (¶ 0033: 148, similar to 144 of Chang) substantially free of germanium (¶ 0033: in at least one embodiment, 148 is made of Si).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the blocking layer of Chen in view of Chang free of germanium, as a means to optimize etching rate and/or etch selectivity (Su, ¶ 0033).
Furthermore (prefd material).
Regarding claim 3, Chen in view of Chang and Su teaches the field-effect transistor structure of claim 1, wherein the blocking layer comprises the non-dielectric material that includes silicon and is substantially free of germanium (Su, ¶ 0033: 148 made of silicon).
Regarding claim 4, Chen in view of Chang and Su teaches the field-effect transistor structure of claim 3, wherein each of the 1st and 2nd source/drain regions comprises p-type impurities (Chen, ¶ 0077).
Regarding claim 7, Chen in view of Chang and Su teaches the field-effect transistor structure of claim 1 wherein each of the 1st and 2nd source/drain regions comprises p-type impurities (Chen, ¶ 0077: 106a/106b regions comprise p-type dopant), and
wherein a width of the blocking layer is less than or equal to a width of a bottom surface of the 1st source/drain region (Chang, fig. 1F: width of 144 substantially equal to width of bottom surface of 110B).
Regarding claim 8, Chen in view of Chang and Su teaches the field-effect transistor structure of claim 1, wherein a side surface of the 2nd contact plug has a positive slope such that a width of a top surface of the 2nd contact plug facing the bottom surface of the 2nd source/drain region is smaller than a width of a bottom surface of the 2nd contact plug facing the backside power rail or the another circuit element (Chen, fig. 4A: top surface of 122a facing 106a has smaller width than bottom surface of 122a facing Vs1).
Regarding claim 9, Chen in view of Chang and Su teaches the field-effect transistor structure of claim 1, wherein no silicon substrate is formed below the 1st and 2nd source/drain regions (Chen, figs. 4A, 21-22A: no silicon substrate disposed below 106b and 106a).
Regarding claim 10, Chen in view of Chang and Su teaches the field-effect transistor structure of claim 1, wherein the blocking layer is a 1st blocking layer (Chang, fig. 1B: 1st portion of 144/146 between 110B and 148).
Chen in view of Chang and Su as applied to claim 1 above does not explicitly teach wherein the field-effect transistor structure further comprises comprising a 2nd blocking layer between the 2nd source/drain region and the 2nd contact plug, and
wherein the 2nd blocking layer comprises silicon or a dielectric material.
However, Chang does teach a 2nd blocking layer (¶ 0032: 138 and/or 140) between a 2nd source/drain region (110A) and a 2nd contact plug (fig. 1B: 138/140 disposed between 110C and 142), and
wherein the 2nd blocking layer comprises silicon or a dielectric material (¶ 0032: 138 and/or 140 comprises silicon and/or dielectric).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the field-effect transistor structure of Chen in view of Chang and Su with a 2nd blocking layer, as a means to prevent the diffusion of metal atoms from the 2nd contact plug to the 2nd source drain region (Chang, ¶ 0032).
Regarding claim 11, Chen in view of Chang and Su teaches the field-effect transistor structure of claim 1, wherein the channel structure comprises a plurality of nanosheet layers (Chen, ¶ 0020: 402, equivalent to 102 of fig. 1A, comprises a plurality of nanosheet layers).
Regarding claim 25, Chen in view of Chang and Su teaches the field-effect transistor structure of claim 3, wherein the 1st source/drain region comprises silicon germanium (Chen, ¶ 0033).
Regarding claim 26, Chen in view of Chang and Su teaches the field-effect transistor structure of claim 10, wherein the 2nd source/drain region comprises silicon germanium (Chen, ¶ 0033).
Claims 12, 14-17 and 27-31 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Chang.
Regarding claim 12, Chen teaches field-effect transistor (fig. 4A: 400A) structure comprising:
a backside interlayer dielectric (ILD) structure (¶ 0022: 120);
a channel structure (¶ 0039: 402) on the backside ILD structure (fig. 4A: 402 disposed on 120);
a 1st source/drain region (¶ 0037: 106b) and a 2nd source/drain region (¶ 0037: 106a) connected to each other through the channel structure (fig. 4A: 106b connected to 106a through 402);
a 1st contact plug (¶ 0037; 404) on a top surface of the 1st source/drain region (fig. 4A: 404 disposed on top surface of 106b) and connected to a back-end-of-line (BEOL) structure (¶¶ 0021, 0037 & fig. 4A: 404 electrically connected to interconnect structure 117);
a 2nd contact plug (¶ 0038: 122a) on a bottom surface of the 2nd source/drain region extending in the backside ILD structure (fig. 4A: 122a disposed on bottom surface of 106a and extending in 120), and connected to a backside power rail (¶ 0039: 122a electrically connected to voltage line VS1),
wherein the 1st source/drain region and the 2nd source/drain region have a substantially same size (fig. 4A: 106b and 106a have substantially same size), and top surfaces of the 1st source/drain region and the 2nd source/drain region are at a substantially at a same level, in a cross-section view in a channel-width direction or a channel-length direction (in the channel-length direction of fig. 4A: top surfaces of 106b and 106a at a substantially equal level).
Chen does not teach the field-effect transistor structure further comprising a blocking layer between the backside ILD structure and a bottom surface of the 1st source/drain region, the blocking layer comprising a dielectric material,
wherein the blocking layer is spaced apart from the 2nd contact plug, and does not extend onto an outer side surface of the 1st source/drain region.
Chang teaches a field-effect transistor structure (¶ 0020: 100) comprising a blocking layer (¶ 0023: stop layer 144 and/or barrier layer 146) between a backside ILD structure (¶ 0023: 148, similar to 122a of Chen) and a 1st source/drain region (¶ 0027, fig. 1B: 144/146 disposed between 148 and 110B, similar to 106b of Chen), the blocking layer comprising a dielectric material that includes silicon (¶ 0040: portion 146 comprises a dielectric material),
wherein the blocking layer is spaced apart from a 2nd contact plug, and does not extend onto an outer side surface of the 1st source/drain region (fig. 1B: at least portion 144 is spaced apart from 142, similar to 122a of Chen, and does not extend onto an outer side surface of 110B).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the transistor of Chen with the blocking layer of Chang, as a means to reduce or prevent the diffusion of oxygen atoms from the ILD layer (Chang, ¶ 0040) and/or protect S/D region 110B during the formation of back S/D contact structure (Chang, ¶ 0039).
Regarding claim 14, Chen in view of Chang teaches the field-effect transistor structure of claim 12, wherein the blocking layer comprises silicon nitride (Chang, ¶ 0040: at least portion 146 comprises silicon nitride).
Regarding claim 15, Chen in view of Chang teaches the field-effect transistor structure of claim 12, wherein each of the 1St and 2nd source/drain regions comprises p-type impurities (Chen, ¶ 0077: in at least one embodiment, 106a/106b comprises p-type impurities), and
wherein a top surface of the blocking layer is coplanar with a top surface of the 2nd contact plug (Chang, fig. 1B: interface 113B of 144 coplanar with interface 143 of 142).
Regarding claim 16, Chen in view of Chang teaches the field-effect transistor structure of claim 12, wherein a side surface of the 2nd contact plug has a positive slope such that a width of a top surface of the 2nd contact plug facing the bottom surface of the 2nd source/drain region is smaller than a width of a bottom surface of the 2nd contact plug facing the backside power rail (Chen, fig. 4A: top surface of 122a facing 106a smaller width than bottom surface of 122a facing Vs1).
Regarding claim 17, Chen in view of Chang teaches the field-effect transistor structure of claim 12, wherein the blocking layer is a 1st blocking layer (Chang, fig. 1B: 1st portion of 144/146 between 110B and 148).
Chen in view of Chang as applied to claim 1 above does not explicitly teach wherein the field-effect transistor structure further comprises comprising a 2nd blocking layer between the 2nd source/drain region and the 2nd contact plug, and
wherein the 2nd blocking layer comprises silicon.
However, Chang does teach a 2nd blocking layer (¶ 0032: 138 and/or 140) between a 2nd source/drain region (110A) and a 2nd contact plug (fig. 1B: 138/140 disposed between 110C and 142), and
wherein the 2nd blocking layer comprises silicon (¶ 0032: 138 and/or 140 comprises silicon).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the field-effect transistor structure of Chen in view of Chang with a 2nd blocking layer, as a means to prevent the diffusion of metal atoms from the 2nd contact plug to the 2nd source drain region (Chang, ¶ 0032).
Regarding claim 30, Chen in view of Chang teaches the field-effect transistor structure of claim 12, wherein a width of the blocking layer is less than or equal to a width of the bottom surface of the 1st source/drain region (Chang, fig. 1B: width of at least portion 144 substantially equal to width of bottom surface of 110B).
Regarding claim 27, Chen teaches a field-effect transistor structure (fig. 4A: 400A) comprising:
a backside interlayer dielectric (ILD) structure (¶ 0022: 120);
a channel structure (¶ 0039: 402) on the backside ILD structure (fig. 4A: 402 disposed on 120);
a 1st source/drain region (¶ 0037: 106b) and a 2nd source/drain region (106a) connected to the channel structure (fig. 4A: 106b, 106a connected to 402);
a 1st contact plug (¶ 0037: 404) on a top surface of the 1st source/drain region (fig. 4A: 404 disposed on top surface of 106b); and
a 2nd contact plug (¶ 0038: 122a) on a bottom surface of the 2nd source/drain region (fig. 4A: 122a disposed on bottom surface of 106a),
wherein a top surface the 2nd contact plug is in direct contact with the bottom surface of the 2nd source/drain region (fig. 4A: top surface of 122 is in direct contact with top surface of 106a).
Chen does not teach the field-effect transistor structure further comprising a blocking layer between the backside ILD structure and the 1st source/drain region, the blocking layer comprising at least one of silicon or a dielectric material,
wherein a top surface the 2nd contact plug is coplanar with a top surface of the blocking layer.
Chang teaches a field-effect transistor structure (¶ 0020: 100) comprising a blocking layer (¶ 0023: stop layer 144 and/or barrier layer 146) between a backside ILD structure (¶ 0023: 148, similar to 122a of Chen) and a 1st source/drain region (¶ 0027, fig. 1B: 144/146 disposed between 148 and 110B, similar to 106b of Chen), the blocking layer comprising at least one of silicon nitride or a dielectric material (¶ 0040: 144/146 comprises silicon nitride and/or a dielectric material),
wherein a top surface of a 2nd contact plug is coplanar with a top surface of the blocking layer (fig. 1B: top surface of contact plug portion 142 coplanar with top surface of 144).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the transistor of Chen with the blocking layer of Chang, as a means to reduce or prevent the diffusion of oxygen atoms from the ILD layer (Chang, ¶ 0040) and/or protect S/D region 110B during the formation of back S/D contact structure (Chang, ¶ 0039).
Regarding claim 28, Chen in view of Chang teaches the field-effect transistor structure of claim 27, wherein the 1st source/drain region and the 2nd source/drain region have a substantially same height (Chen, fig. 4A: 106b and 106a comprise substantially equal heights)
Regarding claim 29, Chen in view of Chang teaches the field-effect transistor structure of claim 27, wherein the 1st source/drain region is connected to a back-end-of-line (BEOL) structure through the 1st contact plug (Chen, ¶¶ 0021, 0037 & fig. 4A: 404 electrically connected to interconnect structure 117 through 404; since 117 comprises metal layers formed after the active device elements, it meets the broadest reasonable interpretation of a BEOL structure), and
wherein the 2nd source/drain region is connected to a backside power rail through the 2nd contact plug (Chen, ¶ 0039 & fig. 4A: 106a electrically connected to voltage line VS1 through 122a; since Vs1 is a source voltage line, it meets the broadest reasonable interpretation of a backside power rail).
Regarding claim 31, Chen in view of Chang teaches the field-effect transistor structure of claim 27, wherein the blocking layer is in direct contact with a bottom surface of the 1st source/drain region (Chang, fig. 1B: portion 144 in direct contact with bottom surface of 110B).
Response to Arguments
Applicant’s arguments on pages 7-11 with respect to the 35 USC § 102 and 35 USC § 103 rejections of claims 1, 3-4, 7-12, 14-17 and 25-29 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/BRIAN TURNER/Examiner, Art Unit 2818
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