DETAILED ACTION
Election/Restrictions
Applicant’s election with traverse of claims 1-10 and 20 in the reply filed on 10/13/25 is acknowledged. The traversal is on the ground(s) that the claims 11-19 are not really method of making steps, and also there are claims that recite a single router, thus making grounds for restriction not properly recited. This is not found persuasive for the following reasons.
This particular application has been forwarded to a Semiconductor Examiner, because the claims recite a semiconductor circuit in an independent claim. However, not all claims are related to Semiconductors (i.e., physical object related art). Some claims (11-19) are related to a routing method, instead (i.e., a software programming related art). This type of art is not properly examinable by Semiconductor Examiners, or even by this Technology Center. Therefore, after consultation with a Supervisor, a restriction was issued between claims examinable by Semiconductor Examiners and those that would need to be transferred to a different Examiner, in a different Technology Center (i.e., a Technology Center that examines software programming), if they would have been elected. Because the claims in question (claims 11-19) do not properly belong for examination in front of this Examiner and this Technology Center, the requirement is still deemed proper and is therefore made FINAL.
Claims 11-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 10/13/25.
Again, if Applicant has any further questions, Applicant is encouraged to call Examiner for an interview.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8-10 & 20 are rejected under 35 U.S.C. 103 as being unpatentable over (US-7,117,468) by Teig et al (“Teig”).
Regarding claim 1, Teig discloses in FIGs. 129-131 and related text, e.g., an integrated circuit (Abstract) comprising:
a first plurality of wiring layers with no preferred wiring direction (FIGs. 129-131 and col. 103, lines 20-35; two wiring layers are explicitly mentioned in cited portion, and are explicitly shown in FIGs. 129-130; also, both of these layers use “non-preferred direction routing”; also, see col. 6, line 5 through col. 7, line 45, which define various examples of “non-preferred direction routing” embodiments explicitly considered by Teig); and
a second plurality of wiring layers with at least first and second preferred wiring directions (col. 7, lines 27-35).
Teig does not explicitly state in disclosed embodiments “a first plurality of wiring layers with no preferred wiring direction and curvilinear wiring”.
To elaborate briefly on the above, the wiring shown in FIGs. 129-130 shows several curved shapes. However, one can argue that each one of those shapes is not “curvilinear” by a strictest definition. To eliminate all doubt, Examiner wishes to point to a different part of Teig’s patent. Specifically, Teig’s Admitted Prior Art.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Teig with “curvilinear wiring”, since such teachings are explicitly included in the Teig’s patent (Page 3, second column, about a third of the way from the bottom, “Hama T. et al., Curvilinear Detailed Routing Algorithm and its Extension to Wire-Spreading and Wire-Fattening”; part of Teig’s Admitted Prior Art), in order to take advantage of curvilinear detailed routing’s notoriously well-known benefits, such as efficiency in terms of space usage.
Regarding claim 2, Teig discloses in FIGs. 129-131 and related text, e.g., wherein the first plurality of wiring layers comprises layers 3 and 4, and the second plurality of wiring layers comprises layers 5 and 6 (col. 7, line 27 and on: “In addition, some embodiments have more than five layers, while other embodiments have fewer. Some embodiments also assign a single preferred direction for some of the layers, while allowing other layers not to have a single preferred wiring direction”; use of more than 5 layers is disclosed, thus teaching use of 6 or more layers; use of some layers with NPD wiring and some with preferred direction wiring is explicitly taught and explained; also, see claim 1; hence, use of NPD layers on some layers (such as layers 5 and 6), and use of preferred direction routing on some other layers (such as layers 3 and 4) is at the very least obvious in light of Teig’s explicit teachings as recited in col. 7 and elsewhere).
Regarding claim 3, Teig discloses in FIGs. 129-131 and related text, e.g., wherein the second plurality of wiring layers further comprises layers 1 and 2 (see rejection of claim 2 above, and the recitation of text in col. 7, line 27 and lower; such embodiment is at the very least obvious in light of Teig’s explicit teachings, as was discussed in rejections of claims 1 & 2).
Regarding claim 4, Teig discloses in FIGs. 129-131 and related text, e.g., wherein the first plurality of wiring layers comprises layers 1-4, and the second plurality of wiring layers comprises layers 5 and 6 (see rejection of claim 2 above, and the recitation of text in col. 7, line 27 and lower; such embodiment is at the very least obvious in light of Teig’s explicit teachings, as was discussed in rejections of claims 1 & 2).
Regarding claim 5, Teig discloses in FIGs. 129-131 and related text, e.g., wherein the second plurality of wiring layers comprises wiring layers 1 and 2 (see rejection of claim 2 above, and the recitation of text in col. 7, line 27 and lower; such embodiment is at the very least obvious in light of Teig’s explicit teachings, as was discussed in rejections of claims 1 & 2).
Regarding claim 8, Teig discloses in FIGs. 129-131 and related text, e.g., wherein each preferred wiring direction is a horizontal direction or a vertical direction, and the preferred wiring directions of different adjacent layers in the second plurality of layers alternate between horizontal and vertical directions (col. 1, line 65 through col. 2, line 3).
Regarding claim 9, Teig discloses in FIGs. 129-131 and related text, e.g., wherein preferred wiring direction on each layer is the direction that includes at least 90% of the wiring on that layer (col. 2, lines 1-3; “However, occasional diagonal jogs are sometimes allowed on the preferred horizontal and vertical layers”; hence, the above limitations of “at least 90%” are at least obvious in light of Teig’s explicit teachings).
Regarding claim 10, Teig discloses in FIGs. 129-131 and related text, e.g., wherein at least one layer in the first plurality of layers comprises wires traversing in more than eight directions (by definition; a curved line, at any point, has an infinity of directions along the curve; hence, “more than eight”, by definition).
Regarding claim 20, Teig discloses in FIGs. 129-131 and related text, e.g., wherein the first plurality of non-preferred direction wiring layers include shorter wires that serve as shorter connections for connecting different locations on a substrate of the IC, while the second plurality of preferred direction wiring layer include longer wires that serve as longer connections for connecting different locations on the IC substrate (by definition; see FIG. 132 for example; it shows various 45 degree turns between various layers; if the 45 degree turn was replaced with a true curve, as in “curvilinear”, the curve portion would be tiny; hence, “include shorter wires that serve as shorter connections for connecting different locations on a substrate of the IC”; the straight lines are relatively long when compared to tiny turns/curves; hence, “include longer wires that serve as longer connections for connecting different locations on the IC substrate”).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over (US-7,117,468) by Teig et al (“Teig”) in view of (US-7,441,220) by Hetzel et al (“Hetzel”).
Regarding claim 6, Teig discloses in cited figures and related text, e.g., substantially the entire claim structure, as recited in above claims, except “wherein the wiring layers 1 and 2 each has a plurality of regions with preferred direction rectilinear wiring for pre-defined IP (intellectual property) circuit blocks”.
Hetzel discloses in FIGs. 2-16B and related text, e.g., use of various preferred direction schemas in a same wiring layer (see FIG. 2 (and other figures) for one preferred direction in general, and very different directions for specific blocks (205, 210-215); see FIG. 7 for “IP Block” specifically situation (and other figures)).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Teig with “wherein the wiring layers 1 and 2 each has a plurality of regions with preferred direction rectilinear wiring for pre-defined IP (intellectual property) circuit blocks” as taught by Hetzel, in order to “recapture the routing resources lost because of obstacles on a wiring layer” (col. 2, lines 11-13).
Regarding claim 7, the combined device of Teig and Hetzel disclose in cited figures and related text, e.g., wherein a plurality of curvilinear wire segments are defined on wiring layers 1 and 2 between the regions with PD wiring for the IP circuit blocks (use of any number of curvilinear line segments, for an entire wiring layer, was explained regarding claim 1; use of “IP circuit blocks” with other wiring schemes, has been explained by Hetzel; the combination of the two references makes all the limitations obvious).
Conclusion
Additional references (if any) are cited on the PTO-892 as disclosing similar features to those of the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alexander Belousov/Patent Examiner, Art Unit 2894
01/08/26
/Mounir S Amer/Primary Examiner, Art Unit 2818