Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This is a response to the amendment filed on 12/04/25. The applicant argument regarding Teig et al. is not persuasive; therefore, all the rejections based on Teig et al. is retained and repeated for the following reasons.
Summary of claims
Claims 1-20 are pending.
Claims 1-20 are rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Teig et al. (US Pat. 7096449).
As to claims 1 the prior art teaches a method of performing curvilinear routing for an integrated circuit design, the method comprising:
performing a topological routing operation to identify a plurality of topological routes for a plurality of nets (see fig 3-8 col. 8 lines 54 to col. 9 lines 56; especially, Teig et al. teach performing a topological routing operation to identify a plurality of topological routes for a plurality of nets as fig 3-8 col. 9 lines 1-50);
and performing a geometric routing operation to identify a plurality of geometric routes for the identified plurality of topological routes, said identified geometric routes comprising a plurality of curvilinear routes with curvilinear segments (see fig 3, fig 6-9 col. 9 lines 23 to col. 11 lines 44; especially, Teig et al. teach performing a geometric routing operation to identify a plurality of geometric routes for the identified plurality of topological routes, said identified geometric routes comprising a plurality of curvilinear routes with curvilinear segments as fig 3, fig 6-9 col. 9 lines 40 to col. 11 lines 30).
As to claims 2, the prior art teaches wherein each topological route in a set of topological routes has a plurality of possible geometric routes that are possible geometric realizations of the topological route (see fig 3-8 col. 9 lines 1-60).
As to claims 3 the prior art teaches wherein each of a plurality of topological route has positional information defined by reference to at least one other topological route, while each geometric route is defined by reference to specific coordinates that define one or more route segments of the geometric route (see fig 3, 6-9 col. 10 lines 20 to col. 11 lines 60).
As to claims 4 the prior art teaches wherein each topological route also has positional information defined by references to at least two nodes in the IC design connected by the topological route (see fig 3-8 col. 11 lines 20 to col. 12 lines 40).
As to claim 5 the prior art teaches wherein performing the topological routing operations comprises tessellating one or more routing layers into a plurality of polygons and defining the topological routes by reference to edges of the polygons (see fig 7-11 col. 12 lines 10 to col. 13 lines 50).
As to claims 6 the prior art teaches wherein the geometric routing operation specifies spacing between the geometric routes, while the topological routing operation does not specify specific spacing as the topological routing operation does not define geometric coordinates for the entirety of each topological route (see fig 7-13 col. 13 lines 20 to col. 14 lines 40).
As to claims 7 the prior art teaches wherein the geometric routing operation specifies spacing between the geometric routes, while the topological routing operation does not specify specific spacing as the topological routing operation does not define geometric coordinates for each end of each segment of each topological route that the topological routing operation defines (see fig 7-13 col. 14 lines 10 to col. 15 lines 50).
As to claims 8 the prior art teaches wherein the topological routing operation accounts for expected wire thickness of the topological routes in order to keep track of congestion along the polygon edges (see fig 7-13 col. 16 lines 10 to col. 17 lines 45).
As to claim 9 the prior art teaches further comprising performing a post-processing operation to optimize one or more identified geometric routes based on one or more optimization criteria (see fig 8-14 col. 17 lines 50 to col. 18 lines 45).
As to claims 10 the prior art teaches wherein the geometric routing defines geometric routes by defining widths for the identified topological routes, and the post-processing operation modifies the geometric routes based on the optimization criteria (see fig 8-14 col. 18 lines 20 to col. 19 lines 50).
As to claims 11, the prior art teaches wherein the optimization criteria comprises a spacing criteria to spread out the geometric routes in order to reduce capacitive coupling between the geometric routes (see fig 8-14 col. 19lines 30 to col. 20lines 45).
As to claims 12 the prior art teaches wherein the optimization criteria comprises a compaction criteria to pack the geometric routes in order to reduce size of an IC die on which the IC is manufactured. (see fig 8-14 col. 20 lines 30 to col. 21 lines 65)
As to claims 13 the prior art teaches wherein the optimization criteria comprises user selectable criteria that a user selects in order to improve the performance of the IC design (see fig 8-16 col. 23 lines 40 to col. 24 lines 56).
As to claim 14 the prior art teaches wherein the user-selectable optimization criteria further comprising reducing the area consumed by the geometric routes (see fig 12-17 col. 24 lines 25 to col. 26 lines 65);
wherein the performing of the post-processing operation comprises directing a compactor to compact the geometric routes when a user selects area reduction as the optimization criteria (see fig 12-17 col 26 lines 14 to col. 27 lines 60).
As to claims 15 the prior art teaches further comprising modifying at least a subset of the geometric routes to be further away from at least some of their neighboring routes when the user selects spacing out the geometric routes to improve timing performance of signals traversing wires that will be produced based on these routes (see fig 12-18 col. 25 lines 50 to col. 27 lines 10).
As to claims 16 the prior art teaches wherein the post-processing optimizes the geometric routes by directing a geometric router that performed the geometric routing operation to re-perform a routing operation for a subset of nets (see fig 8-14 col. 18 lines 50 to col. 19 lines 65).
As to claims 17 the prior art teaches wherein the post-processing optimizes the geometric routes without directing a geometric router that performed the geometric routing operation to re-perform any routing operation for any subset of nets (see fig 9-14 col. 19 lines 40 to col. 21 lines 50).
As to claim 18 the prior art teaches wherein the post-processing operation modifies one or more geometric routes by moving one or more segments of the modified geometric routes in the IC design (see fig 10-15 col. 21 lines 30 to col. 22 lines 60).
As to claim 19 the prior art teaches wherein the post-processing operation modifies one or more geometric routes by defining additional segments and additional coordinates for one or more segments of the modified geometric routes in the IC design (see fig 11-16 col. 22 lines 50 to col. 24 lines 15).
As to claim 20 the prior art teaches a non-transitory machine readable medium storing a routing program which when executed by at least one processing unit defines curvilinear routes for an integrated circuit (IC) design, the program comprising sets of instructions for:
performing a topological routing operation to identify a plurality of topological routes for a plurality of nets in the IC design (see fig 3-8 col. 8 lines 30 to col. 9 lines 50;
and performing a geometric routing operation to identify a plurality of geometric routes for the identified plurality of topological routes, said identified geometric routes comprising a plurality of curvilinear routes, each curvilinear route comprising at least one curved segment that is not a straight line (see fig 3, fig 6-9 col. 9 lines 1 to col. 11 lines 60).
Remarks
Applicant’s response and remarks filed on 12/04/25 have been carefully reviewed. Applicant’s arguments have been fully considered but they are not persuasive. Key argument and their response related to the claims are listed as below:
Applicant contends that Teig et al. do not describe “performing a topological routing operation to identify a plurality of topological routes for a plurality of nets” probes as claimed, Examiner respectfully disagrees. The prior art (Teig et al. US Pat. 7096449) do teach performing a topological routing operation to identify a plurality of topological routes for a plurality of nets (see fig 3-8 col. 8 lines 54 to col. 9 lines 56; especially, Teig et al. teach performing a topological routing operation to identify a plurality of topological routes for a plurality of nets as fig 3-8 col. 9 lines 1-50).
Applicant contends that Teig et al. do not describe “performing a geometric routing operation to identify a plurality of geometric routes for the identified plurality of topological routes, said identified geometric routes comprising a plurality of curvilinear routes with curvilinear segments” probes as claimed, Examiner respectfully disagrees. The prior art (Teig et al. US Pat. 7096449) do teach performing a geometric routing operation to identify a plurality of geometric routes for the identified plurality of topological routes, said identified geometric routes comprising a plurality of curvilinear routes with curvilinear segments (see fig 3, fig 6-9 col. 9 lines 23 to col. 11 lines 44; especially, Teig et al. teach performing a geometric routing operation to identify a plurality of geometric routes for the identified plurality of topological routes, said identified geometric routes comprising a plurality of curvilinear routes with curvilinear segments as fig 3, fig 6-9 col. 9 lines 40 to col. 11 lines 30)
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BINH C TAT/Primary Examiner, Art Unit 2851