Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This office action is in response to response to Notice of Appeal filed on 04/09/26.
Summary of claims
Claims 1-20 are pending.
Claims 1-4, 9-20 are rejected.
Claims 5-8 are objected.
Oath/Declaration
The oath/declaration filed on February 15th, 2023 is acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 9-20 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hama et al. Curvilinear detailed routing algorithm and its extension to wire-spreading and wire-fattening (06/08/2002), IEEE. pp 385-390.
As to claims 1 the prior art teaches a method of performing curvilinear routing (see abstract) for an integrated circuit design, the method comprising:
performing a topological routing operation to identify a plurality of topological routes for a plurality of nets (see fig 1-2 p385 col. 1 lines 18 to col. 2 lines 30);
and performing a geometric routing operation to identify a plurality of geometric routes for the identified plurality of topological routes, said identified geometric routes comprising a plurality of curvilinear routes with curvilinear segments (see fig 1-2 p386 col. 1 lines 7 to col. 2 lines 15).
As to claims 2, the prior art teaches wherein each topological route in a set of topological routes has a plurality of possible geometric routes that are possible geometric realizations of the topological route (see fig 1-2 p385 col. 1 lines 18-40).
As to claims 3 the prior art teaches wherein each of a plurality of topological route has positional information defined by reference to at least one other topological route, while each geometric route is defined by reference to specific coordinates that define one or more route segments of the geometric route (see fig 1-2 p386 col. 1 lines 7-45).
As to claims 4 the prior art teaches wherein each topological route also has positional information defined by references to at least two nodes in the IC design connected by the topological route (see fig 1-2 p386 col. 1 lines 7-45).
As to claim 9 the prior art teaches further comprising performing a post-processing operation to optimize one or more identified geometric routes based on one or more optimization criteria (see fig 2-3 p387 col. 1 lines 1-45).
As to claims 10 the prior art teaches wherein the geometric routing defines geometric routes by defining widths for the identified topological routes, and the post-processing operation modifies the geometric routes based on the optimization criteria ((see fig 2-3 p387 col. 1 lines 28 to col. 2 lines 14).
As to claims 11, the prior art teaches wherein the optimization criteria comprises a spacing criteria to spread out the geometric routes in order to reduce capacitive coupling between the geometric routes (see fig 2-4 p387 col. 2 lines 5-50).
As to claims 12 the prior art teaches wherein the optimization criteria comprises a compaction criteria to pack the geometric routes in order to reduce size of an IC die on which the IC is manufactured. (see fig 3-4 p387 col. 2 lines 40 to p388 col. 1 lines 15)
As to claims 13 the prior art teaches wherein the optimization criteria comprises user selectable criteria that a user selects in order to improve the performance of the IC (see fig 2-4 p388 col. 1 lines 1-40).
As to claim 14 the prior art teaches wherein the user-selectable optimization criteria further comprising reducing the area consumed by the geometric routes (see fig 1-2 p386 col. 1 lines 30 to col. 2 lines 40);
wherein the performing of the post-processing operation comprises directing a compactor to compact the geometric routes when a user selects area reduction as the optimization criteria (see fig 2-4 p387 col. 1 lines 15-50).
As to claims 15 the prior art teaches further comprising modifying at least a subset of the geometric routes to be further away from at least some of their neighboring routes when the user selects spacing out the geometric routes to improve timing performance of signals traversing wires that will be produced based on these routes (see fig 2-4 p388 col. 1 lines 15-50).
As to claims 16 the prior art teaches wherein the post-processing optimizes the geometric routes by directing a geometric router that performed the geometric routing operation to re-perform a routing operation for a subset of nets (see fig 2-3 p388 col. 2 lines 1-40).
As to claims 17 the prior art teaches wherein the post-processing optimizes the geometric routes without directing a geometric router that performed the geometric routing operation to re-perform any routing operation for any subset of nets (see fig 2-3 p389 col. 1 lines 5-44).
As to claim 18 the prior art teaches wherein the post-processing operation modifies one or more geometric routes by moving one or more segments of the modified geometric routes in the IC design (see fig 2-3 p389 col. 2 lines 10-45)
As to claim 19 the prior art teaches wherein the post-processing operation modifies one or more geometric routes by defining additional segments and additional coordinates for one or more segments of the modified geometric routes in the IC design (see fig 2-3 p389 col. 2 lines 15-50).
As to claim 20 the prior art teaches a non-transitory machine readable medium storing a routing program which when executed by at least one processing unit defines curvilinear routes for an integrated circuit (IC) design, the program comprising sets of instructions for:
performing a topological routing operation to identify a plurality of topological routes for a plurality of nets in the IC design (see fig 1-2 p385 col. 1 lines 18 to col. 2 lines 30;
and performing a geometric routing operation to identify a plurality of geometric routes for the identified plurality of topological routes, said identified geometric routes comprising a plurality of curvilinear routes, each curvilinear route comprising at least one curved segment that is not a straight line (see fig 1-2 p386 col. 1 lines 7 to col. 2 lines 15).
Allowable Subject Matter
Claims 5-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BINH C TAT/Primary Examiner, Art Unit 2851
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