DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Species 2, as shown FIG. 12, was elected.
Amendment filed July 22, 2026 is acknowledged. Claims 9 and 12 have been cancelled. Claims 1, 6, 11 and 16 have ben amended. Non-Elected Species, claims 5, 7, 13, 15 and 17-18 have been withdrawn from consideration. Claims 1-8, 10-11 and 13-20 are pending.
Action on merits of the Elected Species, claims 1-4, 6, 8, 10-11, 14, 16 and 19-20 follows.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 16 and 19-20 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There does not appear to be a written description of the claim limitation “wherein a first density of the plurality of segment regions per unit area in a zone between the source electrode and the drain electrode is greater than a second density of the plurality of segment regions per unit area in a remaining zone between the source electrode and the drain electrode excluding the zone and excluding an outermost source region of the source regions.” (amended claim 16) (emphasis added) in the application as filed.
As shown in FIG. 12, first, the “zone between the source electrode (SME) and the drain electrode (DME)” is the middle portion having about 6 PIR (SIR).
Second, the “remaining zone between the source electrode (SME) and the drain electrode (DME) excluding the zone and excluding an outermost source region of the source regions” is nothing because by excluding the “zone” and excluding “an outermost source region of the source regions” there is nothing left.
Thus, the specification does not provide support for “a remaining zone between the source electrode (SME) and the drain electrode (DME) excluding the zone and excluding an outermost source region of the source regions”.
Therefore, amended claim 16 contains new matter(s).
Applicant must cancel the un-support new matters in response to the Office Action.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-4, 6, 8, 11-12, 14; and 16, 19-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claims 1 and 11, claims 1 and 11 contains the trademark/trade name “buck converter”. Where a trademark or trade name is used in a claim as a limitation to identify or describe a particular material or product, the claim does not comply with the requirements of 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph. See Ex parte Simpson, 218 USPQ 1020 (Bd. App. 1982). The claim scope is uncertain since the trademark or trade name cannot be used properly to identify any particular material or product. A trademark or trade name is used to identify a source of goods, and not the goods themselves. Thus, a trademark or trade name does not identify or describe the goods associated with the trademark or trade name. In the present case, the trademark/trade name is used to identify/describe a device that includes a first metal oxide semiconductor field effect transistor (MOSFET) having a first conductivity type (NMOS) and a second MOSFET having a second conductivity type (PMOS) and, accordingly, the identification/description is indefinite.
It is well known in the art that there are many different ways for skill workers in the art to make a “buck converter”.
What is a “buck converter” included or excluded?
The same had already been raised by the Applicant, that the cited reference does not disclose a “buck converter”, only a CMOS.
The same question had been raised by the Examiner.
Other than “buck converter” the claim(s) fail to explicitly claim “a buck converter includes or excludes”.
Therefore, claim 1 and 11 and all dependent claims are indefinite.
For the purpose of examination on merits, a “buck converter” is a device that includes an NMOS and a PMOS, or a CMOS.
Regarding claim 16, the amended claim 16 recites: “wherein a first density of the plurality of segment regions per unit area in a zone between the source electrode and the drain electrode is greater than a second density of the plurality of segment regions per unit area in a remaining zone between the source electrode and the drain electrode excluding the zone and excluding an outermost source region of the source regions.” (amended claim 16) (emphasis added) in the application as filed.
As shown in FIG. 12, the limitation: “zone between the source electrode (SME) and the drain electrode (DME)” is the middle portion having about 6 PIR (SIR); and
The limitation “remaining zone between the source electrode (SME) and the drain electrode (DME) excluding the zone and excluding an outermost source region of the source regions” is nothing because by excluding the “zone” and excluding “an outermost source region of the source regions” there is nothing left to compare with.
There is no way to compare “6 PIR (SIR) to an unknown region, with an unknown number of PIR (SIR)”
Therefore, claim 16 and all dependent claims are indefinite.
Since amended claim 16 contains new matter(s) and indefinite, an action on merits claim 16 and 19-20 are impossible, thus, excluded.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 10-11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over WILLIAMS (US. Patent No. 5,744,994) in view of RISAKI (US. Patent No. 10,438,944) and KER et al. (US. Pub. No. 2004/0070900) both of record.
With respect to claim 1, WIILIAMS teaches a power management integrated circuit substantially as claimed, comprising a buck converter (1120) that includes a first metal oxide semiconductor field effect transistor (MOSFET) (1124) having a first conductivity type (NMOS) and a second MOSFET (1122) having a second conductivity type (PMOS),
wherein the first MOSFET (1124) includes a transistor sets that are two-dimensionally arranged. (See FIG. 11B).
Thus, WILLIAMS is shown to teach all the features of the claim with the exception of explicitly disclosing the first MOSFET includes a plurality of transistor sets; and a first number of the plurality of segment regions in the first source region being different from a second number of the plurality of segment regions in the second source region.
Note that, the term: “A power management integrated circuit comprising a buck converter that includes …” is a non-limiting preamble.
However, RISAKI teaches a power management integrated circuit including a first MOSFET (NMOS),
wherein the first MOSFET includes a plurality of transistor sets that are two-dimensionally arranged,
wherein each of the plurality of transistor sets includes a plurality of source regions (11), a plurality of drain regions (12), and a plurality of gate electrodes (1-6) between the plurality of source regions (11) and the plurality of drain regions (12),
wherein each of the plurality of source regions (11) and each of the plurality of drain regions (12) includes an impurity region having the first conductivity type (N),
wherein each of the plurality of source regions (11) further includes a plurality of segment regions (24) having the second conductivity type (P),
wherein a first source region (left) of the plurality of source regions (11) is spaced apart from a second source region (central) of the plurality of source regions (11) in a first direction,
wherein each of the plurality of transistor sets further includes:
a source electrode (Vss) connected in common to the plurality of source regions (11); and
a drain electrode (PAD) connected in common to the plurality of drain regions (12). (See FIG. 2A).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the first MOFET of WILLIAMS having the plurality of transistor set as taught by RISAKI to cause uniform current to flow through all channels of all transistors.
Further KER teaches a power management integrated circuit including a first MOSFET (NMOS) (30),
wherein the first MOSFET (30) includes a plurality of transistor sets that are two-dimensionally arranged,
wherein each of the plurality of transistor sets includes a plurality of source regions (S), a plurality of drain regions (D), and a plurality of gate electrodes (G) between the plurality of source regions (S) and the plurality of drain regions (D),
wherein each of the plurality of source regions (S) further includes a plurality of segment regions (40) having the second conductivity type (P),
wherein a first number of the plurality of segment regions (40) in the first source region (S, central) is different from a second number of the plurality of segment regions (40) in the second source region (S, left). (See FIGs. 6A-C, 7A-B).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the plurality of the source region of WILLIAMS, in view of RISAKI, having the first number of the plurality of segment regions in the first source region being different from a second number of the plurality of segment regions in the second source region as taught by KER for the same intended purpose of providing back gate contact.
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With respect to claim 2, in view of KER, the first number (S. central) is greater than the second number (S, left), and the first source region (S) is closer than the second source region to a center of the transistor set which includes the first source region and the second source region.
With respect to claim 3, in view of KER, each of the plurality of gate electrodes (G) extends in a second direction (A) that intersects the first direction (B), and each of the plurality of segment regions (40) are spaced apart from each other along the second direction (A).
With respect to claim 4, in view of KER, each of the plurality of transistor sets includes a central region (central) and a peripheral region (left, right) that surrounds the central region, and a first density of the plurality of segment regions (40) in the central region is greater than a second density of the plurality of segment regions (40) in the peripheral region.
With respect to claim 6, in view of KER, a first density of the plurality of segment regions (40) in a zone between the source electrode and the drain electrode is greater than a second density of the plurality of segment regions (40) in a remaining zone other than the zone.
With respect to claim 10, in view of KER, each of the plurality of source regions (S) further includes a lightly doped impurity region (not numbered) below a corresponding gate electrode (G) of the plurality of gate electrodes, the lightly doped impurity region having the first conductivity type (N), when a transistor set is operated, a current flows from a drain region (D) toward a corresponding source region (S), and the current bypasses the plurality of segment regions (40) of the corresponding source region (S) and flows through the lightly doped impurity region toward the corresponding source region (S).
With respect to claim 11, WILLIAMS teaches a power management integrated circuit substantially as claimed, including a buck converter(1120) that includes a first metal oxide semiconductor field effect transistor (MOSFET) having a first conductivity type (NMOS) (1124) and a second MOSFET having a second conductivity type (PMOS) (1122),
wherein the first MOSFET (1124) includes a transistor sets that are two-dimensionally arranged. (See FIG. 11B).
Thus, WILLIAMS is shown to teach all the features of the claim with the exception of explicitly disclosing the first MOSFET includes a plurality of transistor sets; and a first density of the plurality of segment regions in the central region is greater than a second density of the plurality of segment regions in the peripheral region.
Note that, the term: “A power management integrated circuit comprising a buck converter that includes …” is a non-limiting preamble.
However, RISAKI teaches a power management integrated circuit including a first MOSFET (NMOS),
wherein the first MOSFET includes a plurality of transistor sets that are two-dimensionally arranged,
wherein a transistor set includes a plurality of transistor sets includes a source region (11), a drain region (12), and a gate electrodes between the source regions (11) and the drain region (12),
wherein each of the source region (11) and each of the plurality of drain region (12) includes an impurity region having the first conductivity type (N),
wherein the source region (11) further includes a plurality of segment regions (24) having the second conductivity type (P),
wherein the gate electrode extends in a first direction,
wherein a first source region (left) of the plurality of source regions (11) is spaced apart from a second source region (central) of the plurality of source regions (11) in a first direction,
wherein each of the plurality of transistor sets further includes:
a source electrode (Vss) connected in common to the plurality of source regions (11); and
a drain electrode (PAD) connected in common to the plurality of drain regions (12), and
wherein, the transistor set includes a central region and a peripheral region that surrounds the central region and excludes the central region and a boundary region (16). (See FIGs. 2A-B).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the first MOFET of WILLIAMS having the plurality of transistor set as taught by RISAKI to cause uniform current to flow through all channels of all transistors.
Further KER teaches a power management integrated circuit including a first MOSFET (NMOS) (30),
wherein the first MOSFET (30) includes a plurality of transistor sets that are two-dimensionally arranged,
wherein the transistor set of the plurality of transistor sets includes a source region (S), a drain region (D), and a gate electrodes (G) between the source region (S) and the drain region (D),
wherein the source region (S) further includes a plurality of segment regions (40) having the second conductivity type (P),
wherein the plurality of segment regions (40) are spaced apart from each other along the first direction, and
wherein the transistor set a central region and a peripheral region that surrounds the central region, and
a first density of the plurality of segment regions (40) per unit area in the central region is greater than a second density of the plurality of segment regions (40) per unit aera in the peripheral region. (See FIGs. 6A-C, 7A-B).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the plurality of the source region of WILLIAMS, in view of RISAKI, having the first density of the plurality of segment regions per unit area in the central region being greater than the second density of the plurality of segment regions per unit area in the peripheral region as taught by KER for the same intended purpose of providing back gate contact.
With respect to claim 14, in view of RISAKI, the transistor set further includes:
a source electrode (Vss) electrically connected to the source region (11); and
a drain electrode (PAD) electrically connected to the drain region (12),
in view of KER, wherein a first density of the plurality of segment regions (40) in a zone between the source electrode and the drain electrode is greater than a second density of the plurality of segment regions in a remaining zone other than the zone.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over WILLIAMS ‘994 RISAKI ‘944 and KER ‘900 as applied to claim 1 above, and further in view of YASUHARA et al. (US. Pub. No. 2011/0068406) of record.
WILLIAMS, in view of RISAKI and KER, teaches the power management integrated circuit as described in claim 1 above including: the first impurity regions (11) of the source regions (11) and the plurality of segment regions (24) of the source regions (11) are connected at a same potential through a contact (Vss).
Thus, WILLIAMS, RISAKI and KER are shown to teach all the features of the claim with the exception of explicitly disclosing a silicide layer on each of the source regions.
However, YASUHARA teaches a power management integrated circuit including:
a silicide layer (not numbered) on each of source regions (21), wherein the first impurity regions of the source regions (21) and the plurality of segment regions (22) of the source regions (21) are connected at a same potential through the silicide layer. (See FIG. 2).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the contact of KER having the silicide layer on each of source regions as taught by YASUHARA to reduce contact resistance.
Response to Arguments
Applicant’s arguments with respect to amended claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANH D MAI/Primary Examiner, Art Unit 2893
