DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Applicant’s election without traverse of Species 2, as shown FIG. 12, in the reply filed on January 12, 2026 is acknowledged.
Applicant identified claims 1-6, 8-14, 16 and 18-20 are readable on the elected Species. Non-Elected Species, claims 7, 15 and 17 have been withdrawn from consideration. Claims 1-20 are pending.
Claim 5 recites: “wherein a size of the first segment region is greater than a size of the second segment region”.
However, the elected Species, FIG. 12, the size of the first segment region and the second segment region is the same.
Claim 5 directs to non-elected Species. Therefore, claim 5 is effectively withdrawn from consideration.
Claims 13 and 18 recite the similar limitation. Therefore, claims 13 and 18 are effectively withdrawn from consideration.
Thus, Claims 5, 7, 13, 15 and 17-18 have been withdrawn from consideration.
Action on merits of the Elected Species, claims 1-4, 6, 8-12, 14, 16 and 19-20 follows.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 16, 2023; January 05, 2024, January 06, 2025 and February 12, 2026 have been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
A POWER MANAGEMENT INTEGRATED CIRCUIT HAVING A PLURALITY OF SEGMENT REGIONS OF A SECOND CONDUCTIVITY TYPE FORMED WITHIN EACH OF A PLURALITY OF SOURCE REGIONS OF A FIRST CONDUCTIVITY TYPE
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 9 is rejected under 35 U.S.C. 112(d) as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 9 recites: the power management integrated circuit of claim 1, wherein the plurality of segment regions are configured to prevent a drop in a snapback breakdown voltage of a transistor set which includes the plurality of segment regions.
The limitation: “are configured to prevent a drop in a snapback breakdown voltage of a transistor set which includes the plurality of segment regions” is the function of the plurality of segment region.
The function of the plurality of segment regions do not further limit the segment regions, structurally.
Therefore, claim 9 fails to further limit the structure of claim 1.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, 9-12, 14, 16 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KER et al. (US. Pub. No. 2004/0070900).
With respect to claim 1, KER teaches a power management integrated circuit as claimed comprising a buck converter that includes a first metal oxide semiconductor field effect transistor (MOSFET) having a first conductivity type (NMOS) and a second MOSFET having a second conductivity type (PMOS),
wherein the first MOSFET includes a plurality of transistor sets that are two- dimensionally arranged,
wherein each of the plurality of transistor sets includes a plurality of source regions (S), a plurality of drain regions (D), and a plurality of gate electrodes (G) between the plurality of source regions (S) and the plurality of drain regions (D),
wherein each of the plurality of source regions (S) and each of the plurality of drain regions (D) includes an impurity region having the first conductivity type (N),
wherein each of the plurality of source regions (S) further includes a plurality of segment regions (40) having the second conductivity type (P),
wherein a first source region (S, left)) of the plurality of source regions is spaced apart from a second source region (S, central) of the plurality of source regions in a first direction (B), and
wherein a first number of the plurality of segment regions (40) in the first source region (S, central) is different from a second number of the plurality of segment regions (40) in the second source region (S, left). (See FIGs. 6A-C, 7A-B).
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With respect to claim 2, the first number (S. central) of KER is greater than the second number (S, left), and the first source region (S) is closer than the second source region to a center of the transistor set which includes the first source region and the second source region.
With respect to claim 3, each of the plurality of gate electrodes (G) extends in a second direction (A) that intersects the first direction (B), and each of the plurality of segment regions (40) are spaced apart from each other along the second direction (A).
With respect to claim 4, each of the plurality of transistor sets of KER includes a central region (central) and a peripheral region (left, right) that surrounds the central region, and a first density of the plurality of segment regions (40) in the central region is greater than a second density of the plurality of segment regions (40) in the peripheral region.
With respect to claim 6, each of the plurality of transistor sets of KER further includes:
a source electrode (36) electrically connected to the plurality of source regions (S); and
a drain electrode (36) electrically connected to the plurality of drain regions (D),
wherein a first density of the plurality of segment regions (40) in a zone between the source electrode and the drain electrode is greater than a second density of the plurality of segment regions (40) in a remaining zone other than the zone.
With respect to claim 9, the plurality of segment regions (40) of KER are configured to prevent a drop in a snapback breakdown voltage of a transistor set which includes the plurality of segment regions.
The limitation: “are configured to prevent a drop in a snapback breakdown voltage of a transistor set which includes the plurality of segment regions” is the function of the plurality of segment region.
Since the power management integrated circuit of KER comprises the plurality of segment regions, the limitation is met.
With respect to claim 10, each of the plurality of source regions (S) of KER further includes a lightly doped impurity region (not numbered) below a corresponding gate electrode (G) of the plurality of gate electrodes, the lightly doped impurity region having the first conductivity type (N), when a transistor set is operated, a current flows from a drain region (D) toward a corresponding source region (S), and the current bypasses the plurality of segment regions (40) of the corresponding source region (S) and flows through the lightly doped impurity region toward the corresponding source region (S).
With respect to claim 11, KER teaches a power management integrated circuit comprising a buck converter that includes a first metal oxide semiconductor field effect transistor (MOSFET) having a first conductivity type (NMOS) and a second MOSFET having a second conductivity type (PMOS),
wherein the first MOSFET includes a plurality of transistors sets that are two- dimensionally arranged,
wherein a transistor set of the plurality of transistor sets includes a source region (not numbered) , a drain region (not numbered), and a gate electrode (not numbered) between the source region and the drain region,
wherein each of the source region and the drain region includes an impurity region having the first conductivity type (N), wherein the source region further includes a plurality of segment regions (40) having the second conductivity type (P),
wherein the gate electrode extends in a first direction, and
wherein the plurality of segment regions (40) are spaced apart from each other along the first direction. (See FIG. 6A-C, 7A-B).
With respect to claim 12, the transistor set of KER includes a central region and a peripheral region that surrounds the central region, and a first density of the plurality of segment regions (40) in the central region is greater than a second density of the plurality of segment regions (40) in the peripheral region.
(W) With respect to claim 13, the transistor set of KER includes a central region and a peripheral region that surrounds the central region,
wherein the plurality of segment regions (40) include: a first segment region (40) in the central region; and
a second segment region in the peripheral region, wherein a size of the first segment region is greater than a size of the second segment region.
With respect to claim 14, the transistor set of KER further includes: a source electrode (36) electrically connected to the source region; and a drain electrode (36) electrically connected to the drain region, wherein a first density of the plurality of segment regions (40) in a zone between the source electrode and the drain electrode is greater than a second density of the plurality of segment regions in a remaining zone other than the zone.
With respect to claim 15, the transistor set of KER further includes a guard ring region (38) that surrounds a boundary of the transistor set, the guard ring region (38) having the second conductivity type.
With respect to claim 16, KER teaches a power management integrated circuit as claimed including:
source regions (S) and drain regions (S) that are alternately disposed in a first direction (B) on a substrate (38);
gate electrodes (G) correspondingly between the source regions (S) and the drain regions (D);
a source electrode (36) connected in common to the source regions (S); and
a drain electrode (36) connected in common to the drain regions (D),
wherein each of the source regions (S) and each of the drain regions (D) includes a first impurity region having a first conductivity type (N),
wherein each of the source regions (S) further includes a second impurity region (40) having a second conductivity type (P),
wherein the second impurity region includes a plurality of segment regions (40) that are spaced apart from each other, and
wherein a first density of the plurality of segment regions (40) in a zone between the source electrode and the drain electrode is greater than a second density of the plurality of segment regions (40) in a remaining zone other than the zone. (See FIG. 6A)
With respect to claim 20, each of the source regions (S) of Ker further includes a lightly doped impurity region (not numbered) below a corresponding gate electrode (G), the lightly doped impurity region having the first conductivity type (N), a current flows from a drain region (D) toward a corresponding source region (S), and the current bypasses the plurality of segment regions (40) of the corresponding source region (S) and flows through the lightly doped impurity region toward the corresponding source region (S). (See FIG. 6B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over KER ‘900 as applied to claims 1 and 16 above, and further in view of YASUHARA et al. (US. Pub. No. 2011/0068406) of record.
KER teaches the power management integrated circuit as described in claim 16 above including: the first impurity regions (34) of the source regions (S) and the plurality of segment regions (40) of the source regions (S) are connected at a same potential through a contact (36).
Thus, KER is shown to teach all the features of the claim with the exception of explicitly disclosing a silicide layer on each of the source regions.
However, YASUHARA teaches a power management integrated circuit including:
a silicide layer (not numbered) on each of source regions (21), wherein the first impurity regions of the source regions (21) and the plurality of segment regions (22) of the source regions (21) are connected at a same potential through the silicide layer. (See FIG. 2).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the contact of KER having the silicide layer on each of source regions as taught by YASUHARA to reduce contact resistance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 10:00-4:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue A Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANH D MAI/Primary Examiner, Art Unit 2893
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