DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Style
In this action unitalicized bold is used for claim language, while italicized bold is used for emphasis.
Applicant Reply
“The claims may be amended by canceling particular claims, by presenting new claims, or by rewriting particular claims as indicated in 37 CFR 1.121(c). The requirements of 37 CFR 1.111(b) must be complied with by pointing out the specific distinctions believed to render the claims patentable over the references in presenting arguments in support of new claims and amendments. . . . The prompt development of a clear issue requires that the replies of the applicant meet the objections to and rejections of the claims. Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06. . . . An amendment which does not comply with the provisions of 37 CFR 1.121(b), (c), (d), and (h) may be held not fully responsive. See MPEP § 714.” MPEP § 714.02. Generic statements or listing of numerous paragraphs do not “specifically point out the support for” claim amendments. “With respect to newly added or amended claims, applicant should show support in the original disclosure for the new or amended claims. See, e.g., Hyatt v. Dudas, 492 F.3d 1365, 1370, n.4, 83 USPQ2d 1373, 1376, n.4 (Fed. Cir. 2007) (citing MPEP § 2163.04 which provides that a ‘simple statement such as ‘applicant has not pointed out where the new (or amended) claim is supported, nor does there appear to be a written description of the claim limitation ‘___’ in the application as filed’ may be sufficient where the claim is a new or amended claim, the support for the limitation is not apparent, and applicant has not pointed out where the limitation is supported.’)” MPEP § 2163(II)(A).
Election/Restrictions
Applicant’s election of group II in the reply filed on 07/20/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse. See MPEP § 818.01(a). The remarks indicate that Applicant wishes to elect with traverse. However, the Remarks fail to specifically point out any supposed errors in the restriction requirement. See Response to Election/Restriction filed 07/20/2026 PP. 1-2. “As indicated in the first sentence of 37 CFR 1.143, the traverse to a requirement for restriction must be complete as required by 37 CFR 1.111(b). Under this rule, the applicant is required to specifically point out the reason(s) on which he or she bases his or her conclusion(s) that a requirement to restrict is in error. A mere broad allegation that the requirement is in error does not comply with the requirement of 37 CFR 1.111. Thus the required provisional election (see MPEP § 818.01(b)) becomes an election without traverse if accompanied by an incomplete traversal of the requirement for restriction.” MPEP § 818.01. Therefore, Applicants Response is an election without traverse. See also MPEP § 818.01(c) (“To preserve the right to petition from the requirement for restriction, including an election of species requirement, all errors to be relied upon in the petition must be distinctly and specifically pointed out in a timely filed traverse by the applicant. The petition may be deferred until after final action on or allowance of the claims to the elected invention. In any event, the petition must not be filed later than the filing date of the notice of appeal. If applicant does not distinctly and specifically point out supposed errors in the restriction requirement, the election should be treated as an election without traverse and be so indicated to the applicant by use of form paragraph 8.25.02.”).
Claims 1, 5-12, 19 and 21 are examined. Claims 1, 19, and 21 are generic. Claims 6-12 have been elected. Claim 5 is directed to a different species than claims 6-12, but examination of claim 5 without additional claims directed to further details of this species does not result in an undue examination burden. Applicant has elected group II drawn to techniques for determining whether a subcircuit can be replaced with a program, classified in G06N10/20 (Models of quantum computing, e.g. quantum circuits or universal quantum computers.). Applicant has not elected Group I drawn to removing or replacing gates in a quantum circuit; Group III drawn to techniques of testing the modified circuit to determine whether a modification was successful, or Group IV drawn to compilation of quantum subcircuits. Likewise, Applicant has not elected to pursue an invention directed to details of inverting qubits, as recited in claim 5. Applicant is reminded that the Office does not permit shift. Claims amended to include non-elected species will not be examined.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 5-12, 19, and 21 are rejected are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Generally: separately listed claim elements are construed as distinct components, all claim terms must be given weight, and there is presumed to be a difference in meaning and scope when different words or phrases are used in separate claims. Since different term or phrases are presumed to differ in scope and each term or phrase in the claims must find clear support in the description, a description of a single element in the Specification may fail to support multiple claim terms. “[C]laims must ‘conform to the invention as set forth in the remainder of the specification and the terms and phrases used in the claims must find clear support or antecedent basis in the description so that the meaning of the terms in the claims may be ascertainable by reference to the description.’ 37 C.F.R. § 1.75(d)(1).” Phillips v. AWH Corp., 415 F.3d 1303, 1316 (Fed. Cir. 2005) (as cited in MPEP § 2111). Further, a lack of lack of detail in the Specification describing how a claimed result is achieved can support a finding that the Applicant was not in possession of the claimed invention at the time of filing, notwithstanding verbatim support. “It is not enough that one skilled in the art could write a program to achieve the claimed function because the specification must explain how the inventor intends to achieve the claimed function to satisfy the written description requirement. See, e.g., Vasudevan Software, Inc. v. MicroStrategy, Inc., 782 F.3d 671, 681-683, 114 USPQ2d 1349, 1356, 1357 (Fed. Cir. 2015) (reversing and remanding the district court’s grant of summary judgment of invalidity for lack of adequate written description where there were genuine issues of material fact regarding "whether the specification show[ed] possession by the inventor of how accessing disparate databases is achieved"). If the specification does not provide a disclosure of the computer and algorithm in sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the invention a rejection under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, for lack of written description must be made.” MPEP § 2161.01(I). “An original claim may lack written description support when (1) the claim defines the invention in functional language specifying a desired result but the disclosure fails to sufficiently identify how the function is performed or the result is achieved[.] See Ariad Pharms., Inc. v. Eli Lilly & Co., 598 F.3d 1336, 1349-50 (Fed. Cir. 2010) (en banc). The written description requirement is not necessarily met when the claim language appears in ipsis verbis in the specification. ‘Even if a claim is supported by the specification, the language of the specification, to the extent possible, must describe the claimed invention so that one skilled in the art can recognize what is claimed. The appearance of mere indistinct words in a specification or a claim, even an original claim, does not necessarily satisfy that requirement.’” MPEP § 2163.03.
All independent claims substantially recite “the portion of the quantum circuit is configured to prepare one or more input values on one or more input qubits of the quantum circuit, the portion of the quantum circuit is configured to produce an output value based on a manipulation of the one or more input qubits when having the one or more input values[.]” The claims appear to recite a portion of a quantum circuit (simulation) preparing input values the quantum circuit of which it is a portion. This seems to recite a circuit carrying out preparations for a qubit to be used as an input to the circuit used for its own preparations. While there is nothing fundamentally wrong with running a qubit through a circuit twice in a row, there is a lack of detail in how this is accomplished or even making clear that this is what the applicant has invented. Further, there is no description of any operations required to “prepare” the “one or more input values on one or more qubits” or any explanation of how the claimed “portion of a quantum circuit” would be “configured” to do so. Without any details as to the implementation of this unlikely set of operations, the disclosure taken as a whole supports a finding that a “portion of the quantum circuit” so configured was not in applicant’s possession as of the effective filing date.
Claim 7 recites “wherein the subcircuit is configured to produce the output value, wherein the set program comprises a quantum state setter that prepares the output value.” The claimed “quantum state setter” is not described at all in the Specification and is not a known term of art. In place of a description, the Specification purports to incorporate support by indicating “a quantum state setter may be disclosed in U.S [sic] Patent Application No. 17,752,282 [sic][.]” Spec. ¶100. Notwithstanding Applicant’s assertion, no support for any objective meaning attributable to this term was found in this U.S. Application 17/752,282. Of particular note was the explanation that “the testing quantum circuit may be generated to comprise one or more quantum state setters ('setters') for setting initial quantum states of input qubits[.]” ‘282 App. Spec. ¶56. That is, the only explanation of a “state setter” is that it sets a state. Mere indistinct words in the Specification are not a substitute for a supporting description of claim elements. If the ‘282 application includes a more detailed description of a “state setter” the exact language may be pasted into Applicant’s reply, and properly cited. A response that merely alludes to another reference without citing any specific language describing the claim element, or merely invokes the understanding of one of ordinary skill without providing any supporting evidence, is unlikely to be productive.
All dependent claims are rejected as containing the limitations of the claims from which they depend.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 5-12, 19, and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Generally: separately listed claim elements are construed as distinct components, that all claim terms must be given weight, there is presumed to be a difference in meaning and scope when different words or phrases are used in separate claims, and repeated and consistent descriptions in the specification indicate the proper scope of a claimed term. “[C]laims must ‘conform to the invention as set forth in the remainder of the specification and the terms and phrases used in the claims must find clear support or antecedent basis in the description so that the meaning of the terms in the claims may be ascertainable by reference to the description.’ 37 C.F.R. § 1.75(d)(1).” Phillips v. AWH Corp., 415 F.3d 1303, 1316 (Fed. Cir. 2005) (as cited in MPEP § 2111). Therefore, use of two different terms in the claims that both rely on the description of a single structure in the Specification may render at least one term indefinite because there is no way to determine which term should be construed in view of the description of the single structure.
All independent claims recite “obtaining quantum state data that is determined based on a simulation of a portion of a quantum circuit, the quantum circuit is configured to manipulate a plurality of qubits over a plurality of cycles using a plurality of gates, the portion of
the quantum circuit is configured to prepare one or more input values on one or more input qubits of the quantum circuit, the portion of the quantum circuit is configured to produce an output value based on a manipulation of the one or more input qubits when having the one or more input values, the quantum state data comprising the one or more input values and the output value[.]” It is not clear whether the “portion of a quantum circuit” refers to the simulation recited in line 2 of claim 1, or if “the portion of a quantum circuit” refers to something other than the simulation. Claim 1 recites “obtain quantum state data that is determined based on a simulation of a portion of a quantum circuit[.]” Claim 1 then recites various operations using “the portion of the quantum circuit” resulting in quantum state data. The omission of the “simulation” in the operations leading to obtaining a quantum state makes it unclear the “portion of a quantum circuit” refers to a simulation.
All independent claims substantially recite “the portion of the quantum circuit is configured to prepare one or more input values on one or more input qubits of the quantum circuit, the portion of the quantum circuit is configured to produce an output value based on a manipulation of the one or more input qubits when having the one or more input values[.]” The claims appear to recite a portion of a quantum circuit (simulation) preparing input values the quantum circuit of which it is a portion. This seems to recite a circuit carrying out preparations for a qubit to be used as an input to the circuit used for its own preparations. While there is nothing fundamentally wrong with running a qubit through a circuit twice in a row, there is a lack of detail in how this is accomplished. Further, there is no description of any operations required to “prepare” the “one or more input values on one or more qubits” or any explanation of how the claimed “portion of a quantum circuit” would be “configured” to do so. Without any details how a portion of a quantum circuit is configured to prepare its own input values, the metes and bounds of the claim cannot reasonably be determined. This language could also be read as referring to a portion of a quantum circuit inputting and outputting values within the circuit, which is seem closer to the description in the Specification, though this interpretation requires “prepare on or more input values” to be read as an action taken by the portion of the quantum circuit on the input value. Since there are at least two similarly reasonable interpretations when the claim language is read in view of the Specification, the claim is indefinite.
All independent claims substantially recite “obtaining quantum state data that is determined based on a simulation of a portion of a quantum circuit . . . executing the modified quantum circuit on a quantum computer.” The “simulation” is understood to take place on a binary (conventional) computer and the executing “on a quantum computer” is understood to take place on quantum hardware. But it is not clear whether the middle section of the claims refers to operations taking place on a quantum computer or taking place on a conventional binary computer. The omission of “simulation” before the “portion of a quantum” tends to be more consistent with implementation on a quantum circuit, because the quantum aspects are no longer simulated on a binary computer. Similarly, the “prepar[ing] one or more input values on one or more qubits” is consistent with an operation being implemented using quantum hardware. But the first recitation of “a quantum computer” is in the last line of the claims. Further, the terms “input” and “output” with respect to a quantum circuit is more consistent with a quantum circuit diagram (simulation) that represents qubits as lines being input and output to/from various gates. Based on the foregoing, it is not clear whether the claim, up until the “executing . . . on a quantum computer,” is reciting quantum operations or simulations thereof.
Claim 1 recites “a portion of a quantum circuit[.]” Claims 6-8 recite “a subcircuit of the quantum circuit[.]” Different terms imply different claim elements. But both elements are merely limited to being less than the whole of the quantum circuit. Without any way of distinguishing the scope of the terms, they could reasonably refer to the same element. This makes it unclear whether the “subcircuit” of claims 6-8 must be different from the “portion” of claim 1.
Claim 7 recites “wherein the subcircuit is configured to produce the output value, wherein the set program comprises a quantum state setter that prepares the output value.” The claimed “quantum state setter” is not described at all in the Specification and is not a known term of art. In place of a description, the Specification purports to incorporate support by indicating “a quantum state setter may be disclosed in U.S [sic] Patent Application No. 17,752,282 [sic][.]” Spec. ¶100. Notwithstanding Applicant’s assertion, no support for any objective meaning attributable to this term was found in this U.S. Application 17/752,282. Of particular note was the explanation that “the testing quantum circuit may be generated to comprise one or more quantum state setters ('setters') for setting initial quantum states of input qubits[.]” ‘282 App. Spec. ¶56. That is, the only explanation of a “state setter” is that it sets a state. Mere indistinct words in the Specification are insufficient to provide an objective measure of applicant invented terms. If the ‘282 application includes a more detailed description of a “state setter” the exact language may be pasted into Applicant’s reply, and it will be evaluated to determine whether the term is definite in view of the more detailed description. Merely alluding to another reference without citing any specific language describing the claim element is unlikely to be productive.
All dependent claims are rejected as containing the limitations of the claims from which they depend.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 5-12, 19, and 21 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) and the claims as a whole, considering all claim elements both individually and in combination, do not amount to significantly more.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
All claims are found to be directed to one of the four statutory categories, unless otherwise indicated in this action.
Step 2A Prongs One and Two (Alice Step 1): According to Office guidance, claims that read on math do not recite an abstract idea at step 2A1, when the claims fail to refer to the math by name.1 The MPEP also equates “recit[ing] a judicial exception” with “state[ing]” or “describ[ing]” an abstract idea in the claims.2 Consistent with this guidance, an abstract idea may be first recited in a dependent claim even though the independent claims read on that abstract idea. Claim limitations which recite any of the abstract idea groupings set forth in the manual are found to be directed, as a whole, to an abstract idea unless otherwise indicated.3 The claims do not recite additional elements that integrate the abstract ideas into a practical application.4 To confer patent eligibility to an otherwise abstract idea, claims may recite a specific means or method of solving a specific problem in a technological field.5
Independent Claims
1. A method comprising: obtaining quantum state data that is determined based on a simulation of a portion of a quantum circuit, (Determining which quantum state data to obtain reads on a mental/mathematical process. The obtaining of the quantum state data is mere extra solution activity. Using a generic “simulation” is merely an instruction to apply the mental/mathematical process using conventional computing components.) the quantum circuit is configured to manipulate a plurality of qubits over a plurality of cycles using a plurality of gates, (The claimed manipulation of qubits using gates reads on generic mathematical operations.) the portion of the quantum circuit is configured to prepare one or more input values on one or more input qubits of the quantum circuit, (The Specification does not describing preparation input values. As best understood, preparing input values reads on mathematical operations.) the portion of the quantum circuit is configured to produce an output value based on a manipulation of the one or more input qubits when having the one or more input values, (Producing an output value reads on a mathematical process.) the quantum state data comprising the one or more input values and the output value; (This merely designates a name for the input and output values, but does not structurally or functionally limit the claimed invention.) based on the quantum state data, determining a modification of the quantum circuit; (Determining a modification of a quantum circuit reads on a mental/mathematical process.) based on said determining the modification of the quantum circuit, generating a modified quantum circuit, (Generating a quantum circuit reads on a mental/mathematical process. Note that a “quantum circuit” in this art area reads on a description of quantum operations and relationships (i.e. a schematic of a quantum algorithm).) the modified quantum circuit is configured to produce the output value; (Inputting and outputting data is mere extra-solution activity.) and executing the modified quantum circuit on a quantum computer. (This is an instruction to apply the abstract ideas using conventional computing components.)
Independent claim 19 is rejected for the reasons given in the rejection of claim 1. The claim also recites “An apparatus comprising a processor and coupled memory, said processor being adapted to” implement the method of claim 1. This is merely an instruction to apply the judicial exception on a computer.
Independent claim 21 is rejected for the reasons given in the rejection of claim 1. The claim also recites “A computer program product comprising a non-transitory computer readable medium retaining program instructions, which program instructions when read by a processor, cause the processor to” implement the method of claim 1. This is merely an instruction to apply the judicial exception on a computer.
Step 2B (Alice Step 2): The rejected claims do not recite additional elements that amount to significantly more than the judicial exception.
All additional limitations that do not integrate the claimed judicial exception into a practical application also fail to amount to significantly more, for the reasons given at step 2A2. All limitations found to be extra-solution activity at step 2A2 are found to be WURC, including limitations that read on mere data gathering, data storage, and data input/output/transfer. The limitations of “obtaining quantum state data” and “produce[ing] the output value” recite extra-solution activity. Should any other claim limitations be rejected at step 2A1 as extra-solution activity but omitted in the section directly above, it should be understood that such limitations are also found to be WURC at this step. Generic data input/output, storage, repetitive processing operations, and generic display of information and have been found to be generic WURC operations that do not transform the abstract idea into patent eligible subject matter, at the Alice step two analysis.6 Other aspects of generic computing have also been found to be WURC.7 Further, the description itself may provide support for a finding that claim elements are WURC. The analysis under § 112(a) as to whether a claim element is “so well-known that it need not be described in detail in the patent specification” is the same as the analysis as to whether the claim element is widely prevalent or in common use.8 Similarly, generic descriptions in the Specification of claimed components and features has been found to support a conclusion that the claimed components were conventional.9 Improvements to the relevant technology may support a finding that the claims include a patent eligible inventive concept. But some mechanism that results in any asserted improvements must be recited in the claim, and the Specification must provide sufficient details such that one of ordinary skill in the art would recognize the claimed invention as providing the improvement.10 This applies to the dependent claims below.
Dependent Claims:
5. The method of Claim 1, wherein said determining the modification comprises determining that, when the quantum circuit is set with the one or more input values on the one or more input qubits, a qubit of the quantum circuit can be reused, the quantum state data comprising a quantum state value of the qubit, (This merely further limits the mental process of “determining.”) wherein the modified quantum circuit is generated by inversing the quantum state value on the qubit. (Generating a modified quantum circuit by inversing a quantum state reads on performing a mathematical operation.)
6. The method of Claim 1, wherein said determining the modification comprises determining that, when the quantum circuit is set with the one or more input values on the one or more input qubits, a subcircuit of the quantum circuit can be replaced with a set program, (This merely further limits the mental process of “determining.”) wherein the modified quantum circuit is generated by replacing the subcircuit with the set program. (This reads on replacing a portion of a quantum circuit, that is, replacing a portion of a diagram, with a “set program” in the diagram. This reads on a mental process. Note that the “set program” is designed in the specification as an addition to the quantum circuit. See Spec. ¶41 (“the set program may be added to the quantum circuit, such as by concatenating the set program to a beginning of the quantum circuit.”))
7. The method of Claim 6, wherein the subcircuit is configured to produce the output value, wherein the set program comprises a quantum state setter that prepares the output value. (Again, this merely recites a configuration of a quantum circuit, which is merely a diagram of qubits and associated gates/operators. Configuring or modifying a quantum circuit, as that term is used in this art area, is a mental process.)
8. The method of Claim 6, wherein said determining that the subcircuit can be replaced with the set program is performed based on an identification that the subcircuit does not divide any purity sets, the identification is based on the quantum state data. (This merely limits the mental process of determining. Note that the recited “identification” is also a mental process.)
9. The method of Claim 8, wherein the identification is based on a pure decomposition graph that is generated based on the quantum state data, (Basing an identification off of a graph is a mental process. Generating a graph from quantum state data reads on a mental/mathematical process.) wherein the pure decomposition graph indicates, for each stage of the simulation, which qubits of the quantum circuit belong to which purity sets. (This merely limits the mental/mathematical process of generating a graph to a field of use corresponding to a particular data environment.)
10. The method of Claim 9, wherein first and second qubits belong to a same purity set, wherein the first and second qubits are entangled with each other, wherein the first and second qubits are not entangled with any other qubit of the plurality of qubits. (This limits the graph structure to indicate qubits which are entangled with each other without being entangled with other qubits. Further limiting the graph merely limits the associated mental process, to a particular data environment associated with a field of use.)
11. The method of Claim 9, wherein each of the qubits of the quantum circuit comprises an individual qubit or a qubit register. (The recited “quantum circuit [that] comprises an individual qubit or a qubit register” reads on logical qubits. Therefore, this limitation merely limits the mental/mathematical process associated with configuring the quantum circuit (diagram.))
12. The method of Claim 9, wherein the pure decomposition graph comprises a Directed Acyclic Graph (DAG). (This merely limits the mental process associated with the graph to a particular field of use.)
All dependent claims are rejected as containing the material of the claims from which they depend.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-7, 19, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Liu (QContext: Context-Aware Decomposition for Quantum Gates; 7 Feb, 2023) and Younis (Quantum Circuit Optimization and Transpilation via Parameterized Circuit Instantiation, 2022).
1. A method comprising: obtaining quantum state data that is determined based on a simulation of a portion of a quantum circuit, (“QContext provides both topology-aware and context-aware decomposition. QContext provides both topology aware and context aware decomposition. QcContext first finds the gate decomposition variants compatible with the target hardware topology.” Liu P. 1.
While implied by the concepts taught in Liu, Liu does not expressly state that the quantum state data determined based on a simulation of a portion of a quantum circuit is obtained.
Younis teaches “Instantiation is the core subroutine in all bottom-up circuit synthesis algorithms. The standard bottom-up loop (left) is to create an initial circuit template guess then continue to instantiate and extend it until an acceptable solution is found.” Younis, P. 488, description of Fig. 2. See also Younis P. 488, Algorithm 1. “Since methodologies that use numerical instantiation scale
exponentially with the size of the system being instantiated, we employ the circuit partitioning procedure described by Wu et al [13] to ensure competitive performance and scalability, see Figure 6. For large circuits, we partition in smaller blocks which we can optimize (delete gates) or transpile directly, transform the blocks and reassemble the original circuit.” Younis P. 469, Col. 1. “There is a trade-off present with the size of partitions. . . . With both algorithms, larger block sizes will likely lead to better quality results but smaller block sizes will complete quicker.” Younis P. 469, Col. 1-2.
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teaching of Younis because this is part of a technique used to determine whether changes to the circuit have an acceptable error rate.
With respect to claims 19 and 21, note that one of ordinary skill in the art would understand the techniques of Liu and Younis to be run using conventional computing components such as software stored in memory and run on a processor. Note also the source code in Younis.) the quantum circuit is configured to manipulate a plurality of qubits over a plurality of cycles using a plurality of gates, (See Liu Fig. 1.) the portion of the quantum circuit is configured to prepare one or more input values on one or more input qubits of the quantum circuit, the portion of the quantum circuit is configured to produce an output value based on a manipulation of the one or more input qubits when having the one or more input values, (As best understood, preparing input and output values refers to modifying values that are input and output to/from the portion of the quantum circuit. Liu explains various “portion(s)” (i.e. sets of gates) in a quantum circuit that are removed or replaced. Note that portions of quantum circuits have inputs and outputs. See e.g. Liu Fig. 1. Liu teaches techniques of modifying parts of the circuit, which by virtue of being in the circuit prepare input values and produce output values.) the quantum state data comprising the one or more input values and the output value; based on the quantum state data, determining a modification of the quantum circuit; (“Gate context represents the predecessors and the successors in the directed acyclic graph (DAG) representation of the circuit. Since the different gate contexts could induce different circuit optimization opportunities, the quantum gate decomposition should be aware of the context. Here we use an example to demonstrate the effectiveness of context-aware gate decomposition. When the Toffoli gate in Figure 1b is decomposed in the canonical template with six CNOT gates, there is no gate cancellation and circuit resynthesis opportunity. However, since the Toffoli gate is a self-inverse gate, inverting all gates in the canonical template will result in another decomposition template. As shown in Figure 1b, we can perform gate cancellation and two-qubit block resynthesis optimizations when decomposing the Toffoli with the inversed template.” Liu P. 1. See also Liu fig. 1, showing modification by cancellation and resynthesis. Liu further explains that gates in the circuit may be replaced with combinations that are natively supported by quantum hardware. “In order to run a quantum program on real hardware, the complex quantum gates need to be decomposed into the basis gates in an assembly language such as OpenQASM [9]. The basis gates in OpenQASM include single-qubit rotations and two-qubit CNOT gates. However, the CNOT gates may not be natively supported by the quantum devices. The basis gates in the assembly language should be decomposed into a sequence of native gates supported by the target hardware technology.” Liu P. 2. See also Liu P. 2, Fig. 1.) based on said determining the modification of the quantum circuit, generating a modified quantum circuit, the modified quantum circuit is configured to produce the output value; (“We propose a gate library that contains the gate decomposition variants for the Toffoli and CNOT gates. The gate library contains 32 Toffoli gate variants and 14 CNOT gate variants. Each gate variant is associated with a variant tag. The compiler species searches in the library and returns the best matching gate variant based on the hardware topology and the gate context. Then, the compiler performs circuit optimizations. After the optimizations, the basis gates need to be decomposed into native gates. For each CNOT gate in the circuit, the compiler finds the CNOT gate variant that minimizes the number of single-qubit rotations after optimization.” Liu P. 3.) and executing the modified quantum circuit on a quantum computer. (“QContext exploits the circuit information and the hardware topology to select the gate variant that increases circuit optimization opportunities.” Liu Abstract. On of ordinary skill in the art would understand that the circuit optimized for hardware as being ultimately executed on hardware.)
5. The method of Claim 1, wherein said determining the modification comprises determining that, when the quantum circuit is set with the one or more input values on the one or more input qubits, a qubit of the quantum circuit can be reused, the quantum state data comprising a quantum state value of the qubit, wherein the modified quantum circuit is generated by inversing the quantum state value on the qubit. (“We can generate the gate variants based on the circuit equivalence rules [15] and resynthesis. We used three strategies described below to find gate variants. . . . 1) Self-inverse: For the gates that are self-inverse, we can place the gates in the decomposition template in a reversed order and inverse each gate to get a new gate variant. Since the front layer of the circuit permutes with the last layer of the circuit, the variant tag after inversion is specified by permuting pre_tag with suc_tag. The opt tag changes from “O” to “I." Other self-inverse gates include the CNOT gate, SWAP gate, Bridge gate [23], and Fredkin gate [5].” Liu P. 4.)
6. The method of Claim 1, wherein said determining the modification comprises determining that, when the quantum circuit is set with the one or more input values on the one or more input qubits, a subcircuit of the quantum circuit can be replaced with a set program, wherein the modified quantum circuit is generated by replacing the subcircuit with the set program. (With respect to claim interpretation, the “subcircuit” is not interpreted to be structurally different than the “portion” of the quantum circuit of claim 1. Liu teaches: “In this paper we propose QContext, a new compiler structure that incorporates context-aware and topology-aware decompositions. Because of circuit equivalence rules and resynthesis, variants of a gate-decomposition template may exist. QContext exploits the circuit information and the hardware topology to select the gate variant that increases circuit optimization opportunities.” Liu Abstract. “We propose a gate library that contains the gate decomposition variants for the Toffoli and CNOT gates. The gate library contains 32 Toffoli gate variants and 14 CNOT gate variants. Each gate variant is associated with a variant tag. The compiler species searches in the library and returns the best matching gate variant based on the hardware topology and the gate context. Then, the compiler performs circuit optimizations. After the optimizations, the basis gates need to be decomposed into native gates. For each CNOT gate in the circuit, the compiler finds the CNOT gate variant that minimizes the number of single-qubit rotations after optimization.” Liu P. 3.)
7. The method of Claim 6, wherein the subcircuit is configured to produce the output value, wherein the set program comprises a quantum state setter that prepares the output value. (The “state setter” is not described in the Specification. The Specification cites application 17/752,282, which also does not provide a description of a quantum state setter. As best understood, the quantum gate setter changes the values of qubits. It must be noted that, without any guidance in the Specification, the interpretation of this applicant invented term requires significant speculation. In the interest of compact prosecution, a best-efforts mapping to the prior art is offered. See MPEP § 2143.03 (“However, an examiner should not simply speculate about the meaning of the claim language and then enter an obviousness rejection in view of that speculative interpretation. In re Steele, 305 F.2d 859,134 USPQ 292 (CCPA 1962) (The "considerable speculation" by the examiner and the Board as to the scope of the claims did not provide a proper basis for an obviousness rejection.). A claim should not be rejected over prior art just because it is indefinite. Ionescu, 222 USPQ at 540 (citing Steele).”) See rejection of claim 1. See also Younis Fig. 6 showing replacement of sections of a 5 qubit circuit, each limited to 3 qubits. The replacement of the first part of the original circuit in Fig. 6a. With “Block 1/2/3” shown in Fig. 6b is a replacement that prepares an output value. The motivation to combine in claim 1, applies here.)
Claims 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Liu, Younis, and Dou (QPanda: high-performance quantum computing framework for multiple application scenarios, 2022)
8. The method of Claim 6, wherein said determining that the subcircuit can be replaced with the set program is performed based on an identification that the subcircuit does not divide any purity sets, the identification is based on the quantum state data. (The previously cited art does not teach using a decomposition that separates qubits by purity set.
Dou teaches “QPanda utilizes the opt-bmt[43]mapping algorithm, which is suitable for the current NISQ situation where qubits are scarce, and the high depth of the circuit. The high fidelity of the quantum jobs mapped by opt-bmt[43]. Firstly, it transforms the circuit into a Directed Acyclic Graph (DAG: Directed Acyclic Graph) and then traverses from the node with in-degree 0 in the DAG. There will be N corresponding in-degrees for a circuit with N qubits.” Dou P. 11. “This circuit is mapped onto additional subcircuits. These subcircuits consist of two blocks without any qubits entanglement between them, thus transforming the N qubits simulation problem into a set of N/2 qubits subcircuits.” Dou P. 13.
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teaching of Dou because this technique for separating quantum circuits simplifies circuit simulation.
9. The method of Claim 8, wherein the identification is based on a pure decomposition graph that is generated based on the quantum state data, wherein the pure decomposition graph indicates, for each stage of the simulation, which qubits of the quantum circuit belong to which purity sets. (The previously cited art does not teach using a decomposition that separates qubits by purity set.
Dou teaches “QPanda utilizes the opt-bmt[43]mapping algorithm, which is suitable for the current NISQ situation where qubits are scarce, and the high depth of the circuit. The high fidelity of the quantum jobs mapped by opt-bmt[43]. Firstly, it transforms the circuit into a Directed Acyclic Graph (DAG: Directed Acyclic Graph) and then traverses from the node with in-degree 0 in the DAG. There will be N corresponding in-degrees for a circuit with N qubits.” Dou P. 11. “This circuit is mapped onto additional subcircuits. These subcircuits consist of two blocks without any qubits entanglement between them, thus transforming the N qubits simulation problem into a set of N/2 qubits subcircuits.” Dou P. 13.
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teaching of Dou because this technique for separating quantum circuits simplifies circuit simulation.
10. The method of Claim 9, wherein first and second qubits belong to a same purity set, wherein the first and second qubits are entangled with each other, wherein the first and second qubits are not entangled with any other qubit of the plurality of qubits. (See rejection of claim 9.)
11. The method of Claim 9, wherein each of the qubits of the quantum circuit comprises an individual qubit or a qubit register. (See rejection of claim 9. Note that a qubit register refers to a group of qubits and an individual qubit refers to a single qubit. Limiting a qubit to being one or being more than one reads on all possibilities, and is therefore non-limiting.)
12. The method of Claim 9, wherein the pure decomposition graph comprises a Directed Acyclic Graph (DAG). (See rejection of claim 9.)
For rejection of claims 19 and 21, see rejection of claim 1.
Conclusion
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PAUL M. KNIGHTPrimary ExaminerArt Unit 2148
/PAUL M KNIGHT/
Primary Examiner, Art Unit 2148
1 This distinction between claims which read on math and claims which recite an abstract idea is based on official USPTO Guidance. The 2019 Subject Matter Eligibility (SME) Examples instructs examiners that a claim reciting “training the neural network” where the background describes training as “using stochastic learning with backpropagation which is a type of machine learning algorithm that uses the gradient of a mathematical loss function to adjust the weights of the network” “does not recite any mathematical relationships, formulas, or calculations.” See 2019 SME Example 39, PP. 8-9 (emphasis added). In this example, the plain meaning of “training the neural network” read in light of the disclosure reads on backpropagation using the gradient of a mathematical loss function. See MPEP § 2111.01. In contrast, the 2024 SME Examples instructs examiners that a claim reciting “training, by the computer, the ANN . . . wherein the selected training algorithm includes a backpropagation algorithm and a gradient descent algorithm” does recite an abstract idea because “[t]he plain meaning of [backpropagation algorithm and gradient descent algorithm] are optimization algorithms, which compute neural network parameters using a series of mathematical calculations.” 2024 PEG Example 47, PP. 4-6. The Memorandum of August 4, 2025; Reminders on evaluating subject matter eligibility of claims under 35 U.S.C. 101, P. 3 also directs examiners that “training the neural network” recited in Example 39 merely “involve[s] . . . mathematical concepts” and contrasts claim 2 of example 47 as “referring to [specific] mathematical calculations by name[.]” (Emphasis added.)
2 “For instance, the claims in Diehr . . . clearly stated a mathematical equation . . . and the claims in Mayo . . . clearly stated laws of nature . . . such that the claims ‘set forth’ an identifiable judicial exception. Alternatively, the claims in Alice Corp. . . . described the concept of intermediated settlement without ever explicitly using the words ‘intermediated’ or ‘settlement.’” MPEP § 2106.04(II)(A).
3 “By grouping the abstract ideas, the examiners’ focus has been shifted from relying on individual cases to generally applying the wide body of case law spanning all technologies and claim types. . . . If the identified limitation(s) falls within at least one of the groupings of abstract ideas, it is reasonable to conclude that the claim recites an abstract idea in Step 2A Prong One.” MPEP § 2106.04(a). See also MPEP 2104(a)(2).
4 Step 2A prongs one and two are evaluated individually, consistent with the framework in the MPEP. Evaluation of relationships between abstract ideas and additional elements in one location promotes clarity of the record.
5 “In short, first the specification should be evaluated to determine if the disclosure provides sufficient details such that one of ordinary skill in the art would recognize the claimed invention as providing an improvement. The specification need not explicitly set forth the improvement, but it must describe the invention such that the improvement would be apparent to one of ordinary skill in the art. Conversely, if the specification explicitly sets forth an improvement but in a conclusory manner (i.e., a bare assertion of an improvement without the detail necessary to be apparent to a person of ordinary skill in the art), the examiner should not determine the claim improves technology. Second, if the specification sets forth an improvement in technology, the claim must be evaluated to ensure that the claim itself reflects the disclosed improvement. That is, the claim includes the components or steps of the invention that provide the improvement described in the specification. . . . It should be noted that while this consideration is often referred to in an abbreviated manner as the ‘improvements consideration,’ the word ‘improvements’ in the context of this consideration is limited to improvements to the functioning of a computer or any other technology/technical field, whether in Step 2A Prong Two or in Step 2B.” MPEP 2106.04(d)(1). See also Koninklijke KPN N.V. v. Gemalto M2M GmbH, 942 F.3d 1143, 1150-1152 (Fed. Cir. 2019).
6 See MPEP § 2106.05(d)(II) listing operations including “receiving or transmitting data,” “storing and retrieving data in memory,” and “performing repetitive calculations” as WURC. “The claims at issue do not require any nonconventional computer, network, or display components, or even a non-conventional and non-generic arrangement of known, conventional pieces, but merely call for performance of the claimed information collection, analysis, and display functions on a set of generic computer components and display devices.” Elec. Power Grp., LLC v. Alstom S.A., 830 F.3d 1350, 1355 (Fed. Cir. 2016) (emphasis added, internal quotes omitted).
7 “But ‘[f]or the role of a computer in a computer-implemented invention to be deemed meaningful in the context of this analysis, it must involve more than performance of 'well-understood, routine, [and] conventional activities previously known to the industry.’ Content Extraction, 776 F.3d at 1347-48 (quoting Alice, 134 S. Ct at 2359). Here, the server simply receives data, ‘extract[s] classification information . . . from the received data,’ and ‘stor[es] the digital images . . . taking into consideration the classification information.’ See ‘295 patent, col. 10 ll. 1-17 (Claim 17). . . . These steps fall squarely within our precedent finding generic computer components insufficient to add an inventive concept to an otherwise abstract idea. Alice, 134 S. Ct. at 2360 (‘Nearly every computer will include a 'communications controller' and a 'data storage unit' capable of performing the basic calculation, storage, and transmission functions required by the method claims.’); Content Extraction, 776 F.3d at 1345, 1348 (‘storing information’ into memory, and using a computer to ‘translate the shapes on a physical page into typeface characters,’ insufficient confer patent eligibility); Mortg. Grader, 811 F.3d at 1324-25 (generic computer components such as an ‘interface,’ ‘network,’ and ‘database,’ fail to satisfy the inventive concept requirement); Intellectual Ventures I, 792 F.3d at 1368 (a ‘database’ and ‘a communication medium’ ‘are all generic computer elements’); BuySAFE v. Google, Inc., 765 F.3d 1350, 1355 (Fed. Cir. 2014) (‘That a computer receives and sends the information over a network—with no further specification—is not even arguably inventive.’).” TLI Commc'ns LLC v. AV Auto., LLC, 823 F.3d 607, 614 (Fed. Cir. 2016), Emphasis Added.
8 “The analysis as to whether an element (or combination of elements) is widely prevalent or in common use is the same as the analysis under 35 U.S.C. 112(a) as to whether an element is so well-known that it need not be described in detail in the patent specification. See Genetic Techs. Ltd. v. Merial LLC, 818 F.3d 1369, 1377, 118 USPQ2d 1541, 1546 (Fed. Cir. 2016) (supporting the position that amplification was well-understood, routine, conventional for purposes of subject matter eligibility by observing that the patentee expressly argued during prosecution of the application that amplification was a technique readily practiced by those skilled in the art to overcome the rejection of the claim under 35 U.S.C. 112, first paragraph)[.]” MPEP § 2106.05(d)(I).
9 “Similarly, claim elements or combinations of claim elements that are routine, conventional or well-understood cannot transform the claims. (Citing BSG Tech LLC v. BuySeasons, Inc., 899 F.3d 1281, 1290-1291 (Fed. Cir. 2018)). When the patent's specification ‘describes the components and features listed in the claims generically,’ it ‘support[s] the conclusion that these components and features are conventional.’ Weisner v. Google LLC, 51 F.4th 1073, 1083-84 (Fed. Cir. 2022); see also Beteiro, LLC v. DraftKings Inc., 104 F.4th 1350, 1357-58 (Fed. Cir. 2024).” Broadband iTV, Inc. v. Amazon.com, Inc., 113 F.4th 1359 (Fed. Cir. 2024)
10 “If it is asserted that the invention improves upon conventional functioning of a computer, or upon conventional technology or technological processes, a technical explanation as to how to implement the invention should be present in the specification. That is, the disclosure must provide sufficient details such that one of ordinary skill in the art would recognize the claimed invention as providing an improvement. The specification need not explicitly set forth the improvement, but it must describe the invention such that the improvement would be apparent to one of ordinary skill in the art. Conversely, if the specification explicitly sets forth an improvement but in a conclusory manner (i.e., a bare assertion of an improvement without the detail necessary to be apparent to a person of ordinary skill in the art), the examiner should not determine the claim improves technology.” MPEP § 2106.05(a).
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