DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of Species 3 in the reply filed on 01/20/2026 is acknowledged. Claims 10,12,15 and 16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/20/2026 . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-6,11,13,19 and 21 are under 35 U.S.C. 103 as being unpatentable over Lin et al. (US20220367622A1) in view of Yin et al. ( US20220157969A1 ) . Regarding claim 1, Fig.24 of Lin teaches a semiconductor device comprising: an active pattern which includes a lower pattern 62 (para.0014) that extends in a first direction, and a plurality of sheet patterns 66 (para.0014) spaced apart from the lower pattern 62 in a second direction that is perpendicular to the first direction; a plurality of gate structures 122/124 (para.0015) which are on the lower pattern 62 and spaced apart from each other in the first direction, each gate structure 122/124 (para.0015) including a gate electrode 124 (para.0015) and a gate insulating film 122 (para.0015); and a source/drain pattern 98 (para.0015) which is between a pair of the gate structures 122/124 that are adjacent to each other in the first direction, the source/drain pattern 98 including a semiconductor liner film 98A (para.0053) and a semiconductor filling film 98C (para.0053) on the semiconductor liner film 98A, wherein the semiconductor liner film 98A (para.0054) and the semiconductor filling film 98C (para.0054) include silicon-germanium (para.0054, wherein the liner layers 98 B and the main layers 98 C in the p-type region 50 P are formed of boron-doped silicon germanium and wherein t he seed layers 98 A include materials from which the materials of the liner layers 98 B (e.g., boron-doped silicon germanium) ) , wherein the semiconductor liner film 98A includes an outer surface that is in contact with the plurality of sheet patterns 66, and an inner surface that faces the semiconductor filling film 98C, wherein a liner recess defined by the inner surface of the semiconductor liner film 98A includes a plurality of width extension regions (see annotated Fig.24), and wherein a width of each width extension region in the first direction increases and then decreases as a distance increases in the second direction from an upper surface of the lower pattern 62. Annotated Fig.24 Lin does not teach wherein a germanium fraction of the semiconductor liner film is smaller than the germanium fraction of the semiconductor filling film. Fig.16 of Yin teaches a semiconductor device that includes a first source/drain feature and a second source/drain feature over a substrate . Each source/drain feature includes a first epitaxial layer 238 , a second epitaxial layer 240 , and a third epitaxial layer 242 in one source/drain region 212 SD ; wherein w hen the first epitaxial layer 238 and the second epitaxial layer 240 are p-type (i.e., formed of silicon germanium), the germanium content and the p-type dopant concentration in the second epitaxial layer 240 is greater than those in the first epitaxial layer 238 (para.0032). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to inc orporate the difference in the concentration or fraction of germanium content in Lin’s semiconductor liner film and semiconductor filling film respectively , as taught by Yin, because the greater germanium content in the second epitaxial layer 240 allows the second epitaxial layer 240 to strain the channel layers 208 for improved hole mobility and the smaller germanium content in the first epitaxial layer 238 serves as a transitional layer between the germanium-free channel layers 208 and the second epitaxial layer 240 to reduce defects and contact resistance (Yin, [para.0032]) . Regarding claim 2 , Fig.24 of Lin further teaches the semiconductor device of claim 1, wherein the inner surface of the semiconductor liner film 98A (para.0054) includes a plurality of convex curved regions (see annotated Fig.24) and a plurality of concave curved regions (see annotated Fig.24). Regarding claim 3 , Fig.24 of Lin further teaches the semiconductor device of claim 1, wherein a first of the width extension regions (see annotated Fig.24) is between a lower sheet pattern 62 (para.0014) and an upper sheet pattern 66 (para.0014) in the second direction, and wherein a point on which first width extension region (see annotated Fig.24) has a maximum width in the first direction is located between the lower sheet pattern 62 and the upper sheet pattern 66. Regarding claim 4 , the combination of Lin and Yin further teaches the semiconductor device of claim 1, wherein the source/drain pattern 98 (para.0015) further includes a semiconductor insertion film 98B (para.0053) formed along the inner surface of the semiconductor liner film 98A (para.0054) , wherein the semiconductor insertion film 98B (para.0054) includes silicon germanium, and wherein a germanium fraction of the semiconductor insertion film 98B is between the germanium fraction of the semiconductor liner film 98A and the germanium fraction of the semiconductor filling film 98C (para.0055 , wherein germanium concentration of the seed layers 98 A is less than a germanium concentration of the liner layers 98 B and the main layers 98 C and in paragraph 0054 it is disclosed that the seed layers 98 A include materials from which the materials of the liner layers 98 B (e.g., boron-doped silicon germanium) have a low bottom-up growth rate). Regarding claim 5 , Lin further teaches the semiconductor device of claim 4, wherein the width of the semiconductor filling film 98C (para.0053) in the first direction increases as a distance increases in the second direction from the lower pattern 62 (para.0014). Regarding claim 6 , Lin further teaches the semiconductor device of claim 4, wherein the semiconductor insertion film 98B (para.0053) includes an outer surface that faces the inner surface of the semiconductor liner film 98A (para.0054), and an inner surface that faces the semiconductor filling film 98C (para.0053), and wherein the inner surface of the semiconductor insertion film 98B includes a plurality of convex curved regions (see annotated Fig.24) and a plurality of concave curved regions (see annotated Fig.24). Regarding claim 11 , Lin further teaches the semiconductor device of claim 1, wherein the outer surface of the semiconductor liner film 98A (para.0054) includes a plurality of convex curved regions (see annotated Fig.24) and a plurality of concave curved regions (see annotated Fig.24), wherein one of the concave curved regions is in contact with a corresponding one of the sheet patterns 66 (para.0014), and wherein one of the convex curved regions is in contact with one of the gate insulating films 122 (para.0015) of one of the gate electrodes 124 (para.0015). Regarding claim 13 , Lin further teaches the semiconductor device of claim 1, wherein the outer surface of the semiconductor liner film 98A (para.0054) includes a plurality of first concave curved regions (see annotated Fig.24) and a plurality of second concave curved regions (see annotated Fig.24), wherein one of the first concave curved regions is in contact with one of the sheet patterns 66 (para.0014), and wherein one of the second concave curved regions is in contact with one of the gate insulating films 122 (para.0015) of one of the gate electrodes 124 (para.0015). Regarding claim 19 , Fig.24 of Lin teaches a semiconductor device comprising: an active pattern which includes a lower pattern 62 (para.0014) that extends in a first direction, and a plurality of sheet patterns 66 (para.0014) spaced apart from the lower pattern 62 in a second direction perpendicular to the first direction; a plurality of gate structures 122/124 (para.0015) which are on the lower pattern 62 and spaced apart in the first direction, each gate structure 122/124 including a gate electrode 124 (para.0015) and a gate insulating film 122 (para.0015); and a source/drain pattern 98 (para.0015) which is between a pair of the gate structures 122/124 that are adjacent to each other in the first direction, wherein each gate structure 122/124 includes inner gate structure 122/124 between the lower pattern 62 and the sheet pattern 66 in the second direction, and between each pair of the sheet patterns 66 adjacent to each other in the second direction, each inner gate structure 122/124 including the gate electrode 124 and the gate insulating film 122, wherein the source/drain pattern 98 includes a semiconductor liner film 98A (para.0053), a semiconductor filling film 98C (para.0053) on the semiconductor liner film 98A, and a semiconductor insertion film 98B (para.0053) between the semiconductor liner film 98A and the semiconductor filling film 98C, wherein the semiconductor liner film 98A, the semiconductor insertion film 98B and the semiconductor filling film 98C include silicon-germanium, wherein a germanium fraction of the semiconductor insertion film 98B is less than a germanium fraction of the semiconductor filling film 98C (para.00 68 , wherein the main layers 98 C may have a greater germanium concentration and a greater boron concentration than the liner layers 98 B ), wherein the semiconductor liner film 98A includes an outer surface which is in contact with the sheet pattern 66 and the inner gate structure 122/124, and an inner surface which is in contact with the semiconductor insertion film 98B, and wherein the inner surface of the semiconductor liner film 98A includes a plurality of convex curved regions (see annotated Fig.24) and a plurality of concave curved regions (see annotated Fig.24). Lin does not teach wherein a germanium fraction of the semiconductor insertion film is greater than a germanium fraction of the semiconductor liner film . Fig.16 of Yin teaches a semiconductor device that includes a first source/drain feature and a second source/drain feature over a substrate . Each source/drain feature includes a first epitaxial layer 238 , a second epitaxial layer 240 , and a third epitaxial layer 242 in one source/drain region 212 SD ; wherein w hen the first epitaxial layer 238 and the second epitaxial layer 240 are p-type (i.e., formed of silicon germanium), the germanium content and the p-type dopant concentration in the second epitaxial layer 240 is greater than those in the first epitaxial layer 238 (para.0032). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to inc orporate the difference in the concentration or fraction of germanium content in Lin’s semiconductor liner film and semiconductor filling film respectively , as taught by Yin, because the greater germanium content in the second epitaxial layer 240 allows the second epitaxial layer 240 to strain the channel layers 208 for improv ed hole mobility and the smaller germanium content in the first epitaxial layer 238 serves as a transitional layer between the germanium-free channel layers 208 and the second epitaxial layer 240 to reduce defects and contact resistance (Yin, [para.0032]) . Regarding claim 21 , Lin further teaches the semiconductor device of claim 19, wherein the semiconductor insertion film 98B (para.0053) conforms to the inner surface of the semiconductor liner film 98A (para.0053). Claim s 7-9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. ( US20220367622A1 ) in view of Yin et al. ( US20220157969A1 ) and in further view of Lee et al. ( US11489063B2 ) . Regarding claim 7 , Fig.24 of Lin further teaches the semiconductor device of claim 1, wherein each of the semiconductor insertion films 98B (para.0054) is between the semiconductor liner film 98A (para.0054) and the semiconductor filling film 98C (para.0055, wherein each semiconductor insertion film 98B includes silicon germanium, and wherein a germanium fraction of each semiconductor insertion film 98B is greater than the germanium fraction of the semiconductor liner film 98A and smaller than the germanium fraction of the semiconductor filling film 98C (para.0055, wherein germanium concentration of the seed layers 98 A is less than a germanium concentration of the liner layers 98 B and the main layers 98 C and in paragraph 0054 it is disclosed that the seed layers 98 A include materials from which the materials of the liner layers 98 B (e.g., boron-doped silicon germanium) have a low bottom-up growth rate). Lin does not teach wherein the source/drain pattern further includes a plurality of semiconductor insertion films spaced apart from each other in the second direction, Fig.18 of Lee teaches a source/drain epitaxial feature formed in a source/ drain trench; wherein the source/drain epitaxial feature includes seed layers (semiconductor insertion films) 66 that are spaced apart from each other. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Lee’s seed layers that are spaced apart in the teachings of Lin in order to increase the available semiconductor surfaces in the S/D trench 60 for the epitaxial growth and enable the portions of the semiconductor layer 68a grown directly from different semiconductor surfaces merge better and provide a less wavy surface for the subsequent epitaxial growth of the semiconductor layer (Lee, col.10, lines 25-36). Regarding claim 8 , t he combination of Lin and Le further teaches the semiconductor device of claim 7, wherein the semiconductor filling film 68 (Lee, col.10, lines 1-2) is in contact with the semiconductor liner film 64 (col.9, line 38). Regarding claim 9 , t he combination of Lin and Le further teaches the semiconductor device of claim 7, wherein the inner surface of the semiconductor liner film 98A (para.0054) includes a plurality of convex curved regions (see annotated Fig.24) and a plurality of concave curved regions (see annotated Fig.24), and wherein at least part of one of the semiconductor insertion films 98B (para.0054) is in one of the concave curved regions. Regarding claim 20 , Lin does not teach wherein the semiconductor insertion film includes a plurality of sub-semiconductor insertion films spaced apart in the second direction. Fig.18 of Lee teaches a source/drain epitaxial feature formed in a source/ drain trench; wherein the source/drain epitaxial feature includes seed layers (semiconductor insertion films) 66 that are spaced apart from each other. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Lee’s seed layers that are spaced apart in the teachings of Lin in order to increase the available semiconductor surfaces in the S/D trench 60 for the epitaxial growth and enable the portions of the semiconductor layer 68a grown directly from different semiconductor surfaces merge better and provide a less wavy surface for the subsequent epitaxial growth of the semiconductor layer (Lee, col.10, lines 25-36). Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim s 14 and 17 are rejected under 35 U.S.C. 102 (a)(1)/(a)(2) as being FILLIN "Insert either—clearly anticipated—or—anticipated—with an explanation at the end of the paragraph." \d "[ 3 ]" anticipated by Lin et al. (US20220367622A1) . Regarding claim 1 4 , Fig.24 of Lin teaches a semiconductor device comprising: an active pattern which includes a lower pattern 62 (para.0014) that extends in a first direction, and a plurality of sheet patterns 66 (para.0014) spaced apart from the lower pattern 62 in a second direction that is perpendicular to the first direction; a plurality of gate structures 122/124 (para.0015) which are on the lower pattern 62 and spaced apart from each other in the first direction, each gate structure 122/124 including a gate electrode 124 (para.0015) and a gate insulating film 122 (para.0015); and a source/drain pattern 98 (para.0015) which is between a pair of the gate structures 122/124 that are adjacent to each other in the first direction, the source/drain pattern 98 including a semiconductor insertion film 98B (para.0053), and a semiconductor filling film 98C (para.0054) on the semiconductor insertion film 98B, wherein the semiconductor insertion film 98B and the semiconductor filling film 98C include silicon-germanium, wherein a germanium fraction of the semiconductor insertion film 98B is less than the germanium fraction of the semiconductor filling film 98C ( para.0068, wherein the main layers 98 C may have a greater germanium concentration and a greater boron concentration than the liner layers 98 B ), wherein the semiconductor insertion film 98B includes an inner surface that is in contact with the semiconductor filling film 98C, and an outer surface that faces the plurality of sheet patterns 66, wherein the outer surface of the semiconductor insertion film 98B includes a plurality of first convex curved regions (see annotated Fig.24) and a plurality of first concave curved regions (see annotated Fig.24) , and wherein the outer surface of the semiconductor insertion film 98B is not in contact with the plurality of sheet patterns 66. Regarding claim 17 , Lin further teaches the semiconductor device of claim 14, wherein the source/drain pattern 98 (para.0015) includes a semiconductor liner film 98A (para.0053) which surrounds the outer surface of the semiconductor insertion film 98B (para.0053) and is in contact with the semiconductor insertion film 98B, and wherein the semiconductor liner film 98A is in contact with the plurality of sheet patterns 66 (para.0014) and the lower pattern 62 (para.0014). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT VINCENT KIPKEMOI RONO whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-5977 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Mon-Fri, 8am-5pm . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Matthew Landau can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571)272-1731 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent- center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. FILLIN "Examiner Stamp" \* MERGEFORMAT VINCENT KIPKEMOI. RONO Examiner Art Unit 2891 /V.K.R./ Examiner, Art Unit 2891 /MATTHEW C LANDAU/ Supervisory Patent Examiner, Art Unit 2891