DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 4. Claim 4 recites the limitation "the fin the structure" in the last line of the claim language. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of examination and compact prosecution, examiner shall interpret “the fin the structure” to be “the fin structure”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 5, 10-14, 16, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lamorey et al (U.S. 2015/0243609), and Hool (U.S. 7,115,988).
Regarding claim 1. Lamorey et al discloses a packaged electronic device structure (FIG. 1-3, item 10), comprising:
a substrate (FIG. 2, item 20);
an electronic device (FIG. 2, item 12) coupled (FIG. 2, item 21) to the substrate (FIG. 2, item 20) and comprising side edges (FIG. 2, item 12 edges);
a first conductive structure (FIG. 2-3, item 54) coupled to at least a first portion of the substrate (FIG. 2, item 20);
the first conductive structure (FIG. 2-3, item 54) comprising a top portion (FIG. 2-3, item 53) and a side portion (FIG. 2-3, item 55) extending outward ([0022]) from the top portion (FIG. 2-3, item 54), wherein the top portion (FIG. 2-3, item 53) and the side portion (FIG. 2-3, item 55) comprise a continuous structure (FIG. 2-3, item 54; [0022]), and wherein the side portion (FIG. 2-3, item 53) is laterally separated (FIG. 2, item 31) from the side edges ([0022]) of the electronic device (FIG. 2, item 12) and laterally surrounds ([0022]) the electronic device (FIG. 2, item 12) without breaks (FIG. 2-3, item 53-55; [0022]), and wherein the top portion (FIG. 2-3, item 55) and the side portion (FIG. 2-3, item 53) form a first capacitive plate ([Abstract]), and wherein the top portion (FIG. 2-3, item 55) overlies the electronic device (FIG. 2-3, item 12)
a dielectric structure (FIG. 2-3, item 82) on the top and the side portions (FIG. 2-3, item 53) of the first conductive structure wherein the dielectric structure forms a capacitor dielectric; and
a second conductive structure (FIG. 2-3, item 64) the dielectric structure (FIG. 2-3, item 82) and coupled (FIG. 2, item 38a) to a second portion of the substrate (FIG. 2, item 20),
wherein: the second conductive structure (FIG. 2-3, item 64) overlies the top portion and the side portion (FIG. 2-3, item 55) of the first conductive structure (FIG. 2-3, item 64) and forms a second capacitive plate ([0028]), and wherein
the first capacitive plate (FIG. 2-3, item 54), the capacitor dielectric (FIG. 2-3, item 82), and the second capacitive plate (FIG. 2-3, item 53-55) form a capacitor structure ([0028]-[0029]) and one or more of an enclosure structure (FIG. 2-3, item 53-55; [0022]) or a stiffener structure (FIG. 2-3, item 53-55; [0022]).
Lamorey fails to explicitly disclose a dielectric structure on the top portions of the first conductive structure
wherein: the second conductive structure overlies the top portion of the first conductive structure
However, Hool teaches a dielectric structure (FIG. 3A/3B, bottom item 342 of 330) on the top portions of the first conductive structure (FIG. 3A/3B, bottom item 340 of 330) wherein: the second conductive structure (FIG. 3A/3B, top item 340 of 330) overlies the top portion (Col 9, lines 17-18, i.e. Bypass capacitor 330 is typically constructed with plates 340 separated by a dielectric material 342) of the first conductive structure (FIG. 3A/3B, bottom item 340 of 330)
Since Lamorey et al and Hool teach Capacitor structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the packaged electronic device structure as disclosed to modify Lamorey et al with the teachings of a dielectric structure on the top portions of the first conductive structure wherein: the second conductive structure overlies the top portion of the first conductive structure as disclosed by Hool. The use of Bypass capacitor is typically constructed with plates separated by a dielectric material in Hool provides for substantially instant power and/or to control simultaneous switching noise (Hool, [Abstract]).
Regarding claim 2. Lamorey et al and Hool discloses all the limitations of the packaged electronic device structure of claim 1 above.
Lamorey et al further discloses wherein:
the top portion (FIG. 2-3, item 53) is coupled (FIG. 2-3, item 56) to the electronic device (FIG. 2-3, item 12) with an attachment material (FIG. 2-3, item 56); and the the top portion (FIG. 2-3, item 53) and the side portion (FIG. 2-3, item 55) comprise a first lid structure (FIG. 2-3, item 54) that encloses the electronic device (FIG. 2-3, item 12).
Regarding claim 3. Lamorey et al and Hool discloses all the limitations of the packaged electronic device structure of claim 2 above.
Lamorey et al further discloses wherein: the second conductive structure (FIG. 2-3, item 64) comprises a second lid structure (FIG. 2-3, item 64).
Regarding claim 5. Lamorey et al and Hool discloses all the limitations of the packaged electronic device structure of claim 1,
Lamorey et al further disclose wherein: the dielectric structure (FIG. 2-3, item 82) comprises a 3D printed dielectric structure.
The limitation “comprises a 3D printed dielectric structure” is a product-by-process limitation in a device claim.
As long as the limitation of “the dielectric structure” is met, then the claim limitation is met.
"Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). See MPEP 2173.05(p) Section I
Regarding claim 10. Lamorey et al and Hool discloses all the limitations of the packaged electronic device structure of claim 1,
Lamorey et al further disclose wherein: the first conductive structure (FIG. 2-3, item 64) comprises a 3D printed single-piece lid structure.
The limitation “comprises a 3D printed single-piece lid structure” is a product-by-process limitation in a device claim.
As long as the limitation of “the first conductive structure” is met, then the claim limitation is met.
"Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). See MPEP 2173.05(p) Section I
Regarding claim 11. Lamorey et al discloses a packaged electronic device (FIG. 2-3, item 10), comprising:
a substrate (FIG. 2-3, item 20);
an electronic device (FIG. 2-3, item 12) attached to the substrate (FIG. 2-3, item 20), the electronic device (FIG. 2-3, item 12) comprising side edges (FIG. 2-3, item 12 edges);
a single-piece lid structure (FIG. 2-3, item 54) coupled to the substrate (FIG. 2-3, item 20) and coupled to the electronic device (FIG. 2-3, item 12) with an attachment material (FIG. 2-3, item 56), the single-piece lid structure (FIG. 2-3, item 54) comprising a conductive structure (FIG. 2-3, item 54) having a top portion (FIG. 2-3, item 53) and a side portion (FIG. 2-3, item 55) that extends from the top portion (FIG. 2-3, item 53), wherein:
the single-piece lid structure (FIG. 2-3, item 54) forms an enclosure structure (FIG. 2-3, item 54) that vertically ([0022]) and horizontally ([0022]) encloses the electronic device (FIG. 2-3, item 12); and
a dielectric structure (FIG. 2-3, item 52) on the side portion (FIG. 2-3, item 55) of the single piece lid structure (FIG. 2-3, item 54) over the single-piece lid structure (FIG. 2-3, item 54); and
a conductive structure (FIG. 2-3, item 64) over the dielectric structure (FIG. 2-3, item 82) and attached (FIG. 2-3, item 66) to the substrate (FIG. 2-3, item 20), wherein:
the conductive structure (FIG. 2-3, item 64) overlaps the side portion (FIG. 2-3, item 55) of the single-piece lid structure (FIG. 2-3, item 54); the top portion and side portion (FIG. 2-3, item 55) of the single-piece lid structure (FIG. 2-3, item 54) form a first capacitive plate ([0028]);
the dielectric structure (FIG. 2-3, item 82) forms a capacitor dielectric ([0028]);
the conductive structure (FIG. 2-3, item 64) forms a second capacitive plate([0028]); and
the first capacitive plate (FIG. 2-3, item 55), the capacitor dielectric (FIG. 2-3, item 82), and the second capacitive plate (FIG. 2-3, item 64) form a capacitor structure (FIG. 2, item 70; [0028]) for the packaged electronic device (FIG. 1-3, item 10).
Lamorey fails to explicitly disclose a dielectric structure on the top portion of the single-piece lid structure
wherein: the second conductive structure overlaps the top portion of the single-piece lid structure.
However, Hool teaches a dielectric structure (FIG. 3A/3B, bottom item 342 of 330) on the top portions (FIG. 3A/3B, bottom item 340 of 330) of the single-piece lid structure (FIG. 3A/3B, bottom item 340 of 330) wherein: the second conductive structure (FIG. 3A/3B, top item 340 of 330) overlies the top portion (Col 9, lines 17-18, i.e. Bypass capacitor 330 is typically constructed with plates 340 separated by a dielectric material 342) of the single-piece lid structure (FIG. 3A/3B, bottom item 340 of 330)
Since Lamorey et al and Hool teach Capacitor structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the packaged electronic device structure as disclosed to modify Lamorey et al with the teachings of a dielectric structure on the top portion of the single-piece lid structure wherein: the second conductive structure overlaps the top portion of the single-piece lid structure as disclosed by Hool. The use of Bypass capacitor is typically constructed with plates separated by a dielectric material in Hool provides for substantially instant power and/or to control simultaneous switching noise (Hool, [Abstract]).
Regarding claim 12. Lamorey et al and Hool discloses all the limitations of the packaged electronic device structure of claim 11 above.
Lamorey et al further discloses wherein:
the substrate (FIG. 2, item 20) comprises an insulating structure ([0014], i.e. 20 may also comprise an interconnect structure fabricated with middle-end-of-line and back-end-of-line processes.. , 20 to define continuous conductive paths. The conductive features 17 may comprise through silicon vias (TSVs). The TSVs comprising the conductive features 17 may be fabricated by deep reactive ion etching or laser drilling a deep via into the substrate, electrically insulating the deep via) comprising a top surface (FIG. 2, item 20b) and a bottom surface (FIG. 2, item 20a), and an electrically conductive pattern (FIG. 2, item 21) adjacent to the top surface (FIG. 2, item 20b);
the electronic device ([0012]-[0018]) is attached to the electrically conductive pattern (FIG. 2, item 21) at the top surface (FIG. 2, item 20b)
the side portion (FIG. 2-3, item 55) comprises a continuous portion (FIG. 2-3, item 55) that laterally surrounds ([0022]) the side edges of the electronic device (FIG. 2-3, item 12) without a break ([0022]) .
Regarding claim 13. Lamorey et al and Hool discloses all the limitations of the packaged electronic device structure of claim 11 above.
Lamorey et al further discloses wherein: the single-piece lid structure (FIG. 1-3, item 54) comprises ([0023]) one or more fin structures (FIG. 1, item 62) extending outward ([0023]) from the top portion (FIG. 1-3, item 53) in a direction perpendicular from, overlying, and above a top side ([0022]) of the electronic device (FIG. 1-3, item 12).
Regarding claim 14. Lamorey et al and Hool discloses all the limitations of the packaged electronic device structure of claim 11 above.
Lamorey et al further disclose wherein: the conductive structure (FIG. 2-3, item 64) comprises a 3D printed structure.
The limitation “a 3D printed structure” is a product-by-process limitation in a device claim.
As long as the limitation of “the conductive structure” is met, then the claim limitation is met.
"Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). See MPEP 2173.05(p) Section I
Regarding claim 16. Lamorey et al discloses a packaged electronic device (FIG. 1-3, item 10), comprising:
a substrate (FIG. 2-3, item 20);
an electronic device (FIG. 2-3, item 12) coupled to the substrate (FIG. 2-3, item 20), wherein the electronic device comprises (FIG. 2-3, item 12): a top side (FIG. 2-3, item 12 top side); and side edges(FIG. 2-3, item 12 side edges);
a first conductive structure (FIG. 2-3, item 54) coupled to the substrate (FIG. 2-3, item 20) and comprising ([0022]) a top portion (FIG. 2-3, item 53) that overlaps the top side ([0022]) of the electronic device (FIG. 2-3, item 12) and a side portion (FIG. 2-3, item 55) extending from the top portion (FIG. 2-3, item 53), the side portion laterally surrounding the side edges of the electronic device (FIG. 2-3, item 12) without a break ([0022]);
a dielectric structure (FIG. 2-3, item 82) on the top and the side portion (FIG. 2-3, item 55) of the first conductive structure (FIG. 2-3, item 54); and
a second conductive structure (FIG. 2-3, item 64) on the dielectric structure (FIG. 2-3, item 82) and overlapping the top portion and side portion (FIG. 2-3, item 55) of the first conductive structure (FIG. 2-3, item 54);
wherein:
the top portion (FIG. 2-3, item 53) and the side portion (FIG. 2-3, item 12) of the first conductive structure (FIG. 2-3, item 55) provides a first capacitive plate ([0028]);
the top portion (FIG. 2-3, item 53) overlaps the top side ([0022]) of the electronic device (FIG. 2-3, item 12);
the dielectric structure (FIG. 2-3, item 82) provides a capacitor dielectric ([0028]);
the second conductive structure (FIG. 2-3, item 64) provides a second capacitive plate ([0028]); and
the first capacitive plate (FIG. 2-3, item 55), the capacitor dielectric (FIG. 2-3, item 82), and the second capacitive plate (FIG. 2-3, item 64) form a capacitor structure (FIG. 2-3, item 70; [0028]) for the packaged electronic device (FIG. 1-3, item 10).
Regarding claim 18. Lamorey et al and Hool discloses all the limitations of the packaged electronic device structure of claim 16 above.
Lamorey et al further discloses wherein: the first conductive structure (FIG. 2-3, item 53-55) comprises a single-piece lid structure (FIG. 2-3, item 54) couple (FIG. 2-3, item 55) to the substrate (FIG. 2-3, item 20) and coupled to the electronic device (FIG. 2-3, item 12) with an attachment material (FIG. 2-3, item 56), the single-piece lid structure (FIG. 2-3, item 55) comprising a top portion (FIG. 2-3, item 53) and a side portion (FIG. 2-3, item 55) that extends from the top portion (FIG. 2-3, item 53), wherein the single-piece lid structure (FIG. 2-3, item 54) forms an enclosure structure (FIG. 2-3, item 54) that vertically (FIG. 2-3, item 55) and horizontally (FIG. 2-3, item 53) encloses the electronic device (FIG. 2-3, item 21).
Regarding claim 19. Lamorey et al and Hool discloses all the limitations of the packaged electronic device structure of claim 16 above.
Lamorey et al further discloses wherein: the first conductive structure (FIG. 2-3, item 53-55) comprises a first portion (FIG. 2-3, item 55) coupled to the substrate (FIG. 2-3, item 20) and a second portion (FIG. 2-3, item 53) coupled to the first portion (FIG. 2-3, item 55);
and the second portion (FIG. 2-3, item 53) is coupled to the top side of the electronic device (FIG. 2-3, item 12) with an attachment material (FIG. 2-3, item 56).
Regarding claim 20. Lamorey et al and Hool discloses all the limitations of the packaged electronic device structure of claim 16 above.
Lamorey et al further discloses wherein: the packaged electronic device (FIG. 2-4, item 12) is devoid of encapsulant material (FIG. 4, item 31) between the first conductive structure (FIG. 4, item 55) and the side edges (FIG. 4, item 12 side edges) of the electronic device (FIG. 4, item 12).
Claim 4 are rejected under 35 U.S.C. 103 as being unpatentable over Lamorey et al (U.S. 2015/0243609), and Hool (U.S. 7,115,988) as applied to claim 1 above, and further in view of Brench (U.S. 6,011,299).
Regarding claim 4. Lamorey et al and Hool discloses all the limitations of the packaged electronic device structure of claim 2 above.
Lamorey et al further discloses wherein: the top portion (FIG. 2-3, item 53) comprises ([0022]-[0023]) a fin structure (FIG. 1-3, item 62), and
Lamorey et al and Hool fails to explicitly disclose the dielectric structure is on the fin structure and conforms to a shape of the fin the structure.
However, Brench teaches the dielectric structure is on the fin structure and conforms to a shape of the fin the structure.
Since Lamorey et al, Hool, and Brench teach fin structure, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the packaged electronic device as disclosed to modify Lamorey et al and Hool with the teachings of comprises the dielectric structure (FIG. 2, item 56) is on the fin structure (FIG. 2, item 28a-28i) and conforms ([Col 4, lines 13-48]) to a shape of the fin the structure (FIG. 2, item 28a-28i) as disclosed by Brench. The use of fin structure in Brench provides for suppresses unwanted radio frequency radiation emitted by the heatsinks of integrated circuits (Brench, [Col 4, lines 49-51]).
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lamorey et al (U.S. 2015/0243609), and Hool (U.S. 7,115,988) as applied to claims 1 and 11 above, and further in view of Gustafson (U.S. 2017/0018365).
Regarding claims 6 and 15. Lamorey et al and Hool discloses all the limitations of the packaged electronic device of claim 1 and 11 above.
Lamorey et al further discloses wherein the dielectric structure (FIG. 2-3, item 82) has a thickness ([0029], i.e. 82 has a width, G)
Lamorey et al fails to explicitly disclose has a thickness in a range from about 2 microns through about 5 microns.
However, Gustafson teaches the dielectric structure has a thickness in a range from about 2 microns through about 5 microns ([0010], i.e. a dielectric layer, such as below the standard 500 microns, e.g., 1 to 499 microns).
Since Lamorey et al, Hool, and Gustafson teach capacitors, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the packaged electronic device as disclosed to modify Lamorey et al and Hool with the teachings of the dielectric structure has a thickness in a range from about 2 microns through about 5 microns as disclosed by Gustafson. The use of a dielectric layer, such as below the standard 500 microns, e.g., 1 to 499 microns in Gustafson provides for a reduction in distance equates to increased area for the conductive layer, and thus increased capacitance and operating voltage for the capacitor (Gustafson, [0010]).
Response to Arguments
Applicant's arguments filed October 14, 2025 have been fully considered but they are not persuasive.
On page 10-12 of applicant’s remarks, applicant appears to argue for claims 1, 11, and 16 that Lamorey et al fails to teach a top side of the second conductive structure overlies a top portion of the first conductive structure.
Examiner respectfully points out that Hool teaches a top side of the second conductive structure overlies a top portion of the first conductive structure.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
On page 10-11 of applicant’s remarks, applicant appears to argue the claims 2-4 are allowable for the same analogous reasons as claim 1 above.
Examiner respectfully points out that claims 2-4 are rejected for the same analogous reasons as claim 1 above.
On page 12 of applicant’s remarks, applicant appears to argue that claim 12 as allowable for the same analogous reasons as claim 11 above.
Examiner respectfully points out that claim 12 are rejected for the same analogous reasons as claim 11 above
On page 12 of applicant’s remarks, applicant appears to argue that claim 12 as allowable for the same analogous reasons as claim 11 above.
Examiner respectfully points out that claim 12 are rejected for the same analogous reasons as claim 11 above
Applicant further argues that Lamorey die 20 is not the substrate comprises an insulating structure comprising a top surface and a bottom surface, and an electrically conductive pattern adjacent to the top surface.
Examiner respectfully disagrees with applicant’s assessment.
Examiner respectfully points out Lamorey discloses the substrate (FIG. 2, item 20) comprises an insulating structure ([0014], i.e. 20 may also comprise an interconnect structure fabricated with middle-end-of-line and back-end-of-line processes.. , 20 to define continuous conductive paths. The conductive features 17 may comprise through silicon vias (TSVs). The TSVs comprising the conductive features 17 may be fabricated by deep reactive ion etching or laser drilling a deep via into the substrate, electrically insulating the deep via) comprising a top surface (FIG. 2, item 20b) and a bottom surface (FIG. 2, item 20a), and an electrically conductive pattern (FIG. 2, item 21) adjacent to the top surface (FIG. 2, item 20b).
On page 13 of applicant’s remarks, applicant appears to argue that claim 18, 19, and 20 as allowable for the same analogous reasons as claim 16 above.
Examiner respectfully points out that claims 18, 19, and 20 are rejected for the same analogous reasons as claim 16 above
On page 14 of applicant’s remarks, applicant appears to argue that claim 5, and 10 as allowable because the prior art does not teach 3D printing method.
Examiner respectfully points, that the invention is directed to the device not the method.
The limitation “3D printing” is a product-by-process limitation in a device claim.
As long as the limitation of “the device structure” is met, then the claim limitation is met.
"Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). See MPEP 2173.05(p) Section I.
On page 16 of applicant’s remarks, applicant appears to argue that claim 6, 13, 14, and 15 as allowable for the same analogous reasons as claims 1 and 11 above.
Examiner respectfully points out that claims 6, 13, 14, and 15 are rejected for the same analogous reasons as claims 1 and 11 above
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/S.E.B./ Examiner, Art Unit 2815