DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This OA is in response to the amendment filled on 6/15/2026 that has been entered, wherein claims 1-20 are pending and claims 11-17 are withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 and 18-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation " the plurality of conductive interconnects " in line 15. There is insufficient antecedent basis for this limitation in the claim. Are “the plurality of conductive interconnects” the same different than “the plurality of conductive interconnects elements” of line 3? For the purpose of examination “the plurality of conductive interconnects” will be interpreted as “the plurality of conductive interconnects elements”.
Claims 2-10 depend on claim 1 and inherit it’s deficiencies.
Claim 18 recites the limitation " the plurality of conductive interconnects " in line 17. There is insufficient antecedent basis for this limitation in the claim. Are “the plurality of conductive interconnects” the same different than “the plurality of conductive interconnects elements” of line 3? For the purpose of examination “the plurality of conductive interconnects” will be interpreted as “the plurality of conductive interconnects elements”.
Claims 19-20 depend on claim 18 and inherit it’s deficiencies.
Regarding claim 20, a broad range or limitation together with a narrow range or limitation that falls within the broad range or limitation (in the same claim) may be considered indefinite if the resulting claim does not clearly set forth the metes and bounds of the patent protection desired. See MPEP § 2173.05(c). In the present instance, claim20 recites the broad recitation “each thermoset region is at least 30 microns in lateral extent”, and the claim also recites “each thermoset region is … at least 50 microns in lateral extent” and “each thermoset region is … at least 100 microns in lateral extent” which is are narrower statement of the range/limitation. The claim is considered indefinite because there is a question or doubt as to whether the feature introduced by such narrower language is (a) merely exemplary of the remainder of the claim, and therefore not required, or (b) a required feature of the claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-10 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2022/0302087 A1) herein Choi ‘087 in view of Chen et al. (US 11,069,661 B1) of record.
Regarding claim 1, Choi ‘087 teaches a semiconductor device assembly(Fig. 1), comprising:
a die stack(100, 200, 300, 400, ¶0016) comprising at least first and second dies(100, 200, ¶0016), the first die(100, ¶0016) having an upper surface on which are disposed a plurality of conductive interconnect elements(UDP1a, UDP1b, USP1, ¶0021) extending to corresponding electrical connectors(LDP3a, LDP3b, LSP3, ¶0059) on a lower surface of the second die(200, ¶0016);
a plurality of laterally-spaced thermoset regions(region of 520 within 200b, Fig. 2, ¶0036, ¶0039) between the first and second dies(100, 200, ¶0016), each thermoset region(region of 520 within 200b, Fig. 2, ¶0036, ¶0039) comprising a layer of thermoset material(¶0036) extending from the lower surface of the second die(200, ¶0016) to the upper surface of the first die(100, ¶0016), wherein each of the plurality of laterally-spaced thermoset regions(region of 520 within 200b, Fig. 2, ¶0036, ¶0039) extends to fill an area between a plurality of adjacent interconnect elements(UDP1a, UDP1b, USP1, ¶0021) of the first die(100, ¶0016); and
an underfill material(region of 520 within 200a, Fig. 2, ¶0036, ¶0039) filling remaining open areas between the plurality of interconnect elements(UDP1a, UDP1b, USP1, ¶0021) of the first die(100, ¶0016), wherein the layer of thermoset material(¶0036) of each laterally-spaced thermoset region(region of 520 within 200b, Fig. 2, ¶0036, ¶0039) directly contacts a dummy subset(UDP1b, ¶0021) of the plurality of conductive interconnect elements(UDP1a, UDP1b, USP1, ¶0021) that are configured to not carry any electrical signal(¶0037), and is spaced apart by the underfill material(region of 520 within 200a, Fig. 2, ¶0036, ¶0039) from every live one of the plurality of conductive interconnects elements(UDP1a, UDP1b, USP1, ¶0021) that is configured to carry an electrical signal(¶0037).
Choi ‘087 is not relied on to teach plurality of laterally-spaced discrete thermoset regions(region of 520 within 200b, Fig. 2, ¶0036, ¶0039).
Chen teaches a semiconductor device assembly(Fig. 1) comprising plurality of laterally-spaced discrete thermoset regions(15, col. 4, lines 19-26). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Choi ‘087, to include a plurality of laterally-spaced discrete thermoset regions, as taught by Chen, so that the thermoset regions and underfill material can be arranged to create strains in different directions in order to adjust the distribution of stress of semiconductor device assembly, so as to attain an optimal control in the degree of warpage of semiconductor device assembly(col. 3, lines 18-26).
Regarding claim 2, Choi ‘087 teaches the semiconductor device assembly of claim 1, wherein the plurality of thermoset regions(region of 520 within 200b, Fig. 2, ¶0036, ¶0039) includes two thermoset regions(region of 520 within 200b, Fig. 2, ¶0036, ¶0039) located proximate opposite edges of the first die(100, ¶0016).
Regarding claim 3, Choi ‘087 teaches the semiconductor device assembly of claim 1, wherein the plurality of thermoset regions(region of 520 within 200b, Fig. 2, ¶0036, ¶0039) includes four thermoset regions(region of 520 within 200b, Fig. 2, ¶0036, ¶0039) located proximate four corresponding corners of the first die(100, ¶0016).
Regarding claim 4, Choi ‘087 teaches the semiconductor device assembly of claim 1, wherein the area between a plurality of adjacent interconnect elements(UDP1a, UDP1b, USP1, ¶0021) of the first die(100, ¶0016) is bounded by four interconnect elements(UDP1b, ¶0021) arranged in a two-by-two square(Fig. 2).
Regarding claim 5, Choi ‘087 teaches the semiconductor device assembly of claim 1, wherein the thermoset material(¶0036) comprises one of a non-conductive adhesive material(¶0036), a non-conductive film (NCF) (¶0036), a thermosetting polymer(¶0036), a thermosetting epoxy(¶0036), or a thin film.
Regarding claim 6, Choi ‘087 teaches the semiconductor device assembly of claim 5, but is not relied on to teach the underfill material(region of 520 within 200a, Fig. 2, ¶0036, ¶0039) is compatible with the thermoset material(¶0036).
Chen teaches a semiconductor device assembly(Fig. 1) wherein the underfill
material(14, col. 5, lines 54-56) is compatible with the thermoset material(15, col. 6
lines 10-16). It would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention to modify the device of Choi ‘087, so that an underfill material is compatible with the thermoset material, as taught by Chen, so that the thermoset regions and underfill material can be arranged to create strains in
different directions in order to adjust the distribution of stress of semiconductor device
assembly, so as to attain an optimal control in the degree of warpage of semiconductor
device assembly(col. 3, lines 18-26).
Regarding claim 10, Choi ‘087 teaches the semiconductor device assembly of claim 1, wherein the electrical connectors(LDP3a, LDP3b, LSP3, ¶0059) are interconnected by solder(DB1a, DB1b, SB1, ¶0038) to the plurality of conductive interconnect elements(UDP1a, UDP1b, USP1, ¶0021) on the upper surface of the first die(100, ¶0016).
Regarding claim 18, Choi ‘087 teaches a semiconductor device assembly(Fig. 1), comprising:
a die stack(100, 200, 300, 400, ¶0016) comprising N dies(100, 200, 300, 400, ¶0016) and an uppermost die(400, ¶0016), wherein N is an integer greater than or equal to three, each of the N dies including a plurality of conductive interconnect elements(UDP1a, UDP1b, USP1, ¶0021) on upper surfaces, wherein a portion of the interconnect elements(UDP1a, UDP1b, USP1, ¶0021) are connected to through-silicon vias (TSVs)(130, 230, 330,¶0025, ¶0033, ¶0061) that extend between the upper surfaces and lower surfaces of associated ones of the N dies(100, 200, 300, 400, ¶0016);
a plurality of laterally-spaced thermoset regions(region of 520 within 200b, Fig. 2, ¶0036, ¶0039) between the first and second dies(100, 200, ¶0016), each thermoset region(region of 520 within 200b, Fig. 2, ¶0036, ¶0039) comprising a layer of thermoset material(¶0036) extending from the lower surface of the second die(200, ¶0016) to the upper surface of the first die(100, ¶0016), wherein each of the plurality of laterally-spaced thermoset regions(region of 520 within 200b, Fig. 2, ¶0036, ¶0039) extends to fill an area between a plurality of adjacent interconnect elements(UDP1a, UDP1b, USP1, ¶0021) of the first die(100, ¶0016); and
an underfill material(region of 520 within 200a, Fig. 2, ¶0036, ¶0039) filling remaining open areas between the interconnect elements(UDP1a, UDP1b, USP1, ¶0021) of the N-1 dies,
wherein the layer of thermoset material(¶0036) of each laterally-spaced thermoset region(region of 520 within 200b, Fig. 2, ¶0036, ¶0039) directly contacts a dummy subset(UDP1b, ¶0021) of the plurality of conductive interconnect elements(UDP1a, UDP1b, USP1, ¶0021) that are configured to not carry any electrical signal(¶0037), and is spaced apart by the underfill material(region of 520 within 200a, Fig. 2, ¶0036, ¶0039) from every live one of the plurality of conductive interconnects(UDP1a, UDP1b, USP1, ¶0021) that is configured to carry an electrical signal(¶0037.
Choi ‘087 is not relied on to teach plurality of laterally-spaced discrete thermoset regions(region of 520 within 200b, Fig. 2, ¶0036, ¶0039).
Chen teaches a semiconductor device assembly(Fig. 1) comprising plurality of laterally-spaced discrete thermoset regions(15, col. 4, lines 19-26). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Choi ‘087, to include a plurality of laterally-spaced discrete thermoset regions, as taught by Chen, so that the thermoset regions and underfill material can be arranged to create strains in different directions in order to adjust the distribution of stress of semiconductor device assembly, so as to attain an optimal control in the degree of warpage of semiconductor device assembly(col. 3, lines 18-26).
Regarding claim 19, Choi ‘087 teaches the semiconductor device assembly of claim 18, wherein the thermoset material(¶0036) comprises one of a non-conductive adhesive material(¶0036), a non-conductive film (NCF) (¶0036), a thermosetting polymer(¶0036), a thermosetting epoxy(¶0036), or a thin film.
Claims 1-10 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2022/0302087 A1) herein Choi ‘087 and of Chen et al. (US 11,069,661 B1) of record as applied to claims 1 and 20, further in view of Yim et al. (US 8451620 B2) of record.
Regarding claim 7, Choi ‘087, in view of Chen, teaches the semiconductor device assembly of claim 1, but do not explicitly state each of the thermoset regions(region of 520 within 200b, Fig. 2, ¶0036, ¶0039) are at least 30 microns in lateral extent.
Yim teaches a semiconductor device assembly(Fig. 1) wherein the area of the
thermoset regions(104, col. 3, lines 4-23) are optimized to correspond to positions that
exhibit solder joint failure(104, col. 3, lines 4-23). Accordingly, it would have been
obvious to one of ordinary skill in the art before the effective filing date of the claimed
invention to make each of the thermoset regions are at least 30 microns in lateral
extent, since it has been held that when the prior art discloses the general conditions
of the claimed invention, discovering the optimum or workable ranges involves only
ordinary skill in the art. See MPEP 2144.05.
Regarding claim 8, Choi ‘087, in view of Chen, teaches the semiconductor device assembly of claim 1, but do not explicitly state each of the thermoset regions(region of 520 within 200b, Fig. 2, ¶0036, ¶0039) are at least 100 microns in lateral extent.
Yim teaches a semiconductor device assembly(Fig. 1) wherein the area of the
thermoset regions(104, col. 3, lines 4-23) are optimized to correspond to positions that
exhibit solder joint failure(104, col. 3, lines 4-23). Accordingly, it would have been
obvious to one of ordinary skill in the art before the effective filing date of the claimed
invention to make each of the thermoset regions are at least 100 microns in lateral
extent, since it has been held that when the prior art discloses the general conditions
of the claimed invention, discovering the optimum or workable ranges involves only
ordinary skill in the art. See MPEP 2144.05.
Regarding claim 9, Choi ‘087, in view of Chen, teaches the semiconductor device assembly of claim 1, but are not relied on to teach the plurality of thermoset regions(region of 520 within 200b, Fig. 2, ¶0036, ¶0039) includes a thermoset region located in a central region of the upper surface of the first die(100, ¶0016).
Yim teaches the semiconductor device assembly(Fig. 1), wherein
the plurality of thermoset regions(104, col. 3, lines 4-23) includes a thermoset region
located in a central region(not illustrated, underfill in center of package, col. 3, lines 4-
23) of the upper surface of the first die(108, col. 2, lines 57-64). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Choi ‘087, so that the plurality of thermoset region includes a thermoset region located in a central region of the upper surface of the first die, as taught by Yim, in order to reduce underfill material consumption relative to other methods, while still providing solder joint reliability(col. 2, lines 39-56).
Regarding claim 20, Choi ‘087, in view of Chen, teaches the semiconductor device assembly of claim 18, but do not explicitly state each thermoset region(region of 520 within 200b, Fig. 2, ¶0036, ¶0039) is at least 30 microns in lateral extent.
Yim teaches a semiconductor device assembly(Fig. 1) wherein the area of the
thermoset regions(104, col. 3, lines 4-23) are optimized to correspond to positions that
exhibit solder joint failure(104, col. 3, lines 4-23). Accordingly, it would have been
obvious to one of ordinary skill in the art before the effective filing date of the claimed
invention to make each of the thermoset regions are at least 30 microns in lateral
extent, since it has been held that when the prior art discloses the general conditions
of the claimed invention, discovering the optimum or workable ranges involves only
ordinary skill in the art. See MPEP 2144.05.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA DYKES whose telephone number is (571)270-3161. The examiner can normally be reached M-F 9:30 am-5 pm.
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/LAURA M DYKES/Examiner, Art Unit 2892
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