DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This OA is in response to the amendment filled on 11/25/2025 that has been entered, wherein claims 1-20 are pending and claims 11-17 are withdrawn.
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-10 and 18-20 in the reply filed on 11/25/2025 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 and 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation " the two thermoset regions " in line 9. There is insufficient antecedent basis for this limitation in the claim. Are the two thermoset regions part of the plurality of thermoset regions of line 6 or different thermoset regions? For the purpose of examination “the two thermoset regions” will be interpreted as “the plurality of thermoset regions”.
Claims 2-10 depend on claim 1 and inherit it’s deficiencies.
Claim 18 recites the limitation "the two thermoset regions " in line 10. There is insufficient antecedent basis for this limitation in the claim. Are the two thermoset regions part of the plurality of thermoset regions of line 7 or different thermoset regions? For the purpose of examination “the two thermoset regions” will be interpreted as “the plurality of thermoset regions”.
Claims 19-20 depend on claim 18 and inherit it’s deficiencies.
Regarding claim 20, a broad range or limitation together with a narrow range or limitation that falls within the broad range or limitation (in the same claim) may be considered indefinite if the resulting claim does not clearly set forth the metes and bounds of the patent protection desired. See MPEP § 2173.05(c). In the present instance, claim20 recites the broad recitation “each thermoset region is at least 30 microns in lateral extent”, and the claim also recites “each thermoset region is … at least 50 microns in lateral extent” and “each thermoset region is … at least 100 microns in lateral extent” which is are narrower statement of the range/limitation. The claim is considered indefinite because there is a question or doubt as to whether the feature introduced by such narrower language is (a) merely exemplary of the remainder of the claim, and therefore not required, or (b) a required feature of the claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yim et al. (US 8451620 B2) in view of Chen et al. (US 11,069,661 B1).
Regarding claim 1, Yim teaches a semiconductor device assembly(Fig. 1), comprising:
a die stack(100) comprising at least first and second dies(102, 108, col. 2, lines 57-64), the first die(108, col. 2, lines 57-64) having an upper surface on which are disposed a plurality of conductive interconnect elements(112, col. 2, line 65- col. 3, line 3) extending to corresponding electrical connectors(112, col. 2, line 65- col. 3, line 3) on a lower surface of the second die(102, col. 2, lines 57-64);
a plurality of laterally-spaced discrete thermoset regions(104, col. 3, lines 4-23) between the first and second dies(102, 108, col. 2, lines 57-64), each thermoset region(104, col. 3, lines 4-23) comprising a layer of thermoset material(epoxy, silicone, col. 3, lines34-30) extending from the lower surface of the second die(102, col. 2, lines 57-64) to the upper surface of the first die(108, col. 2, lines 57-64), wherein each of the plurality of thermoset regions(104, col. 3, lines 4-23) extends to fill an area between a plurality of adjacent interconnect elements(112, col. 2, line 65- col. 3, line 3) of the first die(108, col. 2, lines 57-64).
Yim is not relied on to teach an underfill material filling remaining open areas between the plurality of interconnect elements of the first die(108, col. 2, lines 57-64).
Chen teaches a semiconductor device assembly(Fig. 1) comprising an underfill material(14, col. 5, lines 54-56) filling remaining open areas between the plurality of interconnect elements(13, col. 4, lines 9-18) of the first die(11, col. 4 line 62- col. 5 line 11). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yim, so that an underfill material filling remaining open areas between the plurality of interconnect elements of the first die, as taught by Chen, so that the thermoset regions and underfill material can be arranged to create strains in different directions in order to adjust the distribution of stress of semiconductor device assembly, so as to attain an optimal control in the degree of warpage of semiconductor device assembly(col. 3, lines 18-26).
Regarding claim 2, Yim teaches the semiconductor device assembly of claim 1, wherein the plurality of thermoset regions(104, col. 3, lines 4-23) includes two thermoset regions(104, col. 3, lines 4-23) located proximate opposite edges(Fig. 2) of the first die(108, col. 2, lines 57-64).
Regarding claim 3, Yim teaches the semiconductor device assembly of claim 1, wherein the plurality of thermoset regions(104, col. 3, lines 4-23) includes four thermoset regions(104, col. 3, lines 4-23) located proximate four corresponding corners(Fig. 2) of the first die(108, col. 2, lines 57-64).
Regarding claim 4, Yim teaches the semiconductor device assembly of claim 1, wherein the area between a plurality of adjacent interconnect elements(112, col. 2, line 65- col. 3, line 3) of the first die(108, col. 2, lines 57-64) is bounded by four interconnect elements(112, col. 2, line 65- col. 3, line 3) arranged in a two-by-two square(Fig. 2).
Regarding claim 5, Yim teaches the semiconductor device assembly of claim 1, wherein the thermoset material(epoxy, silicone, col. 3, lines34-30) comprises one of a non-conductive adhesive material, a non-conductive film (NCF), a thermosetting polymer(epoxy, silicone, col. 3, lines34-30), a thermosetting epoxy(epoxy, silicone, col. 3, lines34-30), or a thin film.
Regarding claim 6, Yim teaches the semiconductor device assembly of claim 5.
Yim is not relied on to teach the underfill material is compatible with the thermoset material(epoxy, silicone, col. 3, lines34-30).
Chen teaches a semiconductor device assembly(Fig. 1) wherein the underfill material(14, col. 5, lines 54-56) is compatible with the thermoset material(15, col. 6 lines 10-16). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yim, so that an underfill material is compatible with the thermoset material, as taught by Chen, so that the thermoset regions and underfill material can be arranged to create strains in different directions in order to adjust the distribution of stress of semiconductor device assembly, so as to attain an optimal control in the degree of warpage of semiconductor device assembly(col. 3, lines 18-26).
Regarding claim 7, Yim teaches the semiconductor device assembly of claim 1.
Yim does not explicitly state each of the thermoset regions(104, col. 3, lines 4-23) are at least 30 microns in lateral extent. However, Yim does teach the area of the thermoset regions(104, col. 3, lines 4-23) are optimized to correspond to positions that exhibit solder joint failure(104, col. 3, lines 4-23). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make each of the thermoset regions are at least 30 microns in lateral extent, since it has been held that when the prior art discloses the general conditions of the claimed invention, discovering the optimum or workable ranges involves only ordinary skill in the art. See MPEP 2144.05.
Regarding claim 8, Yim teaches the semiconductor device assembly of claim 1, wherein each of the thermoset regions(104, col. 3, lines 4-23) are at least 100 microns in lateral extent.
Yim does not explicitly state each of the thermoset regions(104, col. 3, lines 4-23) are at least 100 microns in lateral extent. However, Yim does teach the area of the thermoset regions(104, col. 3, lines 4-23) are optimized to correspond to positions that exhibit solder joint failure(104, col. 3, lines 4-23). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make each of the thermoset regions are at least 100 microns in lateral extent, since it has been held that when the prior art discloses the general conditions of the claimed invention, discovering the optimum or workable ranges involves only ordinary skill in the art. See MPEP 2144.05.
Regarding claim 9, Yim teaches the semiconductor device assembly of claim 1, wherein the plurality of thermoset regions(104, col. 3, lines 4-23) includes a thermoset region located in a central region(not illustrated, underfill in center of package, col. 3, lines 4-23) of the upper surface of the first die(108, col. 2, lines 57-64).
Regarding claim 10, Yim teaches the semiconductor device assembly of claim 1, wherein the electrical connectors(112, col. 2, line 65- col. 3, line 3) are interconnected by solder(110, col. 2, line 65- col. 3, line 3) to the plurality of conductive interconnect elements(112, col. 2, line 65- col. 3, line 3) on the upper surface of the first die(108, col. 2, lines 57-64).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2017/0141071 A1) in view of Chen et al. (US 11,069,661 B1).
Regarding claim 18, Choi teaches a semiconductor device assembly(Fig. 1G), comprising:
a die stack(110, 210, 310, 410, ¶0039, ¶0050) comprising N dies(110, 210, 310, 410, ¶0039, ¶0050) and an uppermost die(410, ¶0039), wherein N is an integer greater than or equal to three, each of the N dies(110, 210, 310, 410, ¶0039, ¶0050) including a plurality of conductive interconnect elements(116, ¶0040) on upper surfaces, wherein a portion of the interconnect elements(116, ¶0040) are connected to through-silicon vias (TSVs)(114, ¶0039) that extend between the upper surfaces and lower surfaces of associated ones of the N dies(110, 210, 310, 410, ¶0039, ¶0050);
a thermoset region(230, ¶0046) between the first and second dies(110, 210, ¶0055), each thermoset region(230, ¶0046) comprising a layer of thermoset material(230, ¶0046) extending from the lower surface of the second die(210, ¶0055) to the upper surface of the first die(110, ¶0055), wherein each of the thermoset regions(230, ¶0046) extends to fill an area between a plurality of adjacent interconnect elements(116, ¶0040) of the first die(110, ¶0055).
Choi is not relied on to teach a plurality of laterally-spaced discrete thermoset regions(230, ¶0046) between the first and second dies(110, 210, ¶0055), each thermoset region(230, ¶0046) comprising a layer of thermoset material(230, ¶0046) extending from the lower surface of the second die(210, ¶0055) to the upper surface of the first die(110, ¶0055), wherein each of the two thermoset regions(230, ¶0046) extends to fill an area between a plurality of adjacent interconnect elements(116, ¶0040) of the first die(110, ¶0055); and
an underfill material filling remaining open areas between the interconnect elements of the N-1 dies.
Chen teaches a semiconductor device assembly(Fig. 1) comprising a plurality of laterally-spaced discrete thermoset regions(15, col. 6 lines 10-16) between the first and second dies(11, col. 4 line 62- col. 5 line 11), each thermoset region(15, col. 6 lines 10-16) comprising a layer of thermoset material(15, col. 6 lines 10-16) extending from the lower surface of the second die(210, ¶0055) to the upper surface of the first die(110, ¶0055), wherein each of the two thermoset regions(15, col. 6 lines 10-16) extends to fill an area between a plurality of adjacent interconnect elements(13, col. 4, lines 9-18) of the first die(11, col. 4 line 62- col. 5 line 11); and an underfill material(14, col. 5, lines 54-56) filling remaining open areas between the interconnect elements(13, col. 4, lines 9-18) of the N-1 dies(11, 15, col. 4 line 62- col. 5 line 27). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Choi, to include a plurality of laterally-spaced discrete thermoset regions between the first and second dies, each thermoset region comprising a layer of thermoset material extending from the lower surface of the second die to the upper surface of the first die, wherein each of the two thermoset regions extends to fill an area between a plurality of adjacent interconnect elements of the first die; and
an underfill material filling remaining open areas between the interconnect elements of the N-1 dies, as taught by Chen, so that the thermoset regions and underfill material can be arranged to create strains in different directions in order to adjust the distribution of stress of semiconductor device assembly, so as to attain an optimal control in the degree of warpage of semiconductor device assembly(col. 3, lines 18-26).
Regarding claim 19, Choi teaches the semiconductor device assembly of claim 18.
Choi does not expletory state the thermoset material(230, ¶0046) comprises one of a non-conductive adhesive material, a non-conductive film (NCF), a thermosetting polymer, a thermosetting epoxy, or a thin film. However, Choi teaches a different thermoset material(130, ¶0042) can comprise a non-conductive film (NCF)(¶0041), a thermosetting polymer(¶0042) and a thermosetting epoxy(¶0042). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the materials of a non-conductive adhesive material, a non-conductive film (NCF), a thermosetting polymer, a thermosetting epoxy, or a thin film for the thermoset material, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use i.e. for an underfill thermoset material, involves only ordinary skill in the art. MPEP 2144.07
Regarding claim 20, Choi teaches the semiconductor device assembly of claim 18.
Choi is not relied on to teach each thermoset region(230, ¶0046) is at least 30 microns in lateral extent, at least 50 microns in lateral extent, or at least 100 microns in lateral extent.
Chen teaches a semiconductor device assembly(Fig. 1) wherein the size of each thermoset regions(15, col. 6 lines 10-16) is optimized to adjust the distribution of stress in the semiconductor device assembly(col. 7, lines 39-60). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make each of the thermoset regions are at least 30 microns in lateral extent, at least 50 microns in lateral extent, or at least 100 microns in lateral extent, since it has been held that when the prior art discloses the general conditions of the claimed invention, discovering the optimum or workable ranges involves only ordinary skill in the art. See MPEP 2144.05.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA DYKES whose telephone number is (571)270-3161. The examiner can normally be reached M-F 9:30 am-5 pm.
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/LAURA M DYKES/Examiner, Art Unit 2892