DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 2 and 4-9 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. There is no support in the original specification for the claim limitations of “the highly-doped layer is electrically inaccessible by the first electrically conductive device terminal and the second electrically conductive device terminal”, as recited in claim 1; and “the highly-doped layer extends across a complete width of the semiconductor device", as recited in claim 9. For examination purposes, the examiner has interpreted these limitations based from the elected embodiment of Fig. 5 as illustrated. Clarification is requested.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 2, 4-6, 8 and 9, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Briere (2011/0284868) in view of Lidow et al. (2012/0153300).
As for claims 1 and 4, Briere shows in Fig. 2 and related text a semiconductor device, comprising:
a base substrate 10, comprising a lower region 14 of type IV semiconductor material extending to a rear surface of the base substrate, a dielectric layer 18 formed directly on the lower region of type IV semiconductor material, and a highly-doped layer 16 of type IV semiconductor material formed directly on the dielectric layer ([0021]-[0023], [0029]-[0030], [0032]),
a first type Ill-V semiconductor layer 22 disposed on the base substrate;
a second type Ill-V semiconductor layer 22 formed on the first type III-V semiconductor layer, the second type Ill-V semiconductor layer having a bandgap different than a bandgap of the first type III-V semiconductor layer such that a two-dimensional charge carrier gas 2-DEG forms at an interface between the first type III-V semiconductor layer and the second type III-V semiconductor layer ([0024]-[0025]);
a first electrically conductive device terminal 26 and a second electrically conductive device terminal 28 each being formed on the second type Ill-V semiconductor layer and each being in ohmic contact with the two-dimensional charge carrier gas ([0026]),
wherein the highly-doped layer is electrically inaccessible by the first electrically conductive device terminal and the second electrically conductive device terminal.
Briere do not disclose the highly-doped layer having a doping concentration that is at least two orders of magnitude greater than a doping concentration of the lower region of type IV semiconductor material (claim 1); and net doping concentration of the highly-doped layer is at least 1018 dopant atoms/cm3 (claim 4).
Lidow et al. teach in Fig. 8 and related text:
As for claim 1, a highly-doped layer 89 having a doping concentration that is at least two orders of magnitude greater than a doping concentration of the lower region of type IV semiconductor material ([0053], lines 3-5; [0076]).
As for claim 4, a net doping concentration of the highly-doped layer is at least 1018 dopant atoms/cm3 ([0079], lines 3-5).
Briere and Lidow et al. are analogous art because they are directed to a HEMT and one of ordinary skill in the art would have had a reasonable expectation of success to modify Briere with the specified feature(s) of Lidow et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to form the highly-doped layer having a doping concentration that is at least two orders of magnitude greater than a doping concentration of the lower region of type IV semiconductor material; and net doping concentration of the highly-doped layer being at least 1018 dopant atoms/cm3, as taught by Lidow et al., in Briere's device, in order to reduce resistivity, leakage current and cost of the device.
Generally, differences in concentration do not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955). See also In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Laboratories Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989), and In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990).
As for claim 2, the combined device shows the semiconductor device is a high-electron-mobility-transistor, wherein the first electrically conductive device terminal is a source terminal, and wherein the second electrically conductive device terminal is a drain terminal (Briere: Fig. 2; [0026]).
As for claim 5, the combined device shows the lower region of type IV semiconductor material is a first conductivity type region, and wherein the highly-doped layer of type IV semiconductor material is a second conductivity type region (Briere: [0029]; [0030]; [0032]; Lidow: [0053]-[0054]; [0075]-[0076]).
As for claim 6, the combined device shows the lower region of type IV semiconductor material and the highly-doped layer of type IV semiconductor material are each a region of silicon (Briere: [0021]).
As for claim 8, the combined device shows the first type III-V semiconductor layer is a layer of gallium nitride, and wherein the second type Ill-V semiconductor layer is layer of aluminum gallium nitride (Briere: [0025]).
As for claim 9, the combined device shows the highly-doped layer extends across a complete width of the semiconductor device (Briere: Fig. 2).
Claim(s) 7, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Briere (2011/0284868) and Lidow et al. (2012/0153300) in view of Hamamoto (2007/0087514).
Briere and Lidow et al. disclosed substantially the entire claimed invention, as applied to claim 1 above, including the lower region of type IV semiconductor material is a region of silicon ([0061]).
Briere and Lidow et al. do not disclose the highly-doped layer of type IV semiconductor material is a region of polysilicon.
Hamamoto teaches in Fig. 1 and related text an upper portion 10b of type IV semiconductor material is a region of polysilicon ([0016], lines 8-10).
Briere, Lidow et al. and Hamamoto are analogous art because they are directed to a SOI substrate and one of ordinary skill in the art would have had a reasonable expectation of success to modify Briere and Lidow et al. with the specified feature(s) of Hamamoto because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to use polysilicon, as an upper portion of SOI substrate, as taught by Hamamoto, in Briere and Lidow et al.'s device, in order to increase the interconnects and the transistor density, and reduce cost of the device.
Response to Arguments
Applicant's arguments filed July 1, 2026 have been fully considered but they are not persuasive.
Applicant argues that “amended claim 1 recites, inter alia, wherein the highly-doped layer is electrically inaccessible by the first electrically conductive device terminal and the second electrically conductive device terminal. Support for this clarifying amendment can be found in Applicant's FIG. 5, which illustrates first and second electrically conductive device terminals 114, 116 terminating in first type III-V semiconductor layer 108 and thus separated from and unable to electrically access the highly-doped layer 138”.
The examiner respectfully disagrees because it is well known in the art that some leakage exists in a real semiconductor device.
Fig. 5 merely shows that first and second electrically conductive device terminals 114, 116 are not in direct contact with the highly-doped layer 138, which does not prove that “the highly-doped layer is electrically inaccessible by the first electrically conductive device terminal and the second electrically conductive device terminal”.
Furthermore, paragraphs [0022]-[0023] disclose that transition region 104 includes one or more lattice transition layers to alleviate crystalline lattice-mismatach stress, which implies that the purpose of the transition region is for structural/crystallographic, not electrical isolation.
Therefore, the new limitation of amended claim 1 is not support in the original specification and contains new matter.
Applicant argues that “the claim 9 limitation "wherein the highly-doped layer extends across a complete width of the semiconductor device” is not new matter because “FIG. 5 illustrates semiconductor device 100. In FIG. 5, the highly-doped layer 138 extends across a complete width of the semiconductor device 100. Applicant's FIG. 5 therefore provides direct, literal support for claim 9”.
The examiner respectfully disagrees because Fig. 5 only shows a cross-section view of the invention, the highly-doped layer extending across the entire illustrated cross section is not necessarily the same as extending across a complete width of the semiconductor device.
Therefore, the limitation of claim 9 is not support in the original specification and contains new matter.
Applicant argues that “withdrawal of all § 103 rejections is therefore respectfully requested” because 1) “according to Briere's teachings, the first and second power electrodes 26/28 are not in ohmic contact with the alleged two-dimensional charge carrier gas in Briere's first III-nitride layer 22 (the alleged first type IV semiconductor layer). Rather, Briere teaches "first and second power electrodes 26 and 28 (e.g., source and drain electrodes) coupled to the 2DEG through second III-nitride layer 24, and gates 30 situated between respective first and second power electrodes 26 and 28” (Emphasis added)” and 2) “The purpose of Lidow's conductive well 51 and SOI layer 89 is obviously directly related to the presence of a connection via between the front side and back side of Lidow's devices 400 and 800, and more specifically terminating the connection via in the conductive well 51 / SOI layer 89 to address the issue of isolating from the substrate potential, particularly in configurations in which a heat sink is connected to the back side of the substrate. Thus, any properties of the conductive 51 and SOI layer 89, including doping concentration and type relative to the substrate on which they are formed, are also directly related to the connection via and its termination in the conductive well 51 / SOI layer 89. Briere's device does not include such a via or other electrical connection between the first or second power electrode 26/28 and the second silicon body 16 (the alleged highly-doped layer) to form a connection between the front side and the back side of the device; nor does Briere teach a heatsink connected to the substrate or suggest any issues with substrate potential”.
The examiner respectfully disagrees because:
1) it is well known in the art that for an AlGaN/GaN HEMT, the two-dimensional charge carrier gas (2DEG) exists at the AlGaN/GaN interface and the source/drain electrodes each can establish ohmic electrical contact to that 2DEG through the semiconductor/metal contact structure without the electrodes literally touching the 2DEG at the interface.
Furthermore, broad limitation does not require the first electrically conductive device terminal and the second electrically conductive device terminal each to be in direct/physical contact with the 2DEG.
2) Lidow was not cited to teach an artisan the entire structure of the claimed invention. Lidow was merely cited to teach an artisan the limitations of “the highly-doped layer having a doping concentration that is at least two orders of magnitude greater than a doping concentration of the lower region of type IV semiconductor material”; and “net doping concentration of the highly-doped layer is at least 1018 dopant atoms/cm3”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEIYA LI whose telephone number is (571)270-1572. The examiner can normally be reached Monday-Friday 7AM-3PM.
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/MEIYA LI/Primary Examiner, Art Unit 2811
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