DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/04/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Status of Application
In response to Office action mailed 06/17/2025, Applicants amended claims 1-3, 9, 11-14 and 16 in the response filed 10/17/2025.
Claim(s) 1-20 are pending examination.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the arguments do not apply to the new combination of references being used in the current rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3, 12-14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Geissler et al. (PG Pub 2018/0331080; hereinafter Geissler) and Hu et al. (PG Pub 2020/0343218; hereinafter Hu).
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Regarding claim 1, refer to the Examiner’s modified mark-up of Fig. 10g (as supported by Fig. 5), Geissler teaches a semiconductor package (see claim limitations below), comprising:
a main semiconductor chip (annotated “main-1” in Fig. 10g) having a first thickness (annotated “t-1” in Fig. 10g);
a first semiconductor device (annotated “device-1” in Fig. 10g) disposed on a first side of the main semiconductor chip (e.g. left side) and having a second thickness (annotated “t-2” in Fig. 10g) less than the first thickness (t2 < t1; see Fig. 10g and Fig. 5);
a second semiconductor device (annotated “device-2” in Fig. 10g) disposed on a second side of the main semiconductor chip (e.g. right side) and having a third thickness (annotated “t-3” in Fig. 10g) less than the first thickness (t3 < t1);
a first molding layer 730 that covers the main semiconductor chip and the semiconductor device so as to expose a top surface of the semiconductor device (top of device-1) and to expose a top surface (top of main-1) and a portion of a lateral surface of the main semiconductor chip (the top portion over and through RDL-2) (see Fig. 10g);
a first redistribution substrate (annotated “RDL-1” in Fig. 10g) below the first molding layer (see Fig. 10g);
a second redistribution substrate (annotated “RDL-2” in Fig. 10g) on the first molding layer; and
a mold via 220 that penetrates the first molding layer and connects the first redistribution substrate to the second redistribution substrate (see Fig. 10g).
Although, Geissler teaches the second semiconductor device is disposed between the first redistribution substrate and the second redistribution substrate in a vertical direction, Geissler does not teach “the second semiconductor device includes a first semiconductor chip and a second semiconductor chip.”
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In the same field of endeavor, refer to Fig. 3 provided above, Hu teaches a semiconductor package 10, comprising: a main semiconductor chip IC1 (para [0082]) having a first thickness (annotated “t1” in Fig. 3);
a first semiconductor device (annotated “device-1” in Fig. 3 above) disposed on a first side of the main semiconductor chip (e.g. right side) and having a second thickness (annotated “t2” in Fig. 3 above) less than the first thickness (see Fig. 3); and a second semiconductor device having a third thickness (annotated “t-3” in Fig. 3) less than the first thickness (t3 < t1); wherein the second semiconductor device includes a first semiconductor chip (c1-1) and a second semiconductor chip (cl-2) (see Fig. 3).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second device comprise multiple components, as taught by Hu, to provide a more robust package.
Regarding claim 2, refer to the figures cited above, Geissler and Hu teach the first semiconductor chip (c1-1 of Hu) includes a first chip pad (annotated “pad-1” in Fig. 3), and the first semiconductor chip is oriented such that the first chip pad faces the first redistribution substrate (RDL-1 of Geissler) and is connected to the first redistribution substrate via the first chip pad (see Fig. 3 and Fig.10g), and wherein the second semiconductor chip (c1-2 or Hu) includes a second chip pad (annotated “pad-2” in Fig. 3), and the second semiconductor chip is stacked on the first semiconductor chip and is oriented such that the second chip pad faces the second redistribution substrate (RDL-2 of Geissler) and is connected to the second redistribution substrate via the second chip pad (see Fig. 3 and Fig.10g).
Regarding claim 3, refer to the figures cited above, Geissler and Hu teach an adhesion layer (annotated “adhesive” in Fig. 3 above) is disposed between the stacked first semiconductor chip C1-1 and the second semiconductor chip c1-2 in the vertical direction (see Fig. 3), and wherein a top surface of the first molding layer 730-Geissler is coplanar with a top surface of the second semiconductor chip (see Fig. 10g).
Regarding claim 12, refer to the Examiner’s modified mark-up of Fig. 10g (as supported by Fig. 5), Geissler teaches a semiconductor package (see claim limitations below), comprising:
a first redistribution substrate (annotated “RDL-1”);
a main semiconductor chip (annotated “main-1”) on the first redistribution substrate (see Fig. 10g);
a second redistribution substrate (annotated “RDL-2”) on the first redistribution substrate, a top surface of the second redistribution substrate being at a level lower than a level of the main semiconductor chip (lower than the top level of the main semiconductor chip);
a first molding layer 730 between the first redistribution substrate and the second redistribution substrate (see Fig. 10g);
a second molding layer 980 that covers the second redistribution substrate and exposes a top surface of the main semiconductor chip (main-top).
Although, Geissler teaches the second semiconductor device is disposed between the first redistribution substrate and the second redistribution substrate in a vertical direction, Geissler does not teach “the second semiconductor device includes a first semiconductor chip and a second semiconductor chip.”
In the same field of endeavor, refer to Fig. 3 provided above, Hu teaches a semiconductor package 10, comprising: a main semiconductor chip IC1 (para [0082]) having a first thickness (annotated “t1” in Fig. 3); a first semiconductor device (annotated “device-1” in Fig. 3 above) disposed on a first side of the main semiconductor chip (e.g. right side) and having a second thickness (annotated “t2” in Fig. 3 above) less than the first thickness (see Fig. 3); and a second semiconductor device having a third thickness (annotated “t-3” in Fig. 3) less than the first thickness (t3 < t1); wherein the second semiconductor device includes a first semiconductor chip (c1-1) and a second semiconductor chip (cl-2) (see Fig. 3).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second device comprise multiple components, as taught by Hu, to provide a more robust package.
Regarding claim 13, refer to the figures cited above, Geissler and Hu teach the semiconductor device (“device-2”) is horizontally spaced apart from the main semiconductor chip (main-1) (see Fig. 3 or Fig. 10g), and wherein first semiconductor chip (c1-1) is oriented such that the first chip pads (annotated “pad-2” in Fig. 3) face the first redistribution substrate (RDL-1 =RDLi) and is connected to the first redistribution substrate via the first chip pads (see Fig. 3 or Fig. 10g), and wherein the second semiconductor chip C1-2 includes second chip pads (annotated “pad-2”), and the second semiconductor chip is stacked on the first semiconductor chip and is oriented such that the second chip pads face the second redistribution substrate (“RDL-2”) and is connected to the second redistribution substrate via the second chip pads (see Fig. 3).
Regarding claim 14, refer to the figures cited above, Geissler and Hu teach the first semiconductor chip (C1-1) and the second semiconductor chip (C1-2) are different types from each other (para [0051] and {0070]), wherein an adhesion layer (annotated “adhesion” in Fig. 3 above) is disposed between the stacked first semiconductor chip and the second semiconductor chip (see Fig. 3), and wherein a top surface of the first molding layer 7630 is coplanar with a top surface of the second semiconductor chip (noted as “device-1”).
Regarding claim 16, refer to the figures cited above, Geissler and Hu teach first chip pads (“pad-1”-Hu) are adjacent to a bottom surface of the first semiconductor chip (c1-1), the second semiconductor chip C1-2 includes second chip pads (“pad-2”) are adjacent to a top surface of the second semiconductor chip (see Fig. 3), the first redistribution substrate (RDL-1 of Geissler) includes first redistribution patterns that contact the first chip pads (see Fig. 10g), and the second redistribution substrate (RDL-2 of Geissler) includes second redistribution patterns that contact the second chip pads (see Fig. 10g).
Claim(s) 4 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Geissler and Hu, as applied to claim 3 and claim 14 above, and further in view of Kim et al. (PG Pub 2020/0273801; hereinafter Kim).
Regarding claim 4, refer to the figures cited above, Geissler and Hu teach the first semiconductor chip (“main-1” of Geissler). He does not teach the first semiconductor chip is a capacitor including silicon (Si).
In the same field of endeavor, refer to Fig.10, Kim teaches a semiconductor package (para [0019- 0091]) comprising: a first semiconductor chip 3830 (para [0091]) is a capacitor (para [0091]) including silicon (para [0091]).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the material composition of the capacitor comprise silicon, as taught by Kim, for the purpose of choosing a suitable and well-known capacitor material composition.
Regarding claim 15, refer to the figures cited above, Geissler and Hu teach the first semiconductor chip (“main-1” of Geissler). He does not teach the first semiconductor chip is a capacitor including silicon (Si).
In the same field of endeavor, refer to Fig.10, Kim teaches a semiconductor package (para [0019- 0091]) comprising: a first semiconductor chip 3830 (para [0091]) is a capacitor (para [0091]) including silicon (para [0091]), and the second semiconductor chip is one of a near field communication (NFC) controller and a touch screen controller chip.
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the material composition of the capacitor comprise silicon, as taught by Kim, for the purpose of choosing a suitable and well-known capacitor material composition.
Note: The recited “the second semiconductor chip is one of a near field communication (NFC) controller and a touch screen controller chip” (i.e., function) does not structurally distinguish an apparatus claim from the prior art apparatus see In re Danly, 263 F.2d 844, 838 (CCPA 1959) (apparatus claims must distinguish in terms of structure rather than function). The only structural limitation that appears to be required for the prior art apparatus to be capable of performing the aforementioned function is having a second semiconductor chip, which Kim clearly shows or in other words, the prior art appears to inherently possess the capability of performing the recited functions. "[T]he discovery of a previously unappreciated property of a prior art composition, or of a scientific explanation for the prior art's functioning, does not render the old composition patentably new to the discoverer." Atlas Powder Co. v. IRECO Inc., 190 F.3d 1342, 1347, 51 USPQ2d 1943, 1947 (Fed. Cir. 1999). Thus, the claiming of a new use, new function or unknown property which is inherently present in the prior art does not necessarily make the claim patentable. In re Best, 562 F.2d 1252, 1254, 195 USPQ 430, 433 (CCPA 1977). See In re Swinehart, 439 F.2d 210 (CCPA 1971) to emphasize that “where the Patent [and Trademark] Office has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter may, in fact be an inherent characteristic of the prior art, it possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on.").
Claim(s) 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over Geissler and Hu, as applied to claim 3 and claim 4 above, and further in view of Huang et al. (PG Pub 2020/0321288; hereinafter Huang).
Regarding claim 5, refer to the figures cited above, Geissler and Hu teach the first redistribution substrate (“RDL-1”) comprises embedding electrical conductive redistribution connections in a dielectric (para [0077]), he does not explicitly teach the details of the redistribution substrate such that “a first redistribution dielectric layer and first redistribution patterns in the first redistribution dielectric layer, wherein each of the first redistribution patterns includes a first line part and a first via part on the first line part.”
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In the same field of endeavor, refer to Fig.10a, Huang teaches a redistribution layer structure (para [0017-0055]) comprising: a first redistribution dielectric layer (110, 120, 130 and 140; para [0039]) and first redistribution patterns (113/115) in the first redistribution dielectric layer, wherein each of the first redistribution patterns includes a first line part 113 and a first via part 115 on the first line part (see Fig. 10a).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the RDL of Geissler comprise the structural elements, as taught by Huang, to re-route or redistribute signals to/from the device (para [0039]).
Regarding claim 6, refer to the figures cited above, Geissler and Hu teach the second redistribution substrate (‘RDL-2") comprises embedding electrical conductive redistribution connections in a dielectric (para [0077]), he does not explicitly teach the details of the second redistribution substrate “includes a second redistribution dielectric layer and a second redistribution pattern in the second redistribution dielectric layer, wherein the second redistribution pattern includes a second line part and a second via part below the second line part.”
In the same field of endeavor, refer to Fig.10a, Huang teaches a redistribution layer structure (para [0017-0055]) comprising: a second redistribution dielectric layer (110, 120, 130 and 140; para [0039]) and first redistribution patterns (113/115) in the first redistribution dielectric layer, wherein each of the first redistribution patterns includes a first line part 113 and a first via part 115 on the first line part (see Fig. 10a).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the RDL of Geissler comprise the structural elements, as taught by Huang, to re-route or redistribute signals to/from the device (para [0039]).
Regarding claim 7, refer to the figures cited above, Geissler and Hu teach a third semiconductor device (F) on the second redistribution pattern (‘RDL-2"), wherein the second redistribution pattern comprises via structures (annotated “via structs” in Fig. 10g), wherein the via structures include: a first via structure (annotated “a”) that connects the third semiconductor device and the second semiconductor chip (device-2) to each other (see Fig. 10g); and a second via structure (via adjacent to the “via struct”) that connects the second semiconductor chip and the mold via to each other (see Fig. 10g).
Regarding claim 8, refer to the figures cited above, in the combination of Geissler and Hu, Geissler teaches the second semiconductor chip (“device-2”) is connected through the second via structure (“via struct”) to the first redistribution substrate (‘RDL-1") and is one of a near field communication (NFC) controller and a touch screen controller chip.
The recited “is one of a near field communication (NFC) controller and a touch screen controller chip.” (i.e., function) does not structurally distinguish an apparatus claim from the prior art apparatus see In re Danly, 263 F.2d 844, 838 (CCPA 1959) (apparatus claims must distinguish in terms of structure rather than function). The only structural limitation that appears to be required for the prior art apparatus to be capable of performing the aforementioned function is having the second semiconductor chip, which Geissler clearly shows or in other words, the prior art appears to inherently possess the capability of performing the recited functions. "[T]he discovery of a previously unappreciated property of a prior art composition, or of a scientific explanation for the prior art's functioning, does not render the old composition patentably new to the discoverer." Atlas Powder Co. v. IRECO Inc., 190 F.3d 1342, 1347, 51 USPQ2d 1943, 1947 (Fed. Cir. 1999). Thus, the claiming of a new use, new function or unknown property which is inherently present in the prior art does not necessarily make the claim patentable. In re Best, 562 F.2d 1252, 1254, 195 USPQ 430, 433 (CCPA 1977). See In re Swinehart, 439 F.2d 210 (CCPA 1971) to emphasize that “where the Patent [and Trademark] Office has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter may, in fact be an inherent characteristic of the prior art, it possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on.").
Regarding claim 9, refer to the figures cited above, in the combination of Geissler and Hu, Geissler teaches a second molding layer 980 that covers the third semiconductor device 130 and exposes the top surface of the main semiconductor chip (“main-1”).
He does not teach a top surface of the third semiconductor chip is at a level lower than a level of the top surface of the main semiconductor chip.
However, it would have been obvious, to one of ordinary skill in the art, to choose from a finite number of identified, predictable solutions, such as to have the top surface of the third semiconductor chip be at a lever lower then, equal to or greater than a level of the top surface of the main semiconductor chip to achieve the same desired outcome (see MPEP 2143 (1)(E) and KSR, 550 U.S. at 421, 82 USPQ2d at 1397).
Regarding claim 10, refer to the figures cited above, in the combination of Geissler and Hu, Geissler teaches a top surface of the second molding layer 980-top is coplanar with the top surface of the main semiconductor chip (“main-1”) (see Fig. 10g).
Geissler does not teach the top surface of the second molding layer is coplanar with the top surface of the main semiconductor chip.
However, it would have been obvious, to one of ordinary skill in the art, to choose from a finite number of identified, predictable solutions, such as to have the top surface of the second molding layer either be coplanar with, higher than or less than the top surface of the main semiconductor chip, with a reasonable expectation of achieving the same desired outcome (see MPEP 2143 (I)(E) and KSR, 550 U.S. at 421, 82 USPQ2d at 1397).
Allowable Subject Matter
Claims 17-20 are allowable.
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 11 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 11, a fourth semiconductor device on the second redistribution pattern and spaced apart from the third semiconductor device and on an opposite side of the main semiconductor chip.
Claim 17 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 17, a main semiconductor chip; a first redistribution substrate below the main semiconductor chip; external connection terminals bonded to a bottom surface of the first redistribution substrate; first redistribution pattems in the first redistribution substrate; a second redistribution substrate that extends parallel to the first redistribution substrate and extends in an outward direction from a lateral surface of the main semiconductor chip, second redistribution pattems in the second redistribution substrate; at least one semiconductor device between the first redistribution substrate and the second redistribution substrate; a first molding layer between the first redistribution substrate and the second redistribution substrate, the first molding layer covering a portion of the lateral surface of the main semiconductor chip; and a second molding layer that covers the second redistribution substrate and another portion of the lateral surface of the main semiconductor chip, the second molding layer exposing a top surface of the main semiconductor chip, wherein each of the first redistribution pattems includes a first line part and a first via part on the first line part, wherein each of the second redistribution pattems includes a second line part and a second via part on the second line part, wherein one of the first and second redistribution pattems transmits a power, wherein another of the first and second redistribution pattems transmits a signal, wherein the main semiconductor chip has a first thickness, wherein the at least one semiconductor device has a second thickness, and wherein the first thickness is about 2 to 5 times the second thickness Claims 18-20 would be allowable, because they depend on allowable claim 17.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F).
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/CHRISTINA A SYLVIA/Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817