DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on March 22, 2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 21, 2023 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Memory Device With Improved Word Line Failure
Election/Restrictions
Applicant’s election without traverse of Group I (Claims 1-16) in the reply filed on October 14, 2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-7, and 9-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2020/0273881). Claim 1, Kim discloses (annotated Fig. 2 below, Figs. 3A-3B) a semiconductor memory device, comprising: a first dummy stacked body (D1, STd, dummy stack structure, Para [0060]) and a second dummy stacked body (D2, STd, dummy stack structure, Para [0060]) formed in a connection area (LAR, connection regions, Para [0036]) of a substrate (SUB, substrate, Para [0089]) including a cell array area (CAR, cell array region, Para [0099]) and the connection area (SUB includes LAR and CAR); a cell stacked body (STc, cell stack structure, Para [0036]) disposed in the cell array area and the connection area (STc is disposed in CAR and LAR) and configured to enclose the first dummy stacked body and the second dummy stacked body (STc encloses D1 and D2); and a first vertical barrier (VB1, VB, vertical barrier, Para [0035]) disposed at a boundary between the cell stacked body and the first dummy stacked body (VB1 is disposed at a boundary between STc and D1) and a second vertical barrier (VB2, VB, vertical barrier, Para [0035]) disposed at a boundary between the cell stacked body and the second dummy stacked body (VB2 is disposed at a boundary between STc and D2), wherein the cell stacked body (STc) comprises first (E1) and second extensions (E2) disposed to extend in substantially a linear shape in the connection area (E1 and E2 have vertical linear shapes in LAR) and a connector (connector) configured to connect the first and second extensions to each other (connector connects E1 to E2).
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Claim 2, Kim discloses (annotated Fig. 2 above, Figs. 3A-3B) the semiconductor memory device according to claim 1, wherein the first vertical barrier (VB1) and the second vertical barrier (VB2) are disposed in the connection area and spaced apart from each other (VB1 and VB2 are disposed in LAR and spaced apart from each other in the lateral direction). Claim 3, Kim discloses (annotated Fig. 2 above, Figs. 3A-3B) the semiconductor memory device according to claim 2, wherein each of the first vertical barrier (VB1) and the second vertical barrier (VB2) has a shape of a rectangular frame (VB1 and VB2 have the shape of a rectangular frame).
Claim 5, Kim discloses (annotated Fig. 2 above, Figs. 3A-3B) the semiconductor memory device according to claim 1, wherein the first vertical barrier (VB1) comprises (Fig. 3A shows makeup of VBs): an inner wall dielectric layer (MLc, dielectric layer, Para [0053]) extending to enclose a sidewall of the first dummy stacked body (MLc encloses a sidewall of STd); a semiconductor pattern (SE, semiconductor pattern, Para [0053]) extending to enclose the inner wall dielectric layer (SE encloses MLc on the left side); and an outer wall dielectric layer (MLd, dielectric layer, Para [0053]) extending to enclose the semiconductor pattern while facing the inner wall dielectric layer (MLd encloses SE when SE is facing MLc).
Claim 6, Kim discloses (annotated Fig. 2 above, Figs. 3A-3B) the semiconductor memory device according to claim 5, wherein the first vertical barrier further comprises (Fig. 3A): a core insulating layer (CO1, first core insulating layer, Para [0053]) enclosed by the semiconductor pattern (CO1 is enclosed by SE). Claim 7, Kim discloses (annotated Fig. 2 above, Figs. 3A-3B) the semiconductor memory device according to claim 1, wherein the cell stacked body (STc) comprises: a plurality of interlayer insulating layers (ILD, interlayer insulating layers, Para [0061]) and a plurality of conductive patterns (CP1-CPn, conductive patterns, Para [0061]) that are alternately stacked (ILD and CP1-CPn are alternately stacked).
Claim 9, Kim discloses (annotated Fig. 2 above, Figs. 3A-3B) the semiconductor memory device according to claim 1, further comprising: a source select line separation structure (Fig. 2, middle SI1, first slit, Para [0036]) configured to partially penetrate a lower portion of the cell stacked body (middle SI1 would penetrate lower portion of CAR) between the first vertical barrier and the second vertical barrier of the connection area (middle SI1 is between VB1 and VB2in LAR as shown in annotated Fig. 2 above). Claim 10, Kim discloses (annotated Fig. 2 above, Figs. 3A-3B) the semiconductor memory device according to claim 1, further comprising: at least one first contact plug (Fig. 3A, CTP, contact plug would penetrate D1, Para [0039], hereinafter “CP1”) configured to penetrate the first dummy stacked body (CP1 penetrates D1); and at least one second contact plug (Fig. 3A, CTP, contact plug would penetrate D2, Para [0039], hereinafter “CP2”) configured to penetrate the second dummy stacked body (CP2 penetrates D2).
Allowable Subject Matter
Claims 4 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Kim (US 2020/0273881), Lee (US 2018/0247953), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 4, wherein the connector is disposed in a space between the first vertical barrier and the second vertical barrier.
Regarding Claim 8, each of the plurality of conductive patterns has one of substantially an H- shape and substantially a ladder shape in the connection area.
Claims 11-16 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Kim (US 2020/0273881), Lee (US 2018/0247953), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 11 (from which claims 12-16 depend), a connector disposed in a space between the first vertical barrier and the second vertical barrier and configured to connect the first extension and the second extension to each other.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee (US 2018/0247953) discloses (Fig. 12B) dummy stacks DM with dummy pillars DPL used as a support for the manufacturing process (Para[ 0154]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/G.G.R/Examiner, Art Unit 2812