Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-43 are pending in this application.
Applicant elected without traverse invention I (claims 1-6, 19-24) in the reply filed on November 5, 2025.
Claims 7-18 and 25-43 remain withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on November 5, 2025.
The Examiner notes that claims 1-6 and 19-24 are examined and claims 7-18 and 25-43 are withdrawn.
Priority
Acknowledgement is made to claims of priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2022-0110436, filed on September 1, 2022.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed February 25, 2026. Claims 1, 5, 19-21 and 23 are amended. Claims 7-18 and 25-43 remain withdrawn. Claims 1-6 and 19-24 are examined.
Claim Objections
Claims 19-24 are objected to because of the following informalities:
In claim 19, “stacke” should read “stack”
Appropriate correction is required.
Claims 20-24 are objected to at least on the same basis as the claims from which they depend.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 5, and 6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites “a protective layer disposed on the source line.” This limitation is repeated from independent claim 1 upon which claim 2 depends. It is indefinite if this refers to the same or a different protective layer. For the purpose of this action, the Examiner will treat the repeated limitation as if it was only recited in claim 1.
Claims 5 and 6 are rejected at least on the same basis as the claims from which they depend.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang (US 2016/0163389 A1).
With respect to claim 1, Zhang teaches in Fig. 29A:
A semiconductor memory device comprising:
a gate stack (stack of insulating layers 32 and conductive layers 46) including a plurality of gate patterns (46) and a plurality of interlayer insulating layers (32) alternately stacked with each other in a cell region;
a source line (source electrode 26) disposed on the gate stack (on bottom side of gate stack);
and a channel plug (passing through the gate stack and the source line in a vertical direction,
wherein the channel plug (pillar structure that includes 68, 66, 60, 63, 30, and 50) comprises:
a backgate (back gate electrode 68);
a backgate insulating layer (back gate dielectric 66) surrounding a sidewall of the backgate;
a channel layer (channel 60) surrounding the sidewall of the backgate;
and a memory layer (memory film 50) surrounding a sidewall of the channel layer,
and wherein the backgate (66) insulating layer extends between the backgate (68) and the source line (26).
wherein the backgate insulating layer (66) contacts the protective layer (132, the Examiner notes that “contacts” can refer to physical, thermal, or electrical contact. 132 is in thermal and electrical contact through 14, which is both a thermal and electrical conductor, and is also in indirect physical contact through semiconductor channel 60)
With respect to claim 2, Zhang further teaches:
further comprising:
a protective layer (dielectric material portion 13) disposed on the source line (26);
and a backgate line (conductive material layer 14) structure disposed on the protective layer (13),
wherein the backgate line structure (14) is electrically connected to the backgate (68) (14 is a conductor and is in direct contact with 68).
With respect to claim 3, Zhang further teaches:
wherein the source line (26) is directly connected to a portion of the sidewall of the channel layer (in direct contact with source region 30, which may be considered a part of the channel layer as the source region is the physically exposed part of semiconductor channel 60 into which dopants have been introduced, para. 178. Alternatively, the source region 30 can be considered a part of the source line along with 26 and 30 is in contact with channel region 60)
With respect to claim 4, Zhang further teaches:
further comprising:
a wiring passing (via structure 76) through the gate stack (32 and 46) and connected to the source line (26).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 2016/0163389 A1) as applied to claim 2 above and further in view of Noh (US 2021/0193678 A1).
With respect to claim 5, Zhang teaches all limitations of claim 2 upon which claim 5 depends. Zhang fails to teach:
further comprising:
a stack including the plurality of interlayer insulating layers and a plurality of sacrificial layers alternately stacked in a contact region; a buffer insulating layer disposed on the stack;
and a contact plug passing through the stack and the buffer insulating layer in the vertical direction.
Noh teaches in Fig. 3a:
a stack including the plurality of interlayer insulating layers (112) and a plurality of sacrificial layers (114) alternately stacked in a contact region;
a buffer insulating layer (buried insulating layer 46) disposed on the stack;
and a contact plug (TSV 170) passing through the stack and the buffer insulating layer in the vertical direction.
With respect to claim 6, the structure of Noh does not include a backgate line structure and therefore the contact plug is not electrically connected to a backgate line structure. It would be obvious when modifying Zhang in view of Noh to space the contact plug apart from the backgate line structure to meet the limitation:
wherein the backgate line structure is electrically spaced apart from the contact plug.
The ordinary artisan would be motivated to modify Zhang as described above in order to prevent electrical shorts between the backgate line structure and the peripheral circuit structure in other parts of the device.
Claims 19-23 are rejected under 35 U.S.C. 103 as being unpatentable over Ishihara (US 2011/0309432 A1) in view of Choi (US 2021/0134832 A1).
With respect to claim 19, Ishihara teaches in Fig. 17-18:
A semiconductor memory device comprising:
a gate stack (electrode films 62 and inter-electrode insulating films 61) including a plurality of gate patterns (62) and a plurality of interlayer insulating layers (61) alternately stacked with each other in a cell region (see annotated Fig. 17 below) and a slimming region (see annotated Fig. 17 below);
a source line (source line SL) disposed on the gate stack of the cell region;
and a channel plug (pillar including first conductive pillar PBG and surrounding films 43, 48, 42, and 49), passing through the gate stack of the cell region and a backgate connection structure passing through the gate stack of the slimming region (conductive pillar PBG serves as a back gate, para. 108, and is included in the slimming region as defined by annotated Fig. 17 below).
wherein the channel plug comprises:
a backgate (PBG);
a backgate insulating layer (inner insulating film 49 and insulating layer BGIaa) surrounding a sidewall of the backgate (PBG);
a channel layer (semiconductor pillar SP) surrounding the sidewall of the backgate;
wherein the backgate (PBG) includes a first portion passing through the gate stack (stack of 61 and 62) of the cell region, and a second portion disposed over the source line (SL) (see annotated Fig. 18 below), and
wherein the first portion and the second portion are connected to each other
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Ishihara fails to teach:
a source pattern including a first source layer, a poly silicon layer, and a second source layer disposed on the gate stack of the slimming region;
a separation pattern separating the source line from the source pattern in a boundary region between the cell region and the slimming region;
Choi teaches in Fig. 13:
a source pattern (second semiconductor patterns 20B), which including a first source layer (first semiconductor layer 21), a channel coupling pattern (channel coupling pattern 121), and a second source layer (semiconductor layer 29) disposed on the gate stack of the slimming region (portion on right side);
a separation pattern (insulating layer 335) separating the source line (semiconductor pattern 20A, para. 72 “first semiconductor pattern 20A may serve as the source select line SSL”) from the sacrificial pattern (20B) in a boundary region between the cell region and the slimming region;
Choi teaches that the channel coupling pattern is a doped semiconductor but does not teach that it is poly silicon. The Examiner takes official notice that polysilicon is a well-known material that can be used as a doped semiconductor in a source layer. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to look to analogous art teaching(s) of alternative suitable or useful material such as poly silicon, as the selection of a known material based on its suitability for intended purpose deemed obvious. See MPEP 2144.07.
Ishihara discloses the claimed invention except for sacrificial pattern separated from the source line by a separation pattern. Choi discloses that it is known in the art to make a source layer from three layers of semiconductor. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to Ishihara with the layers of Choi in order to make a source layer that may perform erase operations by using a GIDL (para. 49 of Choi). See MPEP 2144.
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With respect to claim 20, Ishihara further teaches:
and a memory layer (memory layer 48) surrounding a sidewall of the channel layer,
and the backgate insulating layer (BGIAA) extends between the backgate (PBG) and the source line (SL) (a portion of 49 or BGIaa extends along the fill length of the backgate).
With respect to claim 21, Ishihara further teaches:
wherein the backgate connection structure comprises (pillar through the slimming region as defined in annotated Fig. 17 above):
a backgate oxide layer (inner oxide layer 49 in slimming region, which may be silicon oxide according to para. 110);
the channel layer (SP) surrounding a sidewall of the backgate oxide layer (49);
and the memory layer (48) surrounding a sidewall of the channel layer.
With respect to claim 22, Ishihara further teaches:
further comprising:
a protective layer (interlayer insulating film 23) disposed on the source line (SL);
and a backgate line structure (backgate line BGL) disposed on the protective layer (23),
wherein the backgate line structure electrically connects the backgate of the channel plug and the channel layer of the backgate connection structure (BGL is connected to PBG).
Choi teaches:
a protective layer (interlayer insulating film 41) disposed on the source line (20A) and the sacrificial pattern (20B);
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Ishihara in view of Choi as explained above.
With respect to claim 23, Choi further teaches:
wherein the source line (20A) is directly connected to a portion of the sidewall of the channel layer (383) of the channel plug.
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Ishihara in view of Choi as explained above.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Ishihara (US 2011/0309432 A1) and Choi (US 2021/0134832 A1) as applied to claim 19 above and further in view of Zhang (US 2016/0163389 A1).
With respect to claim 24, Ishihara/Choi teaches all limitations of claim 19 upon which claim 24 depends. Ishihara/Choi fails to teach:
a wiring passing through the gate stack and connected to the source line.
Zhang teaches:
a wiring passing (via structure 76) through the gate stack (32 and 46) and connected to the source line (26).
Ishihara/Choi discloses the claimed invention except for the wiring layer running through the gate stack connected to the source line. Zhang teaches that it is known to have a wiring layer connected to a source line passing through a gate stack. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Ishihara/Choi as taught by Zhang in order to provide a backside contact to the source line. See MPEP 2144.
Response to Arguments
Applicant’s arguments, see pages 20-21, filed February 25, 2026 with respect to the rejections of claims 6 and 20-24 under 112(b) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made for some of the claims in view of amendments.
Applicant's arguments filed February 25, 2026 with respect to prior art rejections have been fully considered but they are not persuasive.
With respect to claim 1, Applicant argues that the newly amended limitations are not anticipated by the prior art of record because the backgate dielectric 66 and bottommost insulator layer 132 are allegedly not in contact with each other. The Examiner notes that “in contact” is a broad term that can refer to direct or indirect, physical, thermal or electrical contact and therefore the elements are at least in thermal, electrical, and indirect physical contact with each other.
With respect to claim 19, Applicant argues that the conductive pillar PGB does not pass through the connection portion conductive layer SCC and therefore the conductive pillar allegedly cannot be defined as recited in amended claim 19. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the conductive pillar passing through the connection portion conductive layer) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The limitation “a second portion disposed over the source line” does not require that that the backgate fully passes through the source line. Therefore, the arguments are found unpersuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897