DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 17 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation "substrate insulation layer" in line 5. There is insufficient antecedent basis for this limitation in the claim.
Regarding claim 17, applicant describes the non-functional surface of the at least one die to be mounted on the heat dissipation plate, but in claim 17 describes a functional surface on the heat dissipation plate instead of the fine circuit layer. It is unclear which surfaces of each element is connected to the functional and non-functional sides of the die.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-12 and 18-20 are rejected under 35 U.S.C. 102(1)(a) as being anticipated by Lin et al. (US Publication No. 2017/0207204).
Regarding claim 1, Lin discloses a multi-chip interconnection package structure with a heat dissipation plate, comprising:
a fine circuit layer (118)
at least one die (102) mounted on the fine circuit layer (118)
a heat dissipation plate (164), provided on the fine circuit layer (118) and mounted on a side of the at least one die (102) away from the fine circuit layer (118)
a plastic package body (116), wrapping the at least one die and the heat dissipation plate (164)
a package circuit layer (158), provided on the plastic package body (116) or a side of the fine circuit layer (118) away from the at least one die (102), wherein a non-functional surface (lower surface) of the at least one die is mounted on a mounting portion (164) of the heat dissipation plate, and an insulating material (109) is used to make a functional surface (upper surface) of the at least one die (102) mounted on the fine circuit layer (118)
the insulating material is used to make a support portion (204/206 inside) of the heat dissipation plate (164) directly adhered onto the fine circuit layer (118)
the at least one die (102) is electrically connected to the fine circuit layer (118), and the package circuit layer (158) is electrically connected (204/206 outer) to the fine circuit layer (118)
at least one first conductive hole (118 lower layer) is formed in the fine circuit layer (118), and direct electrical interconnection between the fine circuit layer (118) and at least one pin pad (108) of the at least one die is realized through a conductive material (120b) in the at least one first conductive hole (118 lower layer)
Regarding claim 2, Lin discloses the heat dissipation plate (164) comprises a support portion (204/206 inside) and the mounting portion (164) that are integrally provided, the mounting portion has at least one sink groove (170) configured to accommodate the at least one die (102), the mounting portion (164) is mounted on a side surface of the at least one die (102) away from the fine circuit layer (118), the support portion (204/206 inside) is mounted on the fine circuit layer (118), and at least one through hole (between 204 and 102) configured for allowing a plastic package material (116) to pass therethrough is provided between the mounting portion (164) and the support portion (204/206 inside).
Regarding claim 3, Lin discloses a thermally conductive adhesive layer is provided between the mounting portion (164) and the at least one die (102), and the at least one die is bonded to the mounting portion through the thermally conductive adhesive layer (paragraph 26).
Regarding claim 4, Lin discloses the functional surface of the at least one die (102) is provided with the at least one pin pad (108), the at least one pin pad is mounted on the fine circuit layer (118 lower layer), the fine circuit layer is formed with the at least one first conductive hole (120b) running through to the at least one pin pad (108) or the heat dissipation plate, the at least one first conductive hole is filled with a conductive material (120b) to realize interconnection between the at least one die (102) and the fine circuit layer (118), the multi-chip interconnection package structure with a heat dissipation plate (164) further comprises a substrate circuit layer (118 upper layer), the substrate circuit layer covers the at least one first conductive hole (118 lower), and is electrically connected to the at least one pin pad or the heat dissipation plate through the at least one first conductive hole (Figure 7).
Regarding claim 5, Lin discloses the substrate circuit layer (118 upper) comprises a substrate wiring layer (120) and a substrate insulation layer (122 upper), the substrate wiring layer is provided on a side surface of the fine circuit layer (118) away from the at least one die (102), and is electrically connected to both the fine circuit layer (118) and/or the at least one first conductive hole (118 lower), and the substrate insulation layer is provided on the side surface of the fine circuit layer away from the at least one die, and covers the substrate wiring layer (Figure 3).
Regarding claim 6, Lin discloses the fine circuit layer (118) comprises a fine wiring layer (120 lower) and a fine insulation layer (122 lower), the fine insulation layer wraps the fine wiring layer, the at least one die (102) is mounted on a side surface of the fine insulation layer, and the fine wiring layer (120 lower) is exposed on a side surface of the fine insulation layer (122 lower) away from the at least one die (102), and the substrate circuit layer (118 upper) is provided on a side of the fine insulation layer away from the at least one die, and is electrically connected to the fine wiring layer (Figure 3).
Regarding claim 7, Lin discloses the fine circuit layer (118) further comprises a base material insulation layer (118 upper), the base material insulation layer is provided on the side surface of the fine insulation layer away from the at least one die (102) and covers the fine wiring layer (120 lower), the substrate circuit layer (118 upper)is provided on a side surface of the substrate insulation layer (122 upper)away from the at least one die (102), the substrate insulation layer is formed with at least one third conductive hole (120B) running through to the fine wiring layer (120 lower)and/or the substrate circuit layer (118 upper), and the substrate circuit layer (118 upper) is electrically connected to the fine wiring layer (120 lower) through the at least one third conductive hole (120B).
Regarding claim 8, Lin discloses the fine wiring layer (120 lower) has at least one external bonding pad (120A), the plastic package body (116) is formed with at least one second conductive hole (120B) running through to the external bonding pad, the at least one second conductive hole (120B) is filled with a conductive material, and the package circuit layer (158) covers the at least one second conductive hole, and is electrically connected to the at least one external bonding pad (120A) through the at least one second conductive hole (120B) (Figure 3).
Regarding claim 9, Lin discloses the package circuit layer (158) comprises a package wiring layer (162) and a package insulation layer (158), the package wiring layer (162) is provided on a surface of the plastic package body (116), the package wiring layer (162) covers the at least one second conductive hole (120B), and is electrically connected (204/206) to the at least one second conductive hole (120B), and/or in electrical contact with the heat dissipation plate, and the package insulation layer (158) is provided on a surface of the plastic package body (116) and wraps the package wiring layer (162) (Figure 4).
Regarding claim 10, Lin discloses the multi-chip interconnection package structure with a heat dissipation plate further comprises at least one stacking chip (152), a non-functional surface of the at least one stacking chip is mounted on a side of the heat dissipation plate (164) away from the at least one die (102), and is wrapped in the plastic package body (116), and the at least one stacking chip is electrically connected to the at least one package circuit layer (158) or the heat dissipation plate (164) through the at least one second conductive hole (120B) (Figure 10).
Regarding claim 11, Lin discloses at least one solder ball (160) is further provided on the substrate circuit layer or the package circuit layer (158).
Regarding claim 12, Lin discloses the package circuit layer (158) is provided on the side of the fine circuit layer (118) away from the at least one die (102), the multi-chip interconnection package structure (158) with a heat dissipation plate (164) further comprises at least one stacking chip (152), the at least one stacking chip is mounted on the side of the fine circuit layer (118) away from the at least one die (102), and is wrapped in the package circuit layer (158), and the at least one stacking chip (152) is electrically connected to the fine circuit layer (118).
Regarding claim 18, Lin discloses the package circuit layer (158) is provided on the side of the fine circuit layer (118) away from the at least one die (102), the multi-chip interconnection package structure (158) with a heat dissipation plate (164) further comprises at least one stacking chip (152), the at least one stacking chip is mounted on the side of the fine circuit layer (118) away from the at least one die (102), and is wrapped in the package circuit layer (158), and the at least one stacking chip (152) is electrically connected to the fine circuit layer (118).
Regarding claim 19, Lin discloses the package circuit layer (158) is provided on the side of the fine circuit layer (118) away from the at least one die (102), the multi-chip interconnection package structure (158) with a heat dissipation plate (164) further comprises at least one stacking chip (152), the at least one stacking chip is mounted on the side of the fine circuit layer (118) away from the at least one die (102), and is wrapped in the package circuit layer (158), and the at least one stacking chip (152) is electrically connected to the fine circuit layer (118).
Regarding claim 20, Lin discloses the package circuit layer (158) is provided on the side of the fine circuit layer (118) away from the at least one die (102), the multi-chip interconnection package structure (158) with a heat dissipation plate (164) further comprises at least one stacking chip (152), the at least one stacking chip is mounted on the side of the fine circuit layer (118) away from the at least one die (102), and is wrapped in the package circuit layer (158), and the at least one stacking chip (152) is electrically connected to the fine circuit layer (118).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US Publication No. 2017/0207204) in view of Chang et al. (US Publication No. 2022/0028842).
Regarding claim 13, Lin discloses a preparation method of a multi-chip interconnection package structure with a heat dissipation plate, for preparing the multi-chip interconnection package structure with a heat dissipation plate according to claim 1, wherein the preparation method comprises steps of:
preparing a fine circuit layer (118) and a heat dissipation plate (164)
mounting a non-functional surface (lower) of at least one die (102) on the heat dissipation plate (164)
mounting a functional surface (upper) of the at least one die (102) and the heat dissipation plate together on the fine circuit layer (118)
forming a plastic package body (116) wrapping the at least one die and the heat dissipation plate (164) on the fine circuit layer (118)
preparing at least one first interconnection hole (118 lower layer) on an insulating material (122) of the fine circuit layer (118), and filling a conductive material (120)
forming a substrate circuit layer (and/or packaging at least one pin pad (108) on a side of the fine circuit layer (118) and the first conductive hole (120b) away from the die
forming, on the plastic package body, at least one second conductive hole (118 lower layer) and at least one third conductive hole (118 lower layer) running through the plastic package body (116), and filling a conductive material
forming a package circuit layer (160) and/or packaging (160) the at least one pin pad on the plastic package body, the at least one second conductive hole and the at least one third conductive hole, wherein the conductive holes are electrically connected to the package circuit layer (160) (Figure 4)
preparing and packaging an external bump (160)
wherein the substrate circuit layer (118 upper) is electrically connected to the fine circuit layer (118), the at least one die (102) is electrically connected to the fine circuit layer and/or the substrate circuit layer, and the package circuit layer is electrically connected to the fine circuit layer (Figure 10)
Lin does not disclose cutting the substrate circuit layer, the fine circuit layer, the plastic package body, and the package circuit layer along a cutting path. However, Chang discloses cutting a substrate circuit layer (204), a fine circuit layer (208), a plastic body (120), and a package circuit layer (122) (Figures 9-12). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the method of Lin to include a step of cutting all these layers together to singulate into individual packages, as taught by Chang, since it can provide multiple packages for improved heat dissipation for an entire singulated package, thereby reducing manufacturing steps (paragraphs 70-71).
Regarding claim 14, Lin discloses before the step of mounting the at least one die (102) on the fine circuit layer (118), the preparation method further comprises: coating a strippable adhesive material (112) on a temporary carrier plate (110), and preparing the fine circuit layer (118) on the strippable adhesive material; or preparing the fine circuit layer on a substrate material (paragraph 23).
Regarding claim 15, Chang discloses before the step of forming a substrate circuit layer on a side of the fine circuit layer away from the at least one die, the preparation method further comprises: stripping off the temporary carrier plate (102) and the strippable adhesive material (104); or thinning the substrate material (Figure 10). As explained above, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified Lin in view of Chang.
Regarding claim 16, Lin discloses wherein before the step of forming on the fine circuit layer a plastic package body wrapping the at least one die and the heat dissipation plate, the preparation method further comprises: mounting at least one stacking chip (152) on a side surface of the heat dissipation plate (164) away from the at least one die (102) (paragraph 24; Figure 4).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US Publication No. 2017/0207204) in view of Kang et al. (US Publication No. 2020/0373244).
Regarding claim 17, Lin discloses a preparation method of a multi-chip interconnection package structure with a heat dissipation plate, for preparing the multi-chip interconnection package structure with a heat dissipation plate according to claim 1, wherein the preparation method comprises:
preparing a fine circuit layer (118) and a heat dissipation plate (164)
mounting a functional surface (upper) of at least one die (102) on the heat dissipation plate (164)
mounting the heat dissipation plate (164) and a functional surface (lower) of the at least one die (102) together on a substrate (110)
forming, on the substrate, a plastic package body (116 upper) wrapping the at least one die (102) and the heat dissipation plate (164)
removing the substrate (110) and forming the fine circuit layer (118) on a side of the at least one die (102) (Figure 3)
mounting at least one stacking chip (152) on a side of the fine circuit layer (118) away from the at least one die (102)
forming, at a layer of the fine circuit layer (118) and the at least one stacking chip (152), a second plastic package body (116 lower) wrapping the at least one stacking chip (152) and the fine circuit layer (118)
preparing at least one conductive hole (120B) running through the second plastic package body (116 lower), to expose a fine interconnection circuit (118) and/or at least one pin pad (108) of the at least one stacking chip (152), the at least one conductive hole (120B) being filled with a conductive material
forming a package circuit layer (158) on a side of the fine circuit layer away from the at least one die, and mounting at least one ball (160)
wherein the package circuit layer (158) is electrically connected to the fine circuit layer (118), the at least one die (102) is electrically connected to the fine circuit layer (118), the at least one stacking chip is electrically connected to the fine circuit layer, and/or the at least one stacking chip (152) is electrically connected to the package circuit layer (158)
Lin does not specifically disclose mounting the functional surface of the die on the heat dissipation plate. However, Kang discloses functional surfaces (121P) of a die (121) connected to a heat dissipation RDL (140) and connected to a heat dissipation structure (180) (paragraphs 88-89; Figure 9). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the functional surface of Lin to connect to a heat dissipation layer to improve heat dissipation of the package while shielding the wiring from interference (paragraph 89).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Sankman et al. (US Publication No. 2020/0357721) discloses back-to-back dies separated by a heat dissipation layer (Figure 4A). Kim et al. (US Publication No. 2022/0359358) discloses dies separated by a heat dissipation layer (150) with through vias surrounding the dies in a plastic body (Figure 2).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm.
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/N.R.P/ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
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