Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
In response to applicant’s arguments, as previously stated and shown below, Spitzlsperger shows a silicon layer 100 having a frontside and an electrically insulated backside; a first trench 149 extending through the silicon layer from the frontside to the electrically insulated backside and laterally isolating a first region of the silicon layer; an electrically conductive material 134/138 in the first trench; a dielectric material 133 separating the electrically conductive material from silicon material of the silicon layer.
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Spitzlsperger in paragraph [0046] states “turning now to FIG. 2H, a dielectric insulating liner 133 is deposited on the sidewalls of the TSVs followed by a conductive filling 134 establishing metal stud 134. Sub atmospheric CVD with ozone/TEOS may be used for conformal deposition of a dielectric liner in the TSVs. There are other possibilities which are known to those skilled in the art. The dielectric liner prevents an electrical connection of the via to the silicon. The dielectric liner 133 must be opened at the bottom of the TSV before filling with conductive material. The conductive filling 134 may be a metal layer such as aluminum, tungsten or copper.
Furthermore, the terms such as “first region” are broad terms and can be considered to be any part of the layer.
Therefore, the rejections remain valid for the reasons set forth below. As illustrated above and explained in more details, the prior art has been shown to read on the current claim language.
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Spitzlsperger et al. (Pub. No. US 2016/0379936 A1, herein Spitzlsperger) in view of Siemieniec et al. (Pub. No. US 2016/0293751 A1, Siemieniec).
Regarding claim 1, Spitzlsperger discloses a semiconductor device, comprising: a silicon layer 100 having a frontside (the interface of layers 100 and 139) and an electrically insulated backside (the interface of layer 100 and dielectric layer 111, Fig. 2J and paragraph [0025]); a first trench 148/149 extending through the silicon layer from the frontside to the electrically insulated backside and laterally isolating a first region of the silicon layer (Figs. 2G-2J, abstract and paragraph [0045]); an electrically conductive material 134 in the first trench; a dielectric material 133 separating the electrically conductive material from silicon material of the silicon layer (Figs. 2J and paragraph [0046]).
Spitzlsperger does not specifically show a plurality of silicon plugs laterally surrounded by the dielectric material and dividing the electrically conductive material into a plurality of separate segments in the first trench.
However, in the same field of endeavor, Siemieniec teaches a plurality of silicon plugs laterally surrounded by the dielectric material 169 and dividing the electrically conductive material into a plurality of separate segments in the first trench (Siemieniec: Figs. 4A-4H, 10A-11B and paragraph [0053]; “The field electrode 165 includes or consists of a heavily doped silicon layer and/or a metal-containing layer. The field dielectric 169 separates the field electrode 165 from the surrounding semiconductor material of the semiconductor portion 100”) thereby preventing leakage paths, unintended current flow and performance degradation between neighboring device regions.
Therefore, given the teachings of Siemieniec, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Spitzlsperger in view of Siemieniec by employing the plurality of silicon plugs.
Regarding claim 2, Spitzlsperger in view of Siemieniec teaches the semiconductor device of claim 1, wherein in a lateral direction, an average thickness of the dielectric material around each silicon plug is greater than an average thickness of the dielectric material between the silicon material and the electrically conductive material (Spitzlsperger: Figs. 2J and paragraph [0046], and Siemieniec: Figs. 4A-4H, 10A-11B and paragraph [0053]; The dielectric material surrounds the conductive material, therefore the thickness of the dielectric material around each silicon plug is at least twice as much as the thickness of the dielectric material between the silicon material and the electrically conductive material.).
Regarding claim 3, Spitzlsperger in view of Siemieniec teaches the semiconductor device of claim 1, wherein the first region of the silicon layer includes a transistor device 200/201 having a source region laterally separated from a drain region by a drift region (Spitzlsperger: Figs. 2J and paragraphs [0004], [0064], [0072]), and wherein the silicon plugs divide the electrically conductive material into the separate segments between the source region and the drain region such that the separate segments are at different potentials when the transistor device is off (Spitzlsperger: Figs. 2J and paragraph [0046], and Siemieniec: Figs. 4A-4H, 10A-11B and paragraphs [0053]).
Allowable Subject Matter
Claims 4 and 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 4, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, a second trench extending through the silicon layer from the frontside to the electrically insulated backside and laterally isolating a second region of the silicon layer, the second trench including the electrically conductive material, wherein the dielectric material separates the electrically conductive material in the second trench from the silicon material of the silicon layer, wherein the first and second trenches intersect or merge with one another, wherein one of the silicon plugs interrupts the electrically conductive material where the first and second trenches intersect or merge with one another.
With respect to claim 6, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, wherein the plurality of silicon plugs interrupts the electrically conductive material at each location where the first trench merges with or intersects another trench that extends through the silicon layer from the frontside to the electrically insulated backside.
With respect to claim 7, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, a plurality of additional trenches extending through the silicon layer from the frontside to the electrically insulated backside and merging with the first trench, wherein the plurality of additional trenches laterally isolate a first additional region of the silicon layer from a second additional region of the silicon layer, wherein the first additional region supports a higher voltage domain than the second additional region, wherein a level shifter device is formed in the first region and configured to provide voltage level shifting between the first and second additional regions, wherein the plurality of silicon plugs interrupts the electrically conductive material where the plurality of additional trenches merge with the first trench.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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April 8, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813
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