DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species 1 (Fig. 1-5) in the reply filed on 5/15/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Applicant has indicated claims 1-12 and 15-20 as reading on the elected species. However, Examiner finds that claims 8, 12, and 19 do not correspond to the elected species (Fig. 1-5).
Claim 8 does not correspond to the elected Species 1 (Fig. 1-5) because the second insulating layer (110, Fig. 5) is not in contact with a lower surface of the source/drain region (SD, Fig. 5) due to intervening active layer F (Fig. 5) as required for claim 8. Rather, claim 8 appears to correspond to Species 3 because this species comprises a second interlayer insulating layer (310, Fig. 55) in contact with a lower surface of the source/drain region (SD, Fig. 55) ([0117]).
Claim 12 does not correspond to the elected Species 1 (Fig. 1-5) because a portion of the second interlayer insulating layer (110, Fig. 5) is not protruded in a vertical direction as required by claim 12. Rather, claim 12 appears to correspond to Species 4 because this species comprises a second interlayer insulating layer (410, Fig. 58) which is protruded in a vertical direction below the active pattern (F4, Fig. 58) ([0122]).
Claim 19 does not correspond to the elected Species 1 (Fig. 1-5) because the power rail via (140) does not “not overlap” with the gate electrode in the second horizontal direction as required by claim 19. Said another way, the power rail via in the elected species overlaps the gate electrode in the second horizontal direction, which conflicts with claim 19. Rather, claim 19 appears to correspond to either Species 6 (Fig. 63, [0136]) or Species 7 (Fig. 67, [0144]) as these species contain the characteristics that the power rail via (640_2, Fig 63 or 740, Fig. 67) does not overlap the gate electrode in the second horizontal direction.
Therefore, claims 1-7, 9-11, 15-18, and 20 correspond to the elected Species 1 (Fig. 1-5).
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 2/24/23 and 3/3/26. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements have been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7, 9-11, 15, 17-18, and 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie et al. (U.S. 2024/0162152 A1).
Regarding claim 1, Xie discloses a semiconductor device comprising:
A base substrate (120, Fig. 1B) ([0054]);
A first interlayer insulating layer (118, Fig. 1B) disposed on the base substrate ([0054]);
A power rail (124, Fig. 1B) disposed inside the first interlayer insulating layer ([0056]);
An active pattern (fin below 114, Fig. 1B) extended in a first horizontal direction and disposed on the first interlayer insulating layer ([0054]);
A gate electrode (112, Fig. 1B) extended in a second horizontal direction different from the first horizontal direction and disposed on the active pattern ([0054]);
A gate cut (126, Fig. 1B) extended in the first horizontal direction and disposed on the power rail, wherein the gate cut separates the gate electrode (112, Fig. 1B) ([0056]); and
A power rail via (122, 128, Fig. 1B) disposed inside the gate cut, wherein the power rail via is overlapped by the power rail (124, Fig. 1B) ([0056]).
Regarding claim 2, Xie discloses a width in the first horizontal direction of the gate cut (126, Fig. 1A-1B) is greater than a width in the first horizontal direction of the power rail via (122, 128, Fig. 1A-1B).
Regarding claim 3, Xie discloses a width in the second horizontal direction of the gate cut (126, Fig. 1A-1B) is greater than a width in the second horizontal direction of the power rail via (122, 128, Fig. 1A-1B).
Regarding claim 4, Xie discloses the gate cut (126, Fig. 1B) is in contact with the power rail (124, Fig. 1B).
Regarding claim 5, Xie discloses a sidewall of the power rail via (122, 128, Fig. 1B) is at least partially surrounded by the gate cut (126, Fig. 1B).
Regarding claim 6, Xie discloses a source/drain region (132, 130, Fig. 1B) disposed on at least one side of the gate electrode (112, Fig. 1B) ([0057]); and a source/drain contact (134, Fig. 1B) connected to the source/drain region, wherein the source/drain contact (134, Fig. 1B) is in contact with a sidewall of the power rail via (122, 128, Fig. 1B).
Regarding claim 7, Xie discloses an upper surface of the source/drain (134, Fig. 1B) contact is coplanar with an upper surface of the power rail via (122, 128, Fig. 1B).
Regarding claim 9, Xie discloses at least a portion of the power rail via (122, 128, Fig. 1B) overlaps the gate electrode (112, Fig. 1B) in the second horizontal direction.
Regarding claim 10, Xie discloses the power rail via (122, 128, Fig. 1B) comprises: a power rail via barrier layer (128, Fig. 1B) disposed along a sidewall of a power rail via trench formed inside the gate cut, wherein the power rail via barrier layer is disposed on the gate cut (126, Fig. 1B) ([0056]); and a power rail via filling layer (122, Fig. 1B) filling the power rail via trench and disposed on the power rail via barrier layer (128, Fig. 1B) ([0056]), wherein the power rail via filling layer (122, Fig. 1B) is disposed on the power rail (124, Fig. 1B).
Regarding claim 11, Xie discloses a plurality of nanosheets (114, Fig. 1B) stacked on each other and spaced apart from each other in a vertical direction on the active pattern (fin below 114, Fig. 1B) and surrounded by the gate electrode (112, Fig. 1B) ([0054]).
Regarding claim 15, Xie discloses a semiconductor device comprising:
A base substrate (120, Fig. 1B) ([0054]);
A power rail (124, Fig. 1B) extended in a first horizontal direction and disposed on the base substrate ([0056]);
A gate electrode (112, Fig. 1B) extended in a second horizontal direction different from the first horizontal direction and disposed on the power rail (124, Fig. 1B) ([0054]);
A gate cut (126, Fig. 1B) extended in the first horizontal direction and disposed on the power rail, wherein the gate cut separates the gate electrode (112, Fig. 1B) ([0056]), and is in contact with the power rail (124, Fig. 1B);
A power rail via (122, 128, Fig. 1B) disposed inside the gate cut, and in contact with the power rail ([0056]);
A source/drain region (132, 130, Fig. 1B) disposed on at least one side of the gate electrode ([0057]); and
A source/drain contact (134, Fig. 1B) disposed on the source/drain region, wherein the source/drain contact is in contact with a sidewall of the power rail via (122, 128, Fig. 1B), wherein a width in the first horizontal direction of the gate cut (126, Fig. 1B) is greater than a width in the first horizontal direction of the power rail via, and a width in the second horizontal direction of the gate cut is greater than a width in the second horizontal direction of the power rail via (122, 128, Fig. 1A-1B) ([0057]).
Regarding claim 17, Xie discloses an upper surface of the source/drain contact (134, Fig. 1B) is coplanar with an upper surface of the power rail via (122, 128, Fig. 1B).
Regarding claim 18, Xie discloses the power rail via (122, 128, Fig. 1B) comprises: a power rail via barrier layer (128, Fig. 1B) disposed along a sidewall of a power rail via trench formed inside the gate cut, and is in contact with the gate cut; and a power rail via filling layer (122, Fig. 1B) filling the power rail via trench and disposed on the power rail via barrier layer, wherein the power rail via filling layer (122, Fig. 1B) contacts the power rail (124, Fig. 1B).
Regarding claim 20, Xie discloses a semiconductor device comprising:
A base substrate (120, Fig. 1B) ([0054]);
A first interlayer insulating layer (118, Fig. 1B) disposed on the base substrate ([0054]);
A power rail (124, Fig. 1B) extended in a first horizontal direction inside the first interlayer insulating layer (118, Fig. 1B);
A second interlayer insulating layer (116, Fig. 1B) disposed on the first interlayer insulating layer;
An active pattern (fin under 114, Fig. 1B) extended in the first horizontal direction and disposed on the second interlayer insulating layer;
A plurality of nanosheets (114, Fig. 1B) stacked on each other and spaced apart from each other in a vertical direction on the active pattern;
A field insulating layer (134, Fig. 1B) at least partially surrounding a sidewall of the active pattern on the second interlayer insulating layer;
A gate electrode (112, Fig. 1B) extended in a second horizontal direction different from the first horizontal direction and disposed on the active pattern, wherein the gate electrode at least partially surrounds the plurality of nanosheets (114, Fig. 1B);
A source/drain region (132, 130, Fig. 1B) disposed on at least one side of the gate electrode;
A gate cut (126, Fig. 1B) extended in the first horizontal direction and disposed on the power rail (124, Fig. 1B), wherein the gate cut passes through the second interlayer insulating layer (116, Fig. 1B) and the field insulating layer (134, Fig. 1B) in the vertical direction, wherein the gate cut separates the gate electrode (112, Fig. 1B), and is in contact with the power rail;
A power rail via (122, 128, Fig. 1B) disposed inside the gate cut, and in contact with the power rail (124, Fig. 1B); and
A source/drain contact (134, Fig. 1B) connected to the source/drain region, and in contact with a sidewall of the power rail via (122, 128, Fig. 1B), wherein an upper surface of the source/drain contact is coplanar with an upper surface of the power rail via (122, 128, Fig. 1B) ([0057]), and
Wherein the power rail via (122, 128, Fig. 1B) comprises: a power rail via barrier layer (128, Fig. 1B) disposed along a sidewall of a power rail via trench formed inside the gate cut, and in contact with the gate cut; and a power rail via filling layer (122, Fig. 1B) filling the power rail via trench and disposed on the power rail via barrier layer, wherein the power rail via filling layer (122, Fig. 1B) is in contact with the power rail (124, Fig. 1B).
Allowable Subject Matter
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to REEMA PATEL whose telephone number is (571)270-1436. The examiner can normally be reached M-F, 8am-5pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/REEMA PATEL/Primary Examiner, Art Unit 2812 7/15/2026
Prosecution Insights