CTNF 18/114,120 CTNF 90678 2814 DETAILED ACTION This action is responsive to the application No. 18/114,120 filed on February 24, 2023. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Acknowledgment This is responsive to the application filed on 02/24/2023. Accordingly, pending in this Office action are claims 1-20. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-3, 5, 7-16, 19, and 20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Yamamoto (US 2002/0158339) . Regarding Claim 1 , Yamamoto (see, e.g., Fig. 6F and annotated Fig. 6F), teaches an apparatus comprising: a first layer 12 comprising a first dielectric material, and first and second regions R 1 /R 2 on a first side 1S of the first layer 12 , the first regions R 1 comprising a first surface S 1 in a first plane P 1 , and each of the second regions R 2 comprising a second surface S 2 in a second plane P 2 spaced away from the first plane P 1 by a first distance d 1 , wherein sidewalls SW 1 extend between the first surface S 1 and the second surfaces S 2 (see, e.g., par. 0116); a plurality of conductive features 18a/18b/18c , each conductive feature 18a/18b/18c comprising a bottom surface 18bs on one of the second surfaces S 2 (see, e.g., par. 0134); and a barrier film 26 comprising a second dielectric material and contacting the sidewalls SW 1 (see, e.g., par. 0147). Regarding Claim 2 , Yamamoto teaches all aspects of claim 1. Yamamoto (see, e.g., Fig. 6F and annotated Fig. 6F), teaches that: each of the conductive features 18a/18b/18c comprises a top surface 18ts opposite the bottom surface 18bs , and a conductive feature sidewall SW 2 extending between the bottom surface 18bs and the top surface 18ts ; and the barrier film 26 contacts the conductive feature sidewall SW 2 and the top surface 18ts of the conductive features 18a/18b/18c . Regarding Claim 3 , Yamamoto teaches all aspects of claim 1. Yamamoto (see, e.g., Fig. 6F and annotated Fig. 6F), teaches that the second dielectric material comprises silicon nitride, silicon oxynitride, silicon oxide, or a carbon doped oxide (see, e.g., par. 0147). Regarding Claim 5 , Yamamoto teaches all aspects of claim 1. Yamamoto (see, e.g., Fig. 6F and annotated Fig. 6F), teaches that the first dielectric material comprises a filler-less material (see, e.g., par. 0116). Regarding Claim 7 , Yamamoto teaches all aspects of claim 1. Yamamoto (see, e.g., Figs. 5B, 6F and annotated Fig. 6F), teaches that the first distance d 1 is between 25 nanometers and 10 microns (see, e.g., par. 0131). Regarding Claim 8 , Yamamoto teaches all aspects of claim 1. Yamamoto (see, e.g., Figs. 5B, 6F and annotated Fig. 6F), teaches that the barrier film 26 is on the first surface S 1 and has a thickness t 1 on the first surface S 1 equal to the first distance d 1 (see, e.g., pars. 0131, 0157). Regarding Claim 9 , Yamamoto teaches all aspects of claim 1. Yamamoto (see, e.g., Figs. 5B, 6F and annotated Fig. 6F), teaches that the barrier film 26 is on the first surface S 1 and has a thickness t 1 on the first surface S 1 less than the first distance d 1 (see, e.g., pars. 0131, 0157). Regarding Claim 10 , Yamamoto teaches all aspects of claim 1. Yamamoto (see, e.g., Fig. 6F and annotated Fig. 6F), teaches a second layer SL over the first layer 12 , the second layer SL comprising: the plurality of conductive features 18a/18b/18c (see, e.g., par. 0119); and a third dielectric material 28 (see, e.g., par. 0148). Regarding Claim 11 , Yamamoto teaches all aspects of claim 10. Yamamoto (see, e.g., Fig. 6F and annotated Fig. 6F), teaches, further comprising: a third layer 30 over the second layer SL , wherein the third layer 30 comprises: third and fourth regions R 3 /R 4 on a third side 3S , the third layer 30 comprising the first dielectric material, wherein the third regions R 3 comprise a third surface S 3 in a third plane P 3 , and each of the fourth regions R 4 comprise a fourth surface S 4 in a fourth plane P 4 spaced away from the third plane P 3 by a second distance d 2 , and second sidewalls SW 3 extending between the third and fourth surfaces S 3 /S 4 (see, e.g., par. 0154); a plurality of second conductive features 22a , each second conductive feature 22a comprising a bottom surface 22bs on one of the fourth surfaces S 4 ; and a second barrier film 34 comprising the second dielectric material, the second barrier film 34 contacting the second sidewalls SW 3 (see, e.g., par. 0160). Regarding Claim 12 , Yamamoto teaches all aspects of claim 11. Yamamoto (see, e.g., Fig. 6F and annotated Fig. 6F), teaches that the apparatus comprises processor circuitry (see, e.g., pars. 0292-0298, 0319). Regarding Claim 13 , Yamamoto (see, e.g., Figs. 6F, 27-29, and annotated Fig. 6F), teaches a system comprising: a microprocessor comprising circuitry on an integrated circuit (IC) die, wherein the IC die comprises (see, e.g., pars. 0292-0298, 0319): a first layer 12 comprising a first dielectric material and a first side TS , the first side 1S comprising first and second regions R 1 /R 2 , wherein the first region R 1 comprises a first surface S 1 in a first plane P 1 , each of the second regions R 2 comprise a second surface S 2 in a second plane P 2 spaced away from the first plane P 1 by a first distance d 1 , the first side TS further comprising sidewalls SW 1 extending between the first S 1 and second surfaces S 2 (see, e.g., par. 0116); a plurality of conductive features 18a/18b/18c , each conductive feature 18a/18b/18c comprising a bottom surface 18bs in contact with one of the second regions R 2 (see, e.g., par. 0134); and a barrier film 26 on the first surface S 1 between first and second conductive features 22a and comprising a second dielectric material (see, e.g., par. 0147). Regarding Claim 14 , Yamamoto teaches all aspects of claim 13. Yamamoto (see, e.g., Figs. 5B, 6F and annotated Fig. 6F), teaches that the barrier film 26 has a thickness t 1 equal to the first distance d 1 (see, e.g., pars. 0131, 0157). Regarding Claim 15 , Yamamoto teaches all aspects of claim 13. Yamamoto (see, e.g., Figs. 5B, 6F and annotated Fig. 6F), teaches that: each of the conductive features 18a/18b/18c comprises a top surface 18ts opposite the bottom surface 18bs , and a conductive feature sidewall SW 2 extending between the bottom surface 18bs and the top surface 18ts ; and the barrier film 26 contacts the conductive feature sidewalls SW 2 and the top surface 18ts of the conductive features 18a/18b/18c . Regarding Claim 16 , Yamamoto teaches all aspects of claim 13. Yamamoto (see, e.g., Figs. 6F and annotated Fig. 6F), teaches that the second dielectric material comprises silicon nitride (see, e.g., pars. 0157, 0259). Regarding Claim 19 , Yamamoto (see, e.g., Figs. 5A-6F, and annotated Fig. 6F), teaches a method comprising: forming conductive features 18a/18b/18c on a first side 1S of a first layer 12 of an IC die, the first layer 12 comprising a first dielectric material, and first and second regions R 1 /R 2 on the first side 1S , wherein each of the conductive features 18a/18b/18c comprises a bottom surface 18bs on a respective one of the second regions R 2 (see, e.g., pars. 0116, 0134); etching the first side TS to create a first surface S 1 in a first plane P 1 in the first regions R 1 and second surfaces S 2 in the second regions R 2 , wherein each of the second surfaces S 2 are in a second plane P 2 spaced away from the first plane P 1 by a first distance d 1 , and sidewalls SW 1 extend between the first surface S 1 and the second surfaces S 2 (see, e.g., par. 0116); and forming a barrier film 26 contacting the sidewalls SW 1 , the barrier film 26 comprising a second dielectric material (see, e.g., par. 0147). Regarding Claim 20 , Yamamoto teaches all aspects of claim 1. Yamamoto (see, e.g., Figs. 5A-6F and annotated Fig. 6F), teaches that the second dielectric material comprises silicon nitride, silicon oxynitride, silicon oxide, or a carbon doped oxide (see, e.g., par. 0147) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 4 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto (US 2002/0158339) in view of Paek (US 2014/0138817) . Regarding Claims 4 and 17 , Yamamoto teaches all aspects of claims 1 and 13. Yamamoto (see, e.g., Fig. 6F and annotated Fig. 6F), teaches that the first dielectric material comprises, wherein the first dielectric material comprises a silicone oxide or BPSG (borophospho silicate glass) film deposited by CVD, a silicon nitride film deposited by CVD, a SOG film (see, e.g., par. 0116). Yamamoto does not teach that the first dielectric material comprises composite polymer/filler material, an organic material, or a polyimide. Yamamoto discloses the claimed invention except for the use of silicone oxide or silicon nitride for the dielectric material instead of an organic material. Paek, on the other hand, teaches that an organic material and silicone oxide or silicon nitride are equivalent materials known in the art (see, e.g., par. 0095). Therefore, because these insulating materials were art-recognized equivalents at the time of the invention, one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, one of ordinary skill in the art would have found it obvious to substitute an organic material for silicone oxide or silicon nitride since the substitution would yield predictable results. See Supreme Court decision in KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 YSPQ2d 1385 (2007) . 07-21-aia AIA Claim s 6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto (US 2002/0158339) . Regarding Claims 6 and 18 , Yamamoto teaches all aspects of claims 1 and 13. Yamamoto (see, e.g., Fig. 6F and annotated Fig. 6F), teaches that the first surface S 1 has a first surface roughness value, the second surface S 2 has a second surface roughness value (every surface has roughness). Yamamoto does not teach that the first surface roughness value is greater than the second surface roughness value. However, this claim limitation is merely considered a change in surface roughness of the first and/or second surfaces in Yamamoto’s device. The specific claimed roughness relationship, absent any criticality, is only considered to be an obvious modification of the roughness of the first and/or second surfaces in Yamamoto’s device, as the courts have held that changes in roughness, without any criticality, are within the level of skill in the art. According to the courts, a particular roughness, is nothing more than one among numerous roughnesses that a person having ordinary skill in the art will find obvious to provide using routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Accordingly, since Applicant’s disclosure does not teach why having the first surface roughness value being greater than the second surface roughness value, is critical to the invention (see next paragraph below), it would have been obvious to one of ordinary skill in the art at the time of filing to have the claimed roughness relationship in Yamamoto’s device. CRITICALITY The specification contains no disclosure of either the critical nature of the claimed surface roughness or any unexpected results arising therefrom. Where patentability is said to be based upon a particular chosen roughness or upon another variable recited in a claim, the applicant must show that the chosen roughness is critical. See In re Aller, PNG media_image1.png 343 373 media_image1.png Greyscale 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garcés whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:30 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. 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If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Nelson Garces/ Primary Examiner, Art Unit 2814 Application/Control Number: 18/114,120 (Non-Final Rejection) Page 2 Art Unit: 2814 Application/Control Number: 18/114,120 (Non-Final Rejection) Page 3 Art Unit: 2814 Application/Control Number: 18/114,120 (Non-Final Rejection) Page 4 Art Unit: 2814 Application/Control Number: 18/114,120 (Non-Final Rejection) Page 5 Art Unit: 2814 Application/Control Number: 18/114,120 (Non-Final Rejection) Page 6 Art Unit: 2814 Application/Control Number: 18/114,120 (Non-Final Rejection) Page 7 Art Unit: 2814 Application/Control Number: 18/114,120 (Non-Final Rejection) Page 8 Art Unit: 2814 Application/Control Number: 18/114,120 (Non-Final Rejection) Page 9 Art Unit: 2814 Application/Control Number: 18/114,120 (Non-Final Rejection) Page 10 Art Unit: 2814