CTNF 18/114,628 CTNF 82564 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION Continued Examination under 37 CFR 1.114 07-42-04 AIA 1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/16/2026 has been entered. 2. This action is responsive to the communication filed on 4/16/2026. Claims 1-2, 7-9, 14-16, 21 and 22 have been amended. Claims 6, 13 and 20 have been cancelled. Claim 23 has been added. Claims 1-5, 7-12, 14-19 and 21-23 are pending. Claim Rejections - 35 USC § 101 3. Claims 1-5, 7-12 and 14-23 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The analysis below of the claims’ subject matter eligibility follows the guidance set forth in MPEP 2106 which has incorporated the 2019 PEG . Regarding to claim 1, Step 1 Analysis : Claim 1 is directed to a system, which is directed to a process, one of the statutory categories. Step 2A Prong One Analysis: Claim 1 recites: “ receive an application programming interface (API) call comprising an API input parameter indicating a value of a flag; and in response to the API call, cause the flag to be set within a primary context data structure to indicate whether one or more memory operations to be performed are dependent on one or more other memory operations, wherein the primary context data structure comprises information defining behaviors of an accelerator . ” This element reads on a person receives an API to set a flag into a structure to indicate whether one or more operations to be performed are dependent on other operation(s), the structure comprising information defining behaviors of an accelerator which could be considered a mental process of an observation or evaluation. Overall, the limitations directed to set a flag to determine whether to perform dependent operation and the various mental process limitations in the context of this claim encompasses limitations that are not only considered to be directed to limitations that could be practically performed in the human mind (including observations and preform an evaluation, judgment, and opinion) aided by the use of pen and paper. If the claim limitations, under their broadest reasonable interpretations, cover performance of the limitation in the mind but for the recitation of generic computer components, then they fall within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. Step 2A Prong Two Analysis: In Step 2A Prong 2, we are directed to Identify whether there are any additional elements recited in the claim beyond the judicial exception(s) and evaluate those additional elements to determine whether they integrate the exception into a practical application of the exception. In particular, the claim only recites the additional element of “One or more processors”, “circuitry”, “one or more kernels.” Regarding the one or more processors, The processor of a computer system for generating and storing in all steps is recited at a high level of generality, i.e. , as a generic processor performing a generic computer function of processing data (generating and storing). This generic processor limitation is no more than mere instructions to apply the exception using a generic computer component(s). Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. Regarding the circuitry, The circuitry of a processor for generating and storing in all steps is recited at a high level of generality, i.e. , as a generic circuitry performing a generic computer function of processing data (generating and storing). This generic circuitry limitation is no more than mere instructions to apply the exception using a generic computer component(s). Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. Regarding the one or more kernels, The one or more kernels of a processor for generating and storing in all steps is recited at a high level of generality, i.e. , as a generic one or more kernels performing a generic computer function of processing data (generating and storing). This generic one or more kernels limitation is no more than mere instructions to apply the exception using a generic computer component(s). Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The additional elements of “one or more processors”, “circuitry”, and “one or more kernels” are simply applying the abstract idea, and there is nothing done with results. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea, and does not provide any improvement in computer technology (see MPEP2106.05(a)). Therefore, the additional elements do not integrate the judicial exception into a practical application. Step 2B Analysis : In Step 2B, we are directed to Identify whether there are any additional elements recited in the claim beyond the judicial exception(s) and evaluate those additional elements to determine whether the additional elements, taken individually and in combination, result in the claim as a whole amounting to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “one or more processors”, “circuitry”, and “one or more kernels” are simply applying the abstract idea, and there is nothing done with results. Accordingly, these additional elements, taken individually and in combination, do not result in the claim as a whole amounting to significantly more than the judicial exception. The claim is not patent eligible. Regarding claim 2, Step 1 Analysis: Claim 2 is directed to a system, which is directed to a process, one of the statutory categories. Step 2A Prong One Analysis: Claim 2 is dependent on claim 1, which as indicated in the analysis above, is directed to an abstract idea without significantly more. Claim 2 recites “wherein the primary context data structure indicates a context to be used by one or more graphics processing units (GPUs) to perform the one or more memory operations and the one or more other memory operations." That is, the claim recites wherein the primary context data structure indicates a context to be used by one or more graphics processing units (GPUs) to perform the one or more memory operations and the one or more other memory operations. The above-noted limitation of claim 2, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. Step 2A Prong Two Analysis: This judicial exception is not integrated into a practical application. Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. Regarding claim 3, Step 1 Analysis: Claim 3 is directed to a system, which is directed to a process, one of the statutory categories. Step 2A Prong One Analysis: Claim 3 is dependent on claim 1, which as indicated in the analysis above, is directed to an abstract idea without significantly more. Claim 3 recites “the one or more memory operations are to be performed by the circuitry after the one or more other memory operations complete." That is, the claim recites the one or more memory operations are to be performed by the circuitry after the one or more other memory operations complete. The above-noted limitation of claim 3, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. Step 2A Prong Two Analysis: This judicial exception is not integrated into a practical application. Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. Regarding claim 4, Step 1 Analysis: Claim 4 is directed to a system, which is directed to a process, one of the statutory categories. Step 2A Prong One Analysis: Claim 4 is dependent on claim 1, which as indicated in the analysis above, is directed to an abstract idea without significantly more. Claim 4 recites “the flag is to indicate to the circuitry that at least one of the one or more memory operations is to be performed synchronously." That is, the claim recites the flag is to indicate to the circuitry that at least one of the one or more memory operations is to be performed synchronously. The above-noted limitation of claim 4, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. Step 2A Prong Two Analysis: This judicial exception is not integrated into a practical application. Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. Regarding claim 5, Step 1 Analysis: Claim 5 is directed to a system, which is directed to a process, one of the statutory categories. Step 2A Prong One Analysis: Claim 5 is dependent on claim 1, which as indicated in the analysis above, is directed to an abstract idea without significantly more. Claim 5 recites “the flag is to indicate to the circuitry that at least one of the one or more memory operations is to be performed asynchronously." That is, the claim recites the flag is to indicate to the circuitry that at least one of the one or more memory operations is to be performed asynchronously. The above-noted limitation of claim 5, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. Step 2A Prong Two Analysis: This judicial exception is not integrated into a practical application. Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. Regarding claim 7, Step 1 Analysis: Claim 7 is directed to a system, which is directed to a process, one of the statutory categories. Step 2A Prong One Analysis: Claim 7 is dependent on claims 1, which as indicated in the analysis above, is directed to an abstract idea without significantly more. Claim 7 recites “the API is to cause the circuitry to receive one or more input values indicating a device to be used to perform the one or more memory operations and the one or more other memory operations." That is, the claim recites the API is to cause the circuitry to receive one or more input values indicating a device to be used to perform the one or more memory operations and the one or more other operations. The above-noted limitation of claim 7, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. Step 2A Prong Two Analysis: This judicial exception is not integrated into a practical application. Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. Regarding claim 21, Step 1 Analysis: Claim 21 is directed to a system, which is directed to a process, one of the statutory categories. Step 2A Prong One Analysis: Claim 21 is dependent on claims 1, which as indicated in the analysis above, is directed to an abstract idea without significantly more. Claim 21 recites “wherein setting the flag within the primary context data structure causes the one or more other memory operations to be added in a stream to be performed by one or more accelerators within a heterogenous processor." That is, the claim recites setting the flag within the primary context data structure causes the one or more other memory operations to be added in a stream to be performed by one or more accelerators within a heterogenous processor. The above-noted limitation of claim 21, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. Step 2A Prong Two Analysis: This judicial exception is not integrated into a practical application. Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. Regarding claim 22, Step 1 Analysis: Claim 22 is directed to a system, which is directed to a process, one of the statutory categories. Step 2A Prong One Analysis: Claim 22 is dependent on claims 1, which as indicated in the analysis above, is directed to an abstract idea without significantly more. Claim 22 recites “wherein the flag is encoded as one or more bits." That is, the claim recites wherein the flag is encoded as one or more bits. The above-noted limitation of claim 22, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. Step 2A Prong Two Analysis: This judicial exception is not integrated into a practical application. Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. Regarding claim 23, Step 1 Analysis: Claim 23 is directed to a system, which is directed to a process, one of the statutory categories. Step 2A Prong One Analysis: Claim 23 is dependent on claims 1, which as indicated in the analysis above, is directed to an abstract idea without significantly more. Claim 23 recites “ wherein the primary context data structure further stores another flag indicating whether pinned host memory is to be mapped for access by the one or more software kernels ." That is, the claim recites wherein the primary context data structure further stores another flag indicating whether pinned host memory is to be mapped for access by the one or more software kernels . The above-noted limitation of claim 23, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. Step 2A Prong Two Analysis: This judicial exception is not integrated into a practical application. Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. Claims 8-12 are rejected under 35 U.S.C. 101 with the same rational of claims 1-5. Claims 14-19 are rejected under 35 U.S.C. 101 with the same rational of claims 1-5. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-02-aia AIA 5. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-20-aia AIA 6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA 7. The factual inquiries set forth in Graham v. John Deere Co. , 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA 8. Claim s 1-4, 7-11, 14-18 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over HUYNH in view of FONTAINE et al (CN 116802613 A, hereinafter “FONTAINE”) . 9. With respect to claim 1, HUYNH discloses one or more processors, comprising: circuitry to, in response to an application programming interface (API) call comprising an API parameter , cause a primary context data structure to indicate whether one or more memory operations to be performed are dependent on one or more other memory operations (HUYNH pages 31-32 e.g. In various examples, the output 1938 of the second stage 1936 includes the respective steps to be performed by the components of the accelerating engine 1912 in the order of the steps to be performed. For example, output 1938 can be represented as a data flow graph , wherein the node in the graph represents a memory operation, calculating and other operations, and the side or connection between the nodes represents the dependency relationship between the nodes, such as data dependency relationship, memory dependency relationship or operation dependency relationship and other examples … In the example of FIG. 19, the host system 1900 may execute the driver 1922 of the management accelerating engine 1912, which may also be referred to as a device driver or a runtime driver. The driver 1922 may provide an interface between the application executed on the host system 1900 (or another host system) and the accelerating engine 1912. For example, the driver 1922 may provide an application program interface (API), which defines functions for feeding input data to the accelerating engine 1912 and defining operations performed on the input data [as circuitry (e.g. integrated circuit device) to, in response to an application programming interface (API) (e.g. application program interface (API)) call comprising an API parameter, cause a primary context data structure (e.g. a data flow graph) to indicate whether one or more memory (e.g. memory operations) operations to be performed (e.g. operations performed) are dependent (e.g. operation dependency) on one or more other memory operations ]) . Although HUYNH substantially teaches the claimed invention, HUYNH does not explicitly indicate an API input parameter indicating a value of a flag; a flag to be set within a primary context data structure; wherein the primary context data structure comprises information defining behaviors of an accelerator during execution of one or more software kernels . FONTAINE teaches the limitations by stating circuitry to: receive an application programming interface (API) call comprising an API input parameter indicating a value of a flag; and in response to the API call, cause the flag to be set within a primary context data structure to indicate whether one or more memory operations to be performed are dependent on one or more other memory operations , wherein the primary context data structure (e.g. execution graphics – dependency path) comprises information defining behaviors (e.g. a call process for sending an instruction to update an execution graphics parameter is a process executed on a GPU ) of an accelerator (FONTAINE pages 32-33, 67, 71 and Fig. 24 e.g. an accelerator (e.g., GPU or FPGA)) during execution of one or more software kernels (FONTAINE pages 9, 17, 20, 54-56, 59, 64-65 e.g. … the selected node that is not a node waiting for user operation from an external process is a kernel node that invokes the kernel function on the GPU at block 1212 by executing the kernel function using a thread block, as described herein) (VOGLREITER [0091] – [0096] e.g. [0091] Aspects of the present disclosure can reuse the s_buffer as the v_buffer, and thus may utilize two buffers rather than three buffers. Additionally, the algorithm herein can use efficient bit operations in the second pass and may not utilize a loop. The present disclosure can utilize a find first set (ffs) bit operation to find the first combination of the d_buffer and the s_buffer, i.e., ffs(D&S), where ‘&’ is a bitwise ‘and.’ Also, the present disclosure can clear the first found bit and perform the same operation to consider the consumed flag. The present disclosure can proceed with ffs(S&!D). Using a bit shift, the present disclosure can generate bit masks to set the v_buffer and the d_buffer all the way through, e.g., one bit-wise operation per 32 or 64 bit word. The present disclosure can use the v_buffer for early-z testing in the final pass, i.e., set the depth buffer value to the first cell that is not visible. [0093] FIG. 11 illustrates an example diagram 1100 in accordance with one or more techniques of this disclosure. More specifically, diagram 1100 includes a number of components for the order-independent occlusion computations described herein. As shown in FIG. 11, diagram 1100 includes 1110 , vertex shader 1120 , fragment shader 1130 , and compute shader 1140 . As described herein, GPU 1110 , vertex shader 1120 , fragment shader 1130 , and compute shader 1140 can perform a number of different steps or processes to determine visible primitives in order-independent occlusion computations.) (FONTAINE pages 13-15 e.g. FIG. 5 illustrates an example repeat initiation sequence 500 of instantiated execution graphics according to at least one embodiment. In at least one embodiment, the template execution pattern 502 includes a simple pattern having four nodes "A"-"D" and a simple dependency path from "A" to "B" to "C" to "D" . In at least one embodiment, the exemplary repeat initiation sequence 500 shows a stream of initiation sequences in which the operations represented by the nodes "A"-"D" are repeatedly initiated using an execution pattern . In at least one embodiment, an execution pattern is constructed from an execution pattern template. In at least one embodiment, a graphics construction API is used to construct execution graphics . In at least one embodiment, an execution pattern is constructed from an execution stream. In at least one embodiment, after block 602, proceeding to block 604 is performed. In at least one embodiment, at block 604, it is determined whether the execution pattern is a valid execution pattern. In at least one embodiment, at block 604, whether the execution pattern is a valid execution pattern is determined by traversing the execution pattern to determine whether the node of the execution pattern is a valid node . In at least one embodiment, whether the execution graph is a valid execution graph is determined by traversing the execution graph to determine whether dependencies between nodes of the execution graph are valid dependencies. In at least one embodiment, it is determined whether the execution pattern is a valid execution pattern by evaluating the topology of the execution pattern. In at least one embodiment, it is determined whether the execution pattern is a valid execution pattern by evaluating shape information associated with the execution pattern. In at least one embodiment, if it is determined at block 604 that the execution pattern is not a valid execution pattern ("NO" branch), the execution proceeds to block 606. In at least one embodiment, if itis determined at block 604 that the execution pattern is a valid execution pattern ("yes" branch), the execution proceeds to block 608 . In at least one embodiment, an error is returned at block 606. In at least one embodiment, an error is returned to the call procedure. In at least one embodiment, an error is returned using an error report API . In at least one embodiment, an error is returned by using a signal. In at least one embodiment, the error is returned by using a signpost. In at least one embodiment, an error is returned by using a flag value . In at least one embodiment, after block 606, execution of the example process 600 is terminated. In at least one embodiment, at block 608, it is determined whether the execution pattern is updated using those systems and methods as described herein. In at least one embodiment, it is determined whether to update the execution graphics based on an instruction to update the execution graphics parameter received prior to initiating the graphics instance of the execution graphics. In at least one embodiment, instructions for updating execution graphical parameters are received from a call process . In at least one embodiment, the call process for sending an instruction to update execution of the graphical parameter is a process executed on the CPU. In at least one embodiment, a call process for sending an instruction to update an execution graphics parameter is a process executed on a GPU . In at least one embodiment, at block 608, when an instruction to update the execution graphic parameter is received from the call procedure, it is determined whether the execution graphic is updated. In at least one embodiment, at block 608, it is determined whether to update the execution pattern when an instruction for updating the execution pattern parameter is received using the API . In at least one embodiment, instructions for updating execution of graphical parameters are received using signals. In at least one embodiment, instructions for updating execution of a graphical parameter are received using a signpost. In at least one embodiment, a flag value is used to receive instructions for updating execution of a graphical parameter [as receive an application programming interface (API) (e.g. API) call (e.g. call) comprising an API input parameter (e.g. parameter) indicating a value of a flag (e.g. flag value) ; and in response to the API call, cause the flag to be set within a primary context data structure (e.g. execution graphics – dependency path) to indicate whether one or more memory operations (e.g. operations) to be performed (e.g. valid) are dependent on (e.g. execution graphics – dependency path) one or more other memory operations (e.g. operations) , wherein the primary context data structure (e.g. execution graphics – dependency path) comprises information defining behaviors (e.g. a call process for sending an instruction to update an execution graphics parameter is a process executed on a GPU) of an accelerator (FONTAINE pages 32-33, 67, 71 and Fig. 24 e.g. an accelerator (e.g., GPU or FPGA)) during execution of one or more software kernels ]) . Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention, in view of the teachings of HUYNH and FONTAINE, to efficiently using the processing component array to realize manual neural network and reduce the data transmitted from the memory (HUYNH page 3). 10. With respect to claim 2, HUYNH discloses wherein the primary context data structure indicates a context (HUYNH page 32 e.g. input data) to be used by the one or more graphics processing units (GPUs) to perform the one or more memory operations and the one or more other memory operations. 11. With respect to claim 3, HUYNH discloses wherein the one or more memory operations are to be performed by the circuitry after the one or more other memory operations complete (HUYNH page 28 e.g. Although flow chart 1800 can describe the operation as a sequence process; see Gyllenskog et al (US 20230289094 A1) [0072] In some cases, the memory system 310 may execute the command 330 in the order received from the host system 305 … as part of performing the commands 330, the memory system 310 may store a command table or other indication of the sequence identifiers 345 of completed commands, for example in a non-volatile portion of the memory system 310) . 12. With respect to claim 4, HUYNH discloses wherein the flag is to indicate to the circuitry that at least one of the one or more memory operations is to be performed synchronously (HUYNH pages 4, 31, 32 e.g. [pages 31-32] The third stage 1940 may operate on the output 1938 of the second stage 1936, and each step is performed before generating the instructions to be executed by the accelerating engine 1912. For example, the steps may include: removing the redundancy dependency relationship; solving or processing the dependency relationship between the nodes by inserting the synchronization instruction into the code ; identifying possible optimisation of memory usage or memory bandwidth usage; and other operations. In some examples, the third stage 1940 may include a data scheduler1950) . 13. With respect to claim 7, FONTAINE discloses wherein the circuitry, in response to the API call, is to receive one or more input values indicating a device to be used to perform the one or more memory operations and the one or more other operations (FONTAINE pages 13-15 e.g. node) . 14. With respect to claim 21, FONTAINE discloses wherein setting the flag within the primary context data structure causes the one or more other memory operations to be added in a stream to be performed by one or more accelerators within a heterogenous processor (FONTAINE pages 5, 13-15, 22-24, 27-28 e.g. operations; stream; processors). 15. Claims 8-11 are same as claims 1-4 and are rejected for the same reasons as applied hereinabove. 16. Claims 15-18 are same as claims 1-4 and are rejected for the same reasons as applied hereinabove . 07-21-aia AIA 17. Claim s 5, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over HUYNH in view of FONTAINE, and further in view of Williams . 18. With respect to claim 5, HUYNH discloses wherein the indication is to indicate to the one or more circuitry that at least one of the one or more memory operations is to be performed asynchronously (HUYNH page 28 e.g. Although flow chart 1800 can describe the operation as a sequence process) . Although HUYNH and FONTAINE combination substantially teaches the claimed invention, they do not explicitly indicate wherein the flag is to indicate to the circuitry that at least one of the one or more memory operations is to be performed asynchronously . Williams teaches the limitations by stating wherein the flag is to indicate to the circuitry that at least one of the one or more memory operations is to be performed asynchronously (Williams [0013] e.g. [0013] Viewed from a first aspect, the present invention provides a data processing apparatus comprising: a device operable to perform a sequence of operations including memory operations on data values having associated data addresses, for at least some of the memory operations the data address being determined relative to an architectural state value of an item of architectural state of the device; and trace logic operable to receive indications of the sequence of operations being performed by the device , and to generate from said indications a stream of trace elements; when for a memory operation the data address is determined to have been determined relative to an architectural state value of said item of architectural state, the trace logic being operable dependent on that item of architectural state to omit at least one of a data address indication and a data value indication from the stream of trace elements generated in respect of that memory operation) . Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention, in view of the teachings of HUYNH and Williams, to efficiently using the processing component array to realize manual neural network and reduce the data transmitted from the memory (HUYNH page 3). 19. Claim 12 is same as claim 5 and is rejected for the same reasons as applied hereinabove. 20. Claim 19 is same as claim 5 and is rejected for the same reasons as applied hereinabove . 07-21-aia AIA 21. Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over HUYNH in view of FONTAINE, and further in view of VOGLREITER et al (US 20210383597 A1, hereinafter “VOGLREITER”) . 22. With respect to claim 22, Although HUYNH and FONTAINE combination substantially teaches the claimed invention, they do not explicitly indicate wherein the flag is encoded as one or more bits . VOGLREITER teaches the limitations by stating wherein the flag is encoded as one or more bits (VOGLREITER [0091] – [0096] e.g. [0091] Aspects of the present disclosure can reuse the s_buffer as the v_buffer, and thus may utilize two buffers rather than three buffers. Additionally, the algorithm herein can use efficient bit operations in the second pass and may not utilize a loop. The present disclosure can utilize a find first set (ffs) bit operation to find the first combination of the d_buffer and the s_buffer, i.e., ffs(D&S), where ‘&’ is a bitwise ‘and.’ Also, the present disclosure can clear the first found bit and perform the same operation to consider the consumed flag. The present disclosure can proceed with ffs(S&!D). Using a bit shift, the present disclosure can generate bit masks to set the v_buffer and the d_buffer all the way through, e.g., one bit-wise operation per 32 or 64 bit word. The present disclosure can use the v_buffer for early-z testing in the final pass, i.e., set the depth buffer value to the first cell that is not visible. [0093] FIG. 11 illustrates an example diagram 1100 in accordance with one or more techniques of this disclosure. More specifically, diagram 1100 includes a number of components for the order-independent occlusion computations described herein. As shown in FIG. 11, diagram 1100 includes 1110 , vertex shader 1120 , fragment shader 1130 , and compute shader 1140 . As described herein, GPU 1110 , vertex shader 1120 , fragment shader 1130 , and compute shader 1140 can perform a number of different steps or processes to determine visible primitives in order-independent occlusion computations.) . Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention, in view of the teachings of HUYNH, FONTAINE and VOGLREITER, to efficiently using the processing component array to realize manual neural network and reduce the data transmitted from the memory (HUYNH page 3) . 07-21-aia AIA 23. Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over HUYNH in view of FONTAINE, and further in view of JUNG (US 20170235671 A1, hereinafter “JUNG”) . 24. With respect to claim 23, Although HUYNH and FONTAINE combination substantially teaches the claimed invention, they do not explicitly indicate wherein the primary context data structure further stores another flag indicating whether pinned host memory is to be mapped for access by the one or more software kernels . JUNG teaches the limitations by stating wherein the primary context data structure further stores another flag (JUNG [0081] - [0092] and Figs. 7-8 e.g. register) indicating whether pinned host memory is to be mapped for access by the one or more software kernels (JUNG [0081] - [0092] and Figs. 7-8 e.g. [0081] Referring to FIG. 7, an NOMA 622 uses a system memory block 700 mapped to a GPU memory 121. The system memory block 700 is a kernel buffer allocated to a CPU memory 131, and includes a memory- mapped register 710 and a GPU pinned memory space 720 . The memory- mapped register 710 is a register which a disk driver controller (for example, an NVMe controller) for an SSO 110 manages , and the GPU pinned memory space 720 is a space mapped to the GPU memory 121 . [0092] Referring to FIG. 8, an NOMA 622 uses a system memory block 800 mapped to a GPU memory 121. The system memory block 800 is a kernel buffer allocated to a CPU memory 131, and includes a memory-mapped register 810 and a GPU pinned memory space 820. The memory-mapped register 810 is a register which a disk driver controller (for example, an AHCI controller) for an SSD 110 manages, and the GPU pinned memory space 820 is a space mapped to the GPU memory 121. ) . Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention, in view of the teachings of HUYNH, FONTAINE and JUNG, to efficiently using the processing component array to realize manual neural network and reduce the data transmitted from the memory (HUYNH page 3). Response to Arguments 25. On pages 10-11, Applicant alleges the Claim Is Not Directed to an Abstract Idea. Examiner disagrees because: Claim 1 recites: “ receive an application programming interface (API) call comprising an API input parameter indicating a value of a flag; and in response to the API call, cause the flag to be set within a primary context data structure to indicate whether one or more memory operations to be performed are dependent on one or more other memory operations, wherein the primary context data structure comprises information defining behaviors of an accelerator . ” This element reads on a person receives an API to set a flag into a structure to indicate whether one or more operations to be performed are dependent on other operation(s), the structure comprising information defining behaviors of an accelerator which could be considered a mental process of an observation or evaluation. Overall, the limitations directed to set a flag to determine whether to perform dependent operation and the various mental process limitations in the context of this claim encompasses limitations that are not only considered to be directed to limitations that could be practically performed in the human mind (including observations and preform an evaluation, judgment, and opinion) aided by the use of pen and paper. If the claim limitations, under their broadest reasonable interpretations, cover performance of the limitation in the mind but for the recitation of generic computer components, then they fall within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. 26. On pages 10-11, Applicant alleges alleged Mental Process Is Integrated Into A Practical Application Examiner disagrees because: Step 2A Prong Two Analysis: In Step 2A Prong 2, we are directed to Identify whether there are any additional elements recited in the claim beyond the judicial exception(s) and evaluate those additional elements to determine whether they integrate the exception into a practical application of the exception. In particular, the claim only recites the additional element of “One or more processors”, “circuitry”, “one or more kernels.” Regarding the one or more processors, The processor of a computer system for generating and storing in all steps is recited at a high level of generality, i.e. , as a generic processor performing a generic computer function of processing data (generating and storing). This generic processor limitation is no more than mere instructions to apply the exception using a generic computer component(s). Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. Regarding the circuitry, The circuitry of a processor for generating and storing in all steps is recited at a high level of generality, i.e. , as a generic circuitry performing a generic computer function of processing data (generating and storing). This generic circuitry limitation is no more than mere instructions to apply the exception using a generic computer component(s). Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. Regarding the one or more kernels, The one or more kernels of a processor for generating and storing in all steps is recited at a high level of generality, i.e. , as a generic one or more kernels performing a generic computer function of processing data (generating and storing). This generic one or more kernels limitation is no more than mere instructions to apply the exception using a generic computer component(s). Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The additional elements of “one or more processors”, “circuitry”, and “one or more kernels” are simply applying the abstract idea, and there is nothing done with results. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea, and does not provide any improvement in computer technology (see MPEP2106.05(a)). Therefore, the additional elements do not integrate the judicial exception into a practical application. 27. On pages 10-11, Applicant alleges the Claim Recites Significantly More. Examiner disagrees because: Step 2B Analysis : In Step 2B, we are directed to Identify whether there are any additional elements recited in the claim beyond the judicial exception(s) and evaluate those additional elements to determine whether the additional elements, taken individually and in combination, result in the claim as a whole amounting to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “one or more processors”, “circuitry”, and “one or more kernels” are simply applying the abstract idea, and there is nothing done with results. Accordingly, these additional elements, taken individually and in combination, do not result in the claim as a whole amounting to significantly more than the judicial exception. The claim is not patent eligible. 28. Applicant’s remarks and arguments presented on pages 11-15 have been fully considered but they are moot in view of the new grounds of rejection presented in this office action. Conclusion The prior art made of record, listed on form PTO-892, and not relied upon, if any, is considered pertinent to applicant's disclosure. 29. The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. 30. When responding to this office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the reference cited or the objections made. He or she must also show how the amendments avoid such references or objections See 37 CFR 1.111(c). Any inquiry concerning this communication or earlier communications from the examiner should be directed to SyLing Yen whose telephone number is 571-270-1306. The examiner can normally be reached on Mon-Fri 8:30am - 5:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sanjiv Shah can be reached at 571-272-4098. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SYLING YEN/Primary Examiner, Art Unit 2166 June 1, 2026 Application/Control Number: 18/114,628 Page 2 Art Unit: 2166
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