Prosecution Insights
Last updated: July 17, 2026
Application No. 18/114,653

SEMICONDUCTOR PACKAGE AND A SEMICONDUCTOR DEVICE MODULE INCLUDING THE SAME

Final Rejection §102§103
Filed
Feb 27, 2023
Priority
Mar 07, 2022 — EU 22160553.8
Examiner
PRASAD, NEIL R
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Infineon Technologies AG
OA Round
2 (Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
607 granted / 711 resolved
+17.4% vs TC avg
Moderate +10% lift
Without
With
+9.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
20 currently pending
Career history
731
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
82.5%
+42.5% vs TC avg
§102
10.3%
-29.7% vs TC avg
§112
0.4%
-39.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 711 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed 1/13/2026 have been fully considered but they are not persuasive. Regarding claim 1, applicant argues that elements 126 lower side and 142 lower side of Kim cannot both be main surfaces. However, applicant describes the die carrier to comprise two main surfaces (first and second) in the specification. Regardless, the conductive elements connected to the pads are on the same side exposed by the encapsulant. Therefore, a main surface (142 lower) of the encapsulant (120) is coplanar with upper surfaces (144) of the first electrical connector (104) and a main surface (126) of the encapsulant (120) is coplanar with the second electrical connector (131/132). Element 131 is electrically connected to 106 and element 132 is electrically connected to 108, both of which are exposed and coplanar with surface 142. Regarding claim 7, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3, 11-14, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US Publication No. 2020/0357729). Regarding claim 1, Kim discloses a semiconductor package, comprising: a die carrier (114/116) comprising a first main face (down) and a second main face (up) opposite to the first main face a semiconductor die (102) disposed on the die carrier (114/116), the semiconductor die comprising a first pad (138) and a second pad (132) a first electrical connector (104) disposed on the first pad (138) an encapsulant (120) at least partially covering the semiconductor die (102), the die carrier (114/116), and the first electrical connector (104) an insulation layer (112) disposed on the second main face (up) of the die carrier (114/116) wherein upper surfaces of the first electrical connector (104) and the second electrical connector (131 or 132) are not covered by the encapsulant (120) wherein a main surface (126/142) of the encapsulant (120) is coplanar with the upper surfaces of the first electrical connector (104) and the second electrical connector (131) Regarding claim 2, Kim discloses the semiconductor die comprises a vertical transistor in which the first pad (138S) is disposed on a first main face (down) of the semiconductor die (102) remote from the die carrier (114/116) and the second pad (132D) is disposed on a second main face (up) of the semiconductor die (102) and connected with the first main face (down) of the die carrier (116). Regarding claim 3, Kim discloses the first pad (138) is a source pad (138) and the second pad (132) is a drain pad (132) (paragraph 37). Regarding claim 11, Kim discloses a leadframe, wherein the die carrier is part of the leadframe (Figure 12; paragraph 35). Regarding claim 12, Kim discloses the insulation layer (112) comprises one or more of an organic insulator, a polymer, a resin, an epoxy resin, a ceramic material, or one of the above filled with ceramic particles (paragraph 29). Regarding claim 13, Kim discloses the insulation layer (112) is an integral insulation layer (situated between metals 116 and 118) of the die carrier (Figure 5; paragraph 29). Regarding claim 14, Kim discloses the insulation layer (112) is a part of and contiguous with the encapsulant (120). Regarding claim 21, Kim discloses a semiconductor package, comprising: a leadframe (108) a die carrier (116) that is part of the leadframe (108), the die carrier comprising a first main face (126) and a second main face (115) opposite to the first main face (126) a semiconductor die (101/102) disposed on the die carrier (116), the semiconductor die comprising a first and second pad a first electrical connector (104) disposed on the first pad (138) an encapsulant (120) at least partially covering the semiconductor die (101/102), the die carrier (116), and the first electrical connector (104) an insulation layer (112) disposed on the second main face (115) of the die carrier (116) Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Publication No. 2020/0357729) in view of Ichiryu et al. (US Publication No. 2020/0027814). Regarding claim 7, Kim discloses the limitations as discussed in the rejection of claim 1 above. Kim does not disclose a further pad disposed on a first main face of the semiconductor die remote from the die carrier; and a further electrical connector disposed on the further pad, wherein a surface of the further electrical connector is not covered by the encapsulant. However, Ichiryu discloses a further pad (35 ohmic pad) disposed on a first main face of the semiconductor die (3) remote from the die carrier (2); and a further electrical connector (35 pad electrode) disposed on the further pad (paragraph 118), wherein a surface of the further electrical connector (35) is not covered by the encapsulant (4). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the device of Kim to form further pads in relation to the encapsulant, as taught by Ichiryu, since it can allow for improved humidity resistance (paragraph 54) and heat dissipation through conductor layers (paragraph 58). Regarding claim 8, Ichiryu discloses a main surface of the encapsulant (4) is coplanar with the surface of the further electrical connector (71) that is not covered by the encapsulant (40). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Kim in view of Ichiryu. Regarding claim 9, Ichiryu discloses the further pad comprises a gate pad (35G). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Kim in view of Ichiryu. Regarding claim 10, Ichiryu discloses the semiconductor die (3) comprises a lateral transistor (paragraph 117) in which the first pad (35) comprises a source pad (35S) and the second pad (35) comprises a drain pad (35D) and both the first and second pads are disposed on a first main face (upper side) of the semiconductor die (3) remote from the die carrier (2). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Kim in view of Ichiryu. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Publication No. 2020/0357729) in view of Mamitsu et al. (US Patent No. 6,703,707). Regarding claim 15, Kim discloses a semiconductor device module, comprising: a die carrier (116) comprising a first main face and a second main face opposite the first main face a semiconductor die (102) disposed on the die carrier (116), the semiconductor die (102) comprising a first pad (138) and a second pad (132) a first electrical connector (104) disposed on the first pad (138) an encapsulant (120) at least partially covering the semiconductor die (102), the die carrier (116), and the first electrical connector (104) an insulation layer (112) disposed on the second main face (115) of the die carrier (116) Kim does not disclose a package carrier comprising an opening for the semiconductor package. However, Mamitsu discloses a package carrier (160) with an opening (within 162) enclosing a package (101/102) (Figure 14). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Kim to be included in a package carrier opening as taught by Mamitsu, since it can improve the radiation property of the device and electrical conductivity (col. 2, lines 17-34). Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Publication No. 2020/0357729) in view of Mamitsu et al. (US Patent No. 6,703,707), and further in view of Ichiryu et al. (US Publication No. 2020/0027814). Regarding claim 16, Kim/Mamitsu discloses the limitations as discussed in the rejection of claim 15 above. Kim?Mamitsu does not disclose the package carrier is a printed circuit board. However, Ichiryu discloses the package carrier is a printed circuit board (paragraph 50). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package carrier of Kim/Mamitsu to be a printed circuit board, as taught by Ichiryu, since it can imprive heat dissipation properties (paragraphs 83-84) and thermal resistance to reduce bonding re-melting during secondary implementation process (paragraph 50). Regarding claim 17, Ichiryu discloses a first insulation layer (38) covering at least portions of the package carrier (2) and the semiconductor package (3). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Kim in view of Ichiryu. Regarding claim 18, Ichiryu discloses the first insulation layer (38) comprises electrical vias (71) connected with the first electrical connector (35). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Kim in view of Ichiryu. Regarding claim 19, Ichiryu discloses a second insulation layer (8) disposed above a first main face of the first insulation layer (38); and a third insulation layer (9) disposed above a second main face of the first insulation layer (38). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Kim in view of Ichiryu. Regarding claim 20, Ichiryu discloses a heatsink (5) applied to a lower surface; and electrical or electronic components (3) applied to an upper surface (Figure 7). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Kim in view of Ichiryu. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /N.R.P/ 5/13/2026Examiner, Art Unit 2897 /JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Feb 27, 2023
Application Filed
Nov 03, 2025
Non-Final Rejection mailed — §102, §103
Jan 13, 2026
Response Filed
May 21, 2026
Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
95%
With Interview (+9.5%)
2y 2m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 711 resolved cases by this examiner. Grant probability derived from career allowance rate.

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