CTFR 18/114,664 CTFR 89277 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 2. In response to the Office action mailed on 1/12/2026, the applicants have filed a response: claims 1 – 7, 9, 12, 14 – 16, 19 and 20 have been amended and claim 21 has been added. Claims 1 – 21 are pending. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA 4. Claims 1, 2, 6 – 9, 13 – 16 and 20 are r ejected under 35 U.S.C. 102(a)(2) as being a nticipated by Bolz et al. (U.S. Publication 2011/0063313) (Bolz hereinafter) (Identified b y A pplicant in IDS). 5 . As per claim 1, Bolz teaches a processor comprising: circuitry to cause, in response to receipt of an application programming interface (API) call [“ FIG. 4 is a flow diagram of method steps for executing a memory barrier command within a stream of graphics application programming interface commands ,” ¶ 0043] an indication to be read from a primary context data structure [“ The texture buffer 166 stores data elements typically organized in one dimensional arrays. The vertex buffer 165 stores data elements describing the position and other attributes of vertices provided as inputs to the vertex shader 152 ,” ¶ 0018; arrays mapped to data structures ; “ a memory management unit (MMU) 158. As is well-known, the vertex shader 152 receives a sequence of one or more sets of vertex attributes, where each set of vertex attributes is typically associated with one vertex and one or more vertices are associated with a geometric primitive. The vertex shader 152 processes the vertex attributes ,” ¶ 0020; “ The data assembler 260 may gather data from buffers stored within system memory 110 and GPU local memory 160 as well as from API calls from the application program 112 used to specify vertex attributes ,” ¶ 0028; vertex shader processing the vertex attributes and data assembler gathering data from buffers both suggest an indication to be read from a primary context data structure ] of whether one or more memory operations to be performed are dependent on one or more other memory operations [“ As described in greater detail below with respect to FIG. 4, high-level memory barrier (memoryBarrierNV()) commands are executable, by the GPU 150, within a stream of graphics API operations, where the memory barrier commands guarantee the synchronization of memory operations scheduled to be executed in a pipeline prior to the execution of each memory barrier command ,” ¶ 0042; barrier command execution guarantees synchronization of memory operations, suggesting memory operations dependence ; ” When data is written by one thread and consumed by other threads launched as a result of the execution of the one thread, coherent memory accesses should be performed, followed by a memory barrier command in the one thread. Further, the dependent threads should perform coherent memory loads when loading the data written by the first thread ,” ¶ 0081]. 6. As per claim 2, Bolz teaches the one or more processors of claim 1. Bolz further teaches wherein the primary context data structure indicates a context to be used by the circuitry to perform the one or more memory operations and the one or more other memory operations [“ The memoryBarrierNV() OpenGL Shading Language (GLSL) operation—along with the “MEMBAR’ assembly operation, provides explicit synchronization that ensures a proper ordering of read and write operations within a shader thread. Memory operations scheduled for execution prior to the memory barrier command are all guaranteed to have completed to a point of coherence when the memory barrier command completes in execution. Further, the compiler does not re-order any load and store memory operations that are scheduled to execute subsequent to a memory barrier command, preventing any automatic optimizations from compromising the guaranteed point of coherence while permitting optimizations between barriers ,” ¶ 0039; memory barrier command mapped to memory operation, read/write operations mapped to other operations ]. 7. As per claim 6, Bolz teaches the one or more processors of claim 1. Bolz further teaches wherein the circuitry, in further response to receipt of the API call, is to receive one or more input values indicating a storage location to which the indication is to be read [“ Memory barrier commands are needed for algorithms that allow multiple threads to access the same memory location. For such algorithms, memory operations associated with that memory location need to be performed in a partially-defined relative order ,” ¶ 0040]. 8. As per claim 7, Bolz teaches the one or more processors of claim 1. Bolz further teaches wherein the API is to cause the circuitry, in further response to receipt of the API call, is to receive one or more input values indicating a storage location to which a state of a context to be used to perform the one or more memory operations and the one or more other memory operations is to be stored [“ FIG. 5 is a flow diagram of method steps for executing a memory barrier command in the context of a shader program that has multiple program invocations update a single shared block of memory ,” 0015]. 9. As per claim 8, it is a method claim having similar limitations as cited in claim 1. Thus, claim 8 is also rejected under the same rationale as cited in the rejection of claim 1 above. 10. As per claim 9, it is a method claim having similar limitations as cited in claim 2. Thus, claim 9 is also rejected under the same rationale as cited in the rejection of claim 2 above. 11. As per claim 13, it is a method claim having similar limitations as cited in claim 6. Thus, claim 13 is also rejected under the same rationale as cited in the rejection of claim 6 above. 12. As per claim 14, it is a method claim having similar limitations as cited in claim 7. Thus, claim 14 is also rejected under the same rationale as cited in the rejection of claim 7 above. 13. As per claim 15, it is a system claim having similar limitations as cited in claim 1. Thus, claim 15 is also rejected under the same rationale as cited in the rejection of claim 1 above. 14. As per claim 16, it is a system claim having similar limitations as cited in claim 2. Thus, claim 16 is also rejected under the same rationale as cited in the rejection of claim 2 above. 15. As per claim 20, it is a system claim having similar limitations as cited in claim 6. Thus, claim 20 is also rejected under the same rationale as cited in the rejection of claim 6 above . Claim Rejections - 35 USC § 103 07-20-aia AIA 16. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA 17. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA 18. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA 19. Claim s 3, 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Bolz in further view of Parker et al. (U.S. Publication 2023/0021678) (Parker hereinafter) . 20. As per claim 3, Bolz teaches the one or more processors of claim 1. Bolz does not explicitly disclose but Lovett discloses wherein the indication comprises a flag to indicate to the circuitry that at least one of the one or more memory operations is to be performed synchronously [“ Thread A may synchronize with thread B by executing a MEMBAR.GL instruction and then storing a flag A. Once flag A is stored, the memory references for by thread A are visible to other threads in the GPU. After observing flag A, thread B may synchronize with thread C by executing a MEMBAR.SYS and then storing a flag B. Because thread B first synchronized with thread A via the MEMBAR.GL instruction and then executed a MEMBAR.SYS instruction, the MEMBAR.SYS instruction causes all memory references for both thread A and thread B, as well as all other threads in the GPU, to be visible to thread C. As a result, all threads in the GPU are synchronized at the system scope, whether or not these other threads need to synchronize with other GPUs and/or the CPU ,” ¶ 0003]. It would have been obvious to one of ordinary skill in the art, having the teachings of Bolz and Parker available before the effective filing date of the claimed invention, to modify the capability of managing memory coherency in graphics command streams as taught by Bolz to include the capability of thread synchronization as disclosed by Parker, thereby providing a mechanism to further enhance system efficiency by leveraging system resources using signaling mechanisms. 21. As per claim 10, it is a method claim having similar limitations as cited in claim 3. Thus, claim 10 is also rejected under the same rationale as cited in the rejection of claim 3 above. 22. As per claim 17, it is a system claim having similar limitations as cited in claim 3. Thus, claim 8 is also rejected under the same rationale as cited in the rejection of claim 3 above . 07-21-aia AIA 23. Claim s 4, 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Bolz in further view of Fabius (U.S. Patent 11,049,211) (Fabius hereinafter) . 24. As per claim 4, Bolz teaches the one or more processors of claim 1. Bolz does not explicitly disclose but Fabius discloses wherein the indication comprises a flag to indicate to the circuitry that at least one of the one or more memory operations is to be performed asynchronously [“ executing, by a second command processor, a second command buffer in the GPU asynchronously and in parallel to execution of the first command buffer, wherein executing the second command buffer comprises: monitoring the frame completed flag variable in the shared memory to determine if the variable is set to the first value ,” Cl. 1]. It would have been obvious to one of ordinary skill in the art, having the teachings of Bolz and Fabius available before the effective filing date of the claimed invention, to modify the capability of managing memory coherency in graphics command streams as taught by Bolz to include the capability of asynchronous buffer processing as disclosed by Parker, thereby providing a mechanism to further enhance system efficiency by coordinating system resources using signaling mechanisms. 25. As per claim 11, it is a method claim having similar limitations as cited in claim 4. Thus, claim 11 is also rejected under the same rationale as cited in the rejection of claim 4 above. 26. As per claim 18, it is a system claim having similar limitations as cited in claim 4. Thus, claim 18 is also rejected under the same rationale as cited in the rejection of claim 4 above . 07-21-aia AIA 27. Claim s 5, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Bolz in further view of Basu et al. (U.S. Publication 2022/0214805) (Basu hereinafter) (Identified by Applicant in IDS) . 28. As per claim 5, Bolz teaches the one or more processors of claim 1. wherein the circuitry, in further response to receipt of the API call, is to receive one or more input values indicating a device to be used to perform the one or more memory operations and the one or more other memory operations [“ the controller 115 can select at least one memory device and can select at least one storage device. For instance, the controller 115 can select both of the memory device 130 and the storage device 140. In such embodiments, the selected memory device 130 and storage device 140 can each perform at least a portion of a memory operation and / or permit substantially concurrent performance of memory operations on the memory device 130 and the storage device 140 ,” ¶ 0034]. It would have been obvious to one of ordinary skill in the art, having the teachings of Bolz and Basu available before the effective filing date of the claimed invention, to modify the capability of managing memory coherency in graphics command streams as taught by Bolz to include the capability of runtime selection of memory devices as disclosed by Basu, thereby providing a mechanism to further enhance system efficiency by coordinating available system resources. 29. As per claim 12, it is a method claim having similar limitations as cited in claim 5. Thus, claim 12 is also rejected under the same rationale as cited in the rejection of claim 5 above. 30. As per claim 19, it is a system claim having similar limitations as cited in claim 5. Thus, claim 19 is also rejected under the same rationale as cited in the rejection of claim 5 above . 07-21-aia AIA 31. Claim s 5, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Bolz in further view of Schumacher et al. (U.S. Patent 9,081,925) (Schumacher hereinafter) . 32. As per claim 21, Bolz teaches the one or more processors of claim 1. Bolz does not explicitly disclose but Schumacher discloses wherein the circuitry, in further response to receipt of the API call, is to cause one or more additional indications to be read from the primary context data structure, the one or more additional indications indicating how a graphics processing unit (GPU) is to behave while waiting for the one or more other memory operations to complete [“ Accelerator programming data can specify one or more settings or values that specify behavioral characteristics of each generic accelerator 210-220 ,” col. 5, lines 34 – 36; accelerator programming data mapped to indications of how GPU is to behave, accelerator mapped to GPU ; “ the accelerator programming data can specify one or more commands for moving data between processor 205 and the generic accelerator. The various commands can include read commands, write commands, or a combination of read and write commands. Each respective read and/or write command can specify an amount of data that is to be read or written. Each read and/or write command also can specify a "delay" parameter that indicates the amount of time to wait before the generic accelerator is to implement the command after the prior command executes (e.g., after the prior transaction completes). In addition, each of the generic accelerators can be configured to implement a repeat, e.g., loop, mode. In the repeat mode, the same sequence of data traffic patterns, e.g., sequence of commands, can be repeated for a particular number of times as specified through programming of the generic accelerator ,” col. 5, lines 34 – 49; delays, repeat mode, etc. are examples of GPU behaviors ]. It would have been obvious to one of ordinary skill in the art, having the teachings of Bolz and Schumacher available before the effective filing date of the claimed invention, to modify the capability of managing memory coherency in graphics command streams as taught by Bolz to include the capability of accelerator execution management as disclosed by Schumacher, thereby providing a mechanism to further enhance system efficiency by coordinating processor behaviors. Response to Arguments Claim Objections 33. Applicant’s amendments fully address the subject objections which are hereby withdrawn. Examiner Interview 34. Applicant asserts on page 6 that it was agreed that “that amendments presented above, in combination with other features of the claims discussed, did not appear to be disclose by the art of record.” However, as reflected in the Office Action summary and associated attachment mailed on 2/27/2026, no proposed amendments were presented and no agreements were reached. There was a discussion regarding the claim language of the independent claims (i.e., “A processor comprising: one or more circuits to perform an application programming interface (API) to cause an indication to be read …”) as being open to broad interpretation including intended use, such that any processor with the capability to perform an API would read on the claims as drafted in their initial form and that the adopted langrage in amended claim one would likely overcome this issue. No other proposed amendments were discussed or agreed to. Claim Rejections - 35 USC § 102 07-37 35. Applicant's arguments have been fully considered but they are not persuasive. 36. As recited above, the noted vertex shader in Bolz processing the vertex attributes and data assembler gathering data from buffers both suggest an indication to be read from a primary context data structure. Additionally, barrier command execution guarantees synchronization of memory operations, suggesting memory operations dependence. Conclusion 07-39 AIA 37. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. 38. Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM C WOOD whose telephone number is (571)272-5285. The examiner can normally be reached Monday - Friday, 8:00 am - 4:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chat C Do can be reached at 571-272-3721. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WILLIAM C WOOD/Examiner, Art Unit 2193 /Chat C Do/Supervisory Patent Examiner, Art Unit 2193 Application/Control Number: 18/114,664 Page 2 Art Unit: 2193 Application/Control Number: 18/114,664 Page 3 Art Unit: 2193 Application/Control Number: 18/114,664 Page 4 Art Unit: 2193 Application/Control Number: 18/114,664 Page 5 Art Unit: 2193 Application/Control Number: 18/114,664 Page 6 Art Unit: 2193 Application/Control Number: 18/114,664 Page 7 Art Unit: 2193 Application/Control Number: 18/114,664 Page 8 Art Unit: 2193 Application/Control Number: 18/114,664 Page 9 Art Unit: 2193 Application/Control Number: 18/114,664 Page 10 Art Unit: 2193 Application/Control Number: 18/114,664 Page 11 Art Unit: 2193 Application/Control Number: 18/114,664 Page 12 Art Unit: 2193 Application/Control Number: 18/114,664 Page 13 Art Unit: 2193 Application/Control Number: 18/114,664 Page 14 Art Unit: 2193
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