DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Office Action is sent in response to Applicant’s Communication received 2/27/2023 for application number 18/114,664. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, claims.
Claim Objections
3. Claims 2, 5, 7, 9, 12, 14, 16 and 19 are objected to because of the following informalities: each of the claims contain “perfom” instead of – perform --. Appropriate correction is required.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1, 2, 6 – 9, 13 – 16 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Bolz et al. (U.S. Publication 2011/0063313) (Bolz hereinafter) (Identified by Applicant in IDS).
6. As per claim 1, Bolz teaches a processor comprising:
one or more circuits to perform an application programming interface (API) [“FIG. 4 is a flow diagram of method steps for executing a memory barrier command within a stream of graphics application programming interface commands,” ¶ 0043] to cause an indication to be read from a primary context data structure [“The texture buffer 166 stores data elements typically organized in one dimensional arrays. The vertex buffer 165 stores data elements describing the position and other attributes of vertices provided as inputs to the vertex shader 152,” ¶ 0018; arrays mapped to data structures; “a memory management unit (MMU) 158. As is well-known, the vertex shader 152 receives a sequence of one or more sets of vertex attributes, where each set of vertex attributes is typically associated with one vertex and one or more vertices are associated with a geometric primitive. The vertex shader 152 processes the vertex attributes,” ¶ 0020; “The data assembler 260 may gather data from buffers stored within system memory 110 and GPU local memory 160 as well as from API calls from the application program 112 used to specify vertex attributes,” ¶ 0028]
of whether one or more memory operations to be performed are dependent on one or more other memory operations [“As described in greater detail below with respect to FIG. 4, high-level memory barrier (memoryBarrierNV()) commands are executable, by the GPU 150, within a stream of graphics API operations, where the memory barrier commands guarantee the synchronization of memory operations scheduled to be executed in a pipeline prior to the execution of each memory barrier command,” ¶ 0042; ”When data is written by one thread and consumed by other threads launched as a result of the execution of the one thread, coherent memory accesses should be performed, followed by a memory barrier command in the one thread. Further, the dependent threads should perform coherent memory loads when loading the data written by the first thread,” ¶ 0081].
7. As per claim 2, Bolz teaches the processor of claim 1. Bolz further teaches wherein the primary context data structure indicates a context to be used by the one or more circuits to perfom the one or more memory operations and the one or more other operations [“The memoryBarrierNV() OpenGL Shading Language (GLSL) operation—along with the “MEMBAR’ assembly operation, provides explicit synchronization that ensures a proper ordering of read and write operations within a shader thread. Memory operations scheduled for execution prior to the memory barrier command are all guaranteed to have completed to a point of coherence when the memory barrier command completes in execution. Further, the compiler does not re-order any load and store memory operations that are scheduled to execute subsequent to a memory barrier command, preventing any automatic optimizations from compromising the guaranteed point of coherence while permitting optimizations between barriers,” ¶ 0039; memory barrier command mapped to memory operation, read/write operations mapped to other operations].
8. As per claim 6, Bolz teaches the processor of claim 1. Bolz further teaches wherein the API is to cause the one or more circuits to receive one or more input values indicating a storage location to which the indication is to be read [“Memory barrier commands are needed for algorithms that allow multiple threads to access the same memory location. For such algorithms, memory operations associated with that memory location need to be performed in a partially-defined relative order,” ¶ 0040].
9. As per claim 7, Bolz teaches the processor of claim 1. Bolz further teaches wherein the API is to cause the one or more circuits to receive one or more input values indicating a storage location to which a state of a context to be used to perfom the one or more memory operations and the one or more other operations is to be stored [“FIG. 5 is a flow diagram of method steps for executing a memory barrier command in the context of a shader program that has multiple program invocations update a single shared block of memory,” 0015].
10. As per claim 8, it is a method claim having similar limitations as cited in claim 1. Thus, claim 8 is also rejected under the same rationale as cited in the rejection of claim 1 above.
11. As per claim 9, it is a method claim having similar limitations as cited in claim 2. Thus, claim 9 is also rejected under the same rationale as cited in the rejection of claim 2 above.
12. As per claim 13, it is a method claim having similar limitations as cited in claim 6. Thus, claim 13 is also rejected under the same rationale as cited in the rejection of claim 6 above.
13. As per claim 14, it is a method claim having similar limitations as cited in claim 7. Thus, claim 14 is also rejected under the same rationale as cited in the rejection of claim 7 above.
14. As per claim 15, it is a system claim having similar limitations as cited in claim 1. Thus, claim 15 is also rejected under the same rationale as cited in the rejection of claim 1 above.
15. As per claim 16, it is a system claim having similar limitations as cited in claim 2. Thus, claim 16 is also rejected under the same rationale as cited in the rejection of claim 2 above.
16. As per claim 20, it is a system claim having similar limitations as cited in claim 6. Thus, claim 20 is also rejected under the same rationale as cited in the rejection of claim 6 above.
Claim Rejections - 35 USC § 103
17. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
18. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
19. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
20. Claims 3, 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Bolz in further view of Parker et al. (U.S. Publication 2023/0021678) (Parker hereinafter).
21. As per claim 3, Bolz teaches the processor of claim 1. Bolz does not explicitly disclose but Lovett discloses wherein the indication comprises a flag to indicate to the one or more circuits that at least one of the one or more memory operations is to be performed synchronously [“Thread A may synchronize with thread B by executing a MEMBAR.GL instruction and then storing a flag A. Once flag A is stored, the memory references for by thread A are visible to other threads in the GPU. After observing flag A, thread B may synchronize with thread C by executing a MEMBAR.SYS and then storing a flag B. Because thread B first synchronized with thread A via the MEMBAR.GL instruction and then executed a MEMBAR.SYS instruction, the MEMBAR.SYS instruction causes all memory references for both thread A and thread B, as well as all other threads in the GPU, to be visible to thread C. As a result, all threads in the GPU are synchronized at the system scope, whether or not these other threads need to synchronize with other GPUs and/or the CPU,” ¶ 0003].
It would have been obvious to one of ordinary skill in the art, having the teachings of Bolz and Parker available before the effective filing date of the claimed invention, to modify the capability of managing memory coherency in graphics command streams as taught by Bolz to include the capability of thread synchronization as disclosed by Parker, thereby providing a mechanism to further enhance system efficiency by leveraging system resources using signaling mechanisms.
22. As per claim 10, it is a method claim having similar limitations as cited in claim 3. Thus, claim 10 is also rejected under the same rationale as cited in the rejection of claim 3 above.
23. As per claim 7, it is a system claim having similar limitations as cited in claim 3. Thus, claim 8 is also rejected under the same rationale as cited in the rejection of claim 3 above.
24. Claims 4, 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Bolz in further view of Fabius (U.S. Patent 11,049,211) (Fabius hereinafter).
25. As per claim 4, Bolz teaches the processor of claim 1. wherein the indication comprises a flag to indicate to the one or more circuits that at least one of the one or more memory operations is to be performed asynchronously [“executing, by a second command processor, a second command buffer in the GPU asynchronously and in parallel to execution of the first command buffer, wherein executing the second command buffer comprises: monitoring the frame completed flag variable in the shared memory to determine if the variable is set to the first value,” Cl. 1].
It would have been obvious to one of ordinary skill in the art, having the teachings of Bolz and Fabius available before the effective filing date of the claimed invention, to modify the capability of managing memory coherency in graphics command streams as taught by Bolz to include the capability of asynchronous buffer processing as disclosed by Parker, thereby providing a mechanism to further enhance system efficiency by coordinating system resources using signaling mechanisms.
26. As per claim 11, it is a method claim having similar limitations as cited in claim 4. Thus, claim 11 is also rejected under the same rationale as cited in the rejection of claim 4 above.
27. As per claim 18, it is a system claim having similar limitations as cited in claim 4. Thus, claim 18 is also rejected under the same rationale as cited in the rejection of claim 4 above.
28. Claims 5, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Bolz in further view of Basu et al. (U.S. Publication 2022/0214805) (Basu hereinafter) (Identified by Applicant in IDS).
29. As per claim 5, Bolz teaches the processor of claim 1. wherein the API is to cause the one or more circuits to receive one or more input values indicating a device to be used to perfom the one or more memory operations and the one or more other operations [“the controller 115 can select at least one memory device and can select at least one storage device. For instance, the controller 115 can select both of the memory device 130 and the storage device 140. In such embodiments, the selected memory device 130 and storage device 140 can each perform at least a portion of a memory operation and / or permit substantially concurrent performance of memory operations on the memory device 130 and the storage device 140,” ¶ 0034].
It would have been obvious to one of ordinary skill in the art, having the teachings of Bolz and Basu available before the effective filing date of the claimed invention, to modify the capability of managing memory coherency in graphics command streams as taught by Bolz to include the capability of runtime selection of memory devices as disclosed by Basu, thereby providing a mechanism to further enhance system efficiency by coordinating available system resources.
30. As per claim 12, it is a method claim having similar limitations as cited in claim 5. Thus, claim 12 is also rejected under the same rationale as cited in the rejection of claim 5 above.
31. As per claim 19, it is a system claim having similar limitations as cited in claim 5. Thus, claim 19 is also rejected under the same rationale as cited in the rejection of claim 5 above.
Conclusion
32. Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM C WOOD whose telephone number is (571)272-5285. The examiner can normally be reached Monday - Friday, 8:00 am - 4:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chat C Do can be reached at 571-272-3721. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM C WOOD/Examiner, Art Unit 2193
/Chat C Do/Supervisory Patent Examiner, Art Unit 2193