DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on April 6, 2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 27, 2023 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Memory Device With Improved Degree of Integration and Manufacturing Method of the Memory Device
Election/Restrictions
Applicant’s election without traverse of Species I (Fig. 4A, Claims 1-22) in the reply filed on November 15, 2025 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, lines: 2-3 recite the limitation “selection lines of a first group”, it is unclear whether it refers to the previous instance of “a first group” or is referring to a new first group. For purposes of examination this will be interpreted as “select lines of the first group”
Claim 1, lines: 4-5 recite the limitation “selection lines of a second group”, it is unclear whether it refers to the previous instance of “a second group” or is referring to a new second group. For purposes of examination this will be interpreted as “select lines of the second group”
Claim 1, lines: 12-13 recite the limitation “wherein the select lines of the first group include a first select line of a first group and a second select line of a first group”, it is unclear whether the first and second instances of “a first group” refer to the previously defined “the first group” or are referring to two different new first group. For purposes of examination this will be interpreted as “wherein the select lines of the first group include a first select line of the first group and a second select line of the first group”
Claim 1, lines: 15-16 recite the limitation “wherein the select lines of the second group include a first select line of a second group and a second select line of a second group”, it is unclear whether the first and second instances of “a second group” refer to the previously defined “the second group” or are referring to two different new second group. For purposes of examination this will be interpreted as “wherein the select lines of the second group include a first select line of the second group and a second select line of the second group” Claim 2, lines: 2 and 4 recite the limitation “a first group” and “a second group”, it is unclear whether “a first group” and “a second group” refer to the previously defined “the first group” and “the second group” or are referring to new first group and new second group. For purposes of examination this will be interpreted as “the first group” and “the second group”
Claim 12, lines: 2-3 recite the limitation “a third group”, it is unclear whether “a third group” refer to the previously defined “the third group” or are referring to new third group. For purposes of examination this will be interpreted as “the third group”
Claim 17, line 4, recite the limitation “select lines of a first group”, it is unclear whether “a first group” refer to the previously defined “a first group” or are referring to new first group. For purposes of examination this will be interpreted as “select lines of the first group”
Claim 17, line 16, recite the limitation “word lines of a Second group”, it is unclear whether “a second group” refer to the previously defined “a second group” or are referring to new second group. For purposes of examination this will be interpreted as “word lines of the second group”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
Claim(s) 1-2, 6-7, 11, and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oh (US 2010/0109065).
Claim 1, Oh discloses (see annotated Fig. 13 below) a memory device comprising: a first stack structure (LSG/CG1/724a, gate patterns/insulation patterns, Para [0171], hereinafter “stack1”) including a word line (CG1, lowermost cell gate pattern, Para [0172]) of a first group (first group referring to stack1 group, hereinafter “G1”) and select lines (multiple LSG on same row, lower select gate pattern, Para [0171]) of the first group (LSG of G1), wherein the select lines of the first group are isolated from each other (multiple LSGs are isolated from each other) ; a second stack structure (CG2/USG, second cell gate patterns/upper select gate pattern, Para [0171], hereinafter “stack2”) including a word line (CG2, second cell gate patterns, Para [0171]) of a second group (second group referring to stack2 group, hereinafter “G2”) and select lines (multiple USG on same row, upper select gate pattern, Para [0172]) of the second group (USG of G2), wherein the select lines of the second group are isolated from each other (multiple USGs are isolated from each other); a first plug (left ACT1, first sub-active bar, Para [0177], hereinafter “plug1”) in the first stack structure (plug1 is in stack1); a second plug (left ACT2, second sub-active bar, Para [0180], hereinafter “plug2”) connected to the first plug (plug2 is connected to plug1 through 746, Para [0181]), the second plug being disposed in the second stack structure (plug2 is disposed in stack2); a first isolation pattern (left 752, first filling insulating layer, Para [0177]) between the select lines of the first group (left 752 is between left LSGs); and a second isolation pattern (left 754, second filling insulating layer, Para [0180]) between the select lines of the second group (left 754 is between left USGs), wherein the select lines of the first group (left LSGs of G1) include a first select line (LSL1) of the first group (G1) and a second select line (LSL2) of the first group (G1), which respectively surround a first side portion (left side of plug1) and a second side portion (right side of plug1) of the first plug at both sides of the first isolation pattern (LSL1 and LSL2 surround left and right side of plug1 at both sides of left 752), and wherein the select lines of the second group (left USGs of G2) include a first select line (USL1) of the second group (G2) and a second select line (USL2) of the second group (G2), which respectively surround a first side portion (left side of plug2) and a second side portion (right side of plug2) of the second plug at both sides of the second isolation pattern (USL1 and USL2 surround left and right side of plug2 at both sides of left 754).
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Claim 2, Oh discloses (see annotated Fig. 13 above) the memory device of claim 1, comprising: select transistors (transistors formed LSL1 and LSL2, hereinafter “st1”) of the first group (G1), connected to the select lines of the first group (each st1 is connected to LSL1 or LSL2), the select transistors of the first group included in the first plug (st1 of G1 are included in plug1); and select transistors (transistors formed USL1 and USL2, hereinafter “st2”) of the second group (G2), connected to the select lines of the second group (each st2 is connected to USL1 or USL2), the select transistors of the second group included in the second plug (st2 of G2 are included in plug2); wherein the select transistors (st1) of the first group (G1) include a first select transistor (transistor of LSL1, hereinafter “t1”) and a second select transistor (transistor of LSL2, hereinafter “t2”), which are respectively connected to the first select line of the first group and the second select line of the first group (t1 is connected to LSL1 and t2 is connected to LSL2), and wherein the select transistors (st2) of the second group (G2) include a third select transistor (transistor of USL1, hereinafter “t3”) and a fourth select transistor (transistor of USL2, hereinafter “t4”), which are respectively connected to the first select line of the second group and the second select line of the second group (t3 is connected to USL1 and t4 is connected to USL2).
Claim 6, Oh discloses (see annotated Fig. 13 above) the memory device of claim 1, wherein the first isolation pattern (left 752) overlaps with a portion of the first plug (left 752 overlaps with a portion of plug1 in the lateral direction), and the second isolation pattern (left 754) overlaps with a portion of the second plug (left 754 overlaps with a portion of plug2 in the lateral direction). Claim 7, Oh discloses (see annotated Fig. 13 above) the memory device of claim 1, wherein the first isolation pattern (left 752) is in contact with a portion of the first plug between the first side portion and the second side portion of the first plug (left 752 is in contact with an inner portion of plug1 between left and right portion of plug1), and the second isolation pattern (left 754) is in contact with a portion of the second plug between the first side portion and the second side portion of the second plug (left 754 is in contact with an inner portion of plug2 between left and right portion of plug2). Claim 11, Oh discloses (see annotated Fig. 13 above) the memory device of claim 2, wherein the second stack structure (stack2) further includes: select lines (USL3/USL4 of right USG, upper select gate pattern, Para [0171], of a third group (right USG/CG2/724A, hereinafter “G3”) isolated from each other (USL3 and USL4 are isolated from one another); and a third isolation pattern (right 754, second filling insulating layer, Para [0180]) between the select lines of the third group (right 754is between USL3 and USL4 of G3). Claim 16, Oh discloses (see annotated Fig. 13 above) the memory device of claim 1, wherein the first plug (plug1) and the second plug (plug2) are aligned in a direction vertical to the select lines of the first group (plug1 and plug2 are aligned in a direction vertical to LSGs of G1).
Allowable Subject Matter
Claims 3-5, 8-10, and 12-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to overcome the 112 rejections above and in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Oh (US 2010/0109065), Lee (US 2012/00068247), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 3 (from which claims 4-5 depend), the second select transistor and the fourth select transistor are connected to each other along the other side of the first plug and the second plug.
Regarding Claim 8 (from which claims 9-10 depend), wherein each of the first plug and the second plug includes a capping layer, a core pillar…
Regarding Claim 12 (from which claims 13-14 depend), wherein the first select line of the third group and the second select line of the third group respectively surround a first side portion and a second side portion of the second plug at both sides of the third isolation pattern.
Regarding Claim 15, a first dummy word line disposed below the word line of the first group; or a second dummy word line disposed between the word line of the first group and the select lines of the first group.
Claims 17-22 would be allowed if rewritten to overcome the 112 rejections above.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Oh (US 2010/0109065), Lee (US 2012/00068247), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 17 (from which claims 18-22 depend), forming, on the first stack structure, a first sub-structure including select lines of a second group, wherein the select lines of the second group are isolated from each other; forming a second isolation pattern isolating the select lines of the second group from each other; and forming, above the select lines of the second group, a second sub-structure including word lines of the second group and select lines of a third group…
Oh discloses the first stack structure (stack1), first isolation pattern (left 752), first plug (left ACT1) and forming a first sub-structure including select lines (stack2 with USL1/USL2), but Oh does not disclose forming above the select lines a second sub-structure including word lines.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee discloses (Fig. 33) a first stack HS1/HS2 with plug VS and an isolation structure 265 isolating select top lines HS1. Lee does not disclose a second stack structure with a second plug connected to the first plug and select lines.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/G.G.R/Examiner, Art Unit 2812