DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
Content of Specification
(b) CROSS-REFERENCES TO RELATED APPLICATIONS: See 37 CFR 1.78 and MPEP § 211 et seq.
The disclosure is objected to because the application is claiming foreign priority under 35 USC 119(e) to United Kingdom 2202733.8 02/28/2022 but the specification does not contain a reference to such designation. See CFR 1.78(a)(3).
Appropriate correction is required.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “904” has been used to designate both the NNA and GPU (see [0088-0089]).
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: “mapping unit 12, MMM 40, and hardware accelerator 200” and “a communication bus 905. A store 912 (corresponding to memory 25)” in [0088].
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
There is insufficient antecedent basis for this limitation in the following claims:
Claim 1 recites the limitations "the respective bits" in line 7 and “the position of the first one bit” in line 8. Claims 2-15, 17-18, 20 inherit the deficiencies by reasons of dependence on claim 1 and are similarly rejected. Corresponding claim 16 recite similar deficiencies to claim 1 and is similarly rejected. Claim 19 inherits the deficiencies by reasons of dependence on claim 16 and is similarly rejected.
Claim 3 recites the limitation “the whole vector” in line 12.
Claim 4 recites the limitation “the least significant bit” in lines 2-3.
Claim 5 recites the limitation “the most significant bit” in lines 2-3.
Claim 6 recites the limitation “the most significant bits end” in lines 2-3.
Claim 7 recites the limitation “the most significant bit” in line 2. Claim 8 inherits the deficiency by reasons of dependence and is similarly rejected.
Claim 8 recites the limitations “the least significant bits” in line 2 and “the most significant bits” in line 3.
Claim 10 recites the limitations “the starting search position” in line 3 and “the relative location” in line 5. Claims 11-12 inherit the same deficiencies by reasons of dependence on claim 10 and are similarly rejected.
Claim 12 recites the limitation “the first bit” in line 4.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is
directed to an abstract idea without significantly more.
Regarding claim 1, under the Alice Framework Step 1 analysis, the claim falls within the four statutory categories of patentable subject matter: a method.
Under the Alice Framework Step 2A Prong 1 analysis, claim 1 recites Mathematical Concepts and/or Mental Processes. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas, and/or recites Evaluations, which is specifically identified as an exemplar in the Mental Processes grouping of abstract ideas:
“method of processing a vector, the method comprising:
grouping the bits of the vector into mutually exclusive pairs of two adjacent
bits;
identifying, for each pair of two, the presence or absence of a one bit and outputting, for each pair of two, a first level indicator output indicating whether a one bit is present in the respective bits of the vector and, for each pair of two, a first level position output indicating the position of the first one bit in the respective bits of the pair;
grouping the first level indicator outputs and the first level position outputs into mutually exclusive groups of two adjacent first level indicator outputs and first level position outputs; and
determining (i) based on a group of two adjacent first level indicator outputs, the presence or absence of a one bit in the respective bits of the vector and outputting, for each group of two adjacent first level indicator outputs, a second level indicator output indicating whether a one bit is present in the respective bits of the vector and (ii) based on a group of two adjacent first level position outputs, the position of the first one bit in the respective bits of the vector and outputting, for each group of two adjacent first level position outputs, a second level position output indicating the position of the first one bit in the respective bits of the vector.”
See specification ([0006]) describing processing. See specification ([0043]) describing grouping. See specification ([0044-0046]) describing identifying. See specification ([0047]) describing grouping. See specification ([0050-0057]) describing determining. The steps of “processing”, “grouping”, “identifying”, “grouping”, and “determining” are processes that under the broadest reasonable interpretation, cover performance of the limitations in the mind. That is, other than reciting “receiving the vector”, nothing in the claim element precludes the steps from practicality being performed in the human mind. For example, but for the “receiving the vector” language, the claim encompasses manually assessing pairs of two bits, determining if a “1” exists in each pair (for the example given a total length of 8 bit so 4 pairs of two), and use that information for further “1” determinations, using pen and paper, as shown in at least Fig. 4A and described in the above paragraphs. For these reasons, the claim recites Mathematical Concepts and/or Mental Processes.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: receiving the vector. The “receiving the vector” limitation is an example of insignificant extra-solution activity, mere data gathering (see MPEP 2106.05(g): Insignificant Extra-Solution Activity). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites limitations described above as an insignificant extra-solution activity. This limitation is also well-understood, routine, or conventional (see MPEP 2106.05(d)(II)(i): Receiving or transmitting data over a network). Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 1 is ineligible.
Claims 2-15 merely further limit the abstract idea and do not appear to recite any new additional elements.
Under the Alice Framework Step 2A Prong 1 analysis, claim 17 recites Mathematical Concepts and/or Mental Processes. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas, and/or recites Evaluations, which is specifically identified as an exemplar in the Mental Processes grouping of abstract ideas:
“performing the method as set forth in claim 1”
See specification ([0006], [0043-0047], [0050-0057]) describing performing the method as in claim 1. For these reasons, the claim recites Mathematical Concepts and/or Mental Processes.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: a graphics processing system. The graphics processing system is an example of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). The claim recites limitations which are examples of generic computing elements that result in “apply it” on a computer and/or generally link the abstract idea to a particular technological environment. Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites generic computing components which merely result in “apply it” on a computer and/or generally link the abstract idea to a particular technological environment. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 17 is ineligible.
Under the Alice Framework Step 2A Prong 2 analysis, claim 18 recites the combination of the following additional elements: the graphics processing system is embodied in hardware on an integrated circuit. The graphics processing system is embodied in hardware on an integrated circuit is an example of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). The claim recites limitations which are examples of generic computing elements that result in “apply it” on a computer and/or generally link the abstract idea to a particular technological environment. Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites generic computing components which merely result in “apply it” on a computer and/or generally link the abstract idea to a particular technological environment. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 18 is ineligible.
Under the Alice Framework Step 2A Prong 1 analysis, claim 20 recites Mathematical Concepts and/or Mental Processes. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas, and/or recites Evaluations, which is specifically identified as an exemplar in the Mental Processes grouping of abstract ideas:
“performing the method as set forth in claim 1”
See specification ([0006], [0043-0047], [0050-0057]) describing performing the method as in claim 1. For these reasons, the claim recites Mathematical Concepts and/or Mental Processes.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: a non-transitory computer readable storage medium having stored thereon computer executable code configured. The non-transitory computer readable storage medium having stored thereon computer executable code configured is an example of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). The claim recites limitations which are examples of generic computing elements that result in “apply it” on a computer and/or generally link the abstract idea to a particular technological environment. Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites generic computing components which merely result in “apply it” on a computer and/or generally link the abstract idea to a particular technological environment. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 20 is ineligible.
Claims 16, 19 are directed to a method that recites similar limitations to claims 1, 17. The claims 1, 17 analysis similarly applies and claims 16, 19 are similarly rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-14, 16-20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 5383142 A Chung et al. (hereinafter “Chung”).
Regarding claim 1, Chung discloses a machine-implemented method of processing a vector (Fig. 1 “
A
0
…
A
7
” co. 2 ln. 63-67), the method comprising:
receiving the vector (Fig. 1 “11” co. 2 ln. 63-67, co. 3 ln. 15-16);
grouping the bits of the vector into mutually exclusive pairs of two adjacent bits (Fig. 1 “
A
0
A
1
”, “
A
2
A
3
” co. 3 ln. 32-37);
identifying, for each pair of two, the presence or absence of a one bit and outputting, for each pair of two, a first level indicator output indicating whether a one bit is present in the respective bits of the vector (Figs. 1-2 “S” co. 3 ln. 15-38) and, for each pair of two, a first level position output indicating the position of the first one bit in the respective bits of the pair (Figs. 1-2 “O” co. 3 ln. 15-38);
grouping the first level indicator outputs and the first level position outputs into mutually exclusive groups of two adjacent first level indicator outputs and first level position outputs (Fig. 1 “
S
1
O
1
”, “
S
2
O
2
” output from level containing “14, 13” co. 3 ln. 38-68, co. 4 ln. 1-25); and
determining (i) based on a group of two adjacent first level indicator outputs, the presence or absence of a one bit in the respective bits of the vector (co. 3 ln. 38-68, co. 4 ln. 1-25 example in untitled Table) and outputting, for each group of two adjacent first level indicator outputs, a second level indicator output indicating whether a one bit is present in the respective bits of the vector (Fig. 1 “
S
1
O
1
”, “
S
2
O
2
” output from level containing “16, 15” co. 3 ln. 10-14, 38-68, co. 4 ln. 1-25) and (ii) based on a group of two adjacent first level position outputs (Fig. 1 adjacent to “14, 13” co. 3 ln. 38-68, co. 4 ln. 1-25), the position of the first one bit in the respective bits of the vector and outputting, for each group of two adjacent first level position outputs (Fig. 1 “
S
1
O
1
”, “
S
2
O
2
” output from level containing “14, 13” co. 3 ln. 38-68, co. 4 ln. 1-25), a second level position output indicating the position of the first one bit in the respective bits of the vector (Fig. 1 “
S
1
O
1
”, “
S
2
O
2
” output from level containing “16, 15” co. 3 ln. 10-14, 38-68, co. 4 ln. 1-25).
Regarding claim 2, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Chung discloses the method further comprising:
grouping the second level indicator outputs and the second level position outputs into mutually exclusive groups of two adjacent second level indicator outputs and second level position outputs (Fig. 1 “
S
1
O
1
”, “
S
2
O
2
” output from level containing “16, 15” co. 3 ln. 10-14, 38-68, co. 4 ln. 1-25);
determining (i) based on a group of two adjacent second level indicator outputs, the presence or absence of a one bit in the respective bits of the vector (co. 3 ln. 10-14, 38-68, co. 4 ln. 1-25 example in untitled Table) and outputting a third level indicator output indicating whether a one bit is present in the respective bits of the vector (Fig. 1 “STATE OUTPUT” and “OUTPUT” from level containing “18” co. 3 ln. 10-14, 38-68, co. 4 ln. 1-25) and (ii) based on a group of two adjacent second level position outputs (Fig. 1 adjacency of “15, 16” co. 3 ln. 38-68, co. 4 ln. 1-2), the position of the first one bit in the respective bits of the vector and outputting a third level position output indicating the position of the first one bit in the respective bits of the vector (Fig. 1 “STATE OUTPUT” and “OUTPUT” from level containing “18” co. 3 ln. 10-14, 38-68, co. 4 ln. 1-25).
Regarding claim 3, the teachings addressed in the claim 2 analysis and rejection are incorporated, and Chung discloses the method wherein
the steps of grouping (n-1)th level indicator outputs and (n-1)th level position outputs into mutually exclusive groups of two adjacent (n-1)th level indicator outputs and (n-1)th level position outputs (Fig. 1 “
S
1
O
1
”, “
S
2
O
2
” outputs from levels containing “16, 15” and “14, 13” and “STATE OUTPUT” and “OUTPUT” from “18” co. 3 ln. 10-14, 38-68, co. 4 ln. 1-25) and determining (i), based on a group of two adjacent (n-1)th level indicator outputs, the presence or absence of a one bit in the respective bits of the vector to output an n level indicator output indicating whether a one bit is present in the respective bits of the vector (co. 3 ln. 10-14, 38-68, co. 4 ln. 1-25 example in untitled Table), and (ii) based on a group of two adjacent (n-1)th level position outputs, the position of the first one bit in the respective bits of the vector and outputting an n level position output indicating the position of the first one bit in the respective bits of the vector are repeated until a grouping and determining step is determining the presence or absence of a one bit (Fig. 1 “
S
1
O
1
”, “
S
2
O
2
” output from level containing “14, 13”, “
S
1
O
1
”, “
S
2
O
2
” output from level containing “16, 15”, “STATE OUTPUT” and “OUTPUT” output from level containing “18” co. 3 ln. 38-68, co. 4 ln. 1-25), and the position of the first one bit in the whole vector (co. 3 ln. 10-14, 38-68, co. 4 ln. 1-25 example in untitled Table).
Regarding claim 4, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Chung discloses the method wherein
the position of the first one bit is starting from the least significant bit (co. 4 ln. 10-32
A
7
).
Regarding claim 5, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Chung discloses the method wherein
the position of the first one bit is starting from the most significant bit (co. 4 ln. 10-32
A
4
).
Regarding claim 6, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Chung discloses the method further comprising
adding zero bits to the vector at the most significant bits end until the vector has a length of a power of 2 (co. 5 ln. 3-11, 50-68; co. 6 ln. 1-7, 20-38 example “101” turns to “0101” in Table VI).
Regarding claim 7, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Chung discloses the method wherein
the most significant bit in the second level position output (Fig. 1 “
O
2
” output from level containing “15” co. 3 ln. 10-14, 38-68, co. 4 ln. 1-25) is based on the first one bit in the first level indicator outputs in the group of two adjacent first level indicator outputs (Fig. 1 “
S
1
O
1
”, “
S
2
O
2
” output from level containing “14, 13” co. 3 ln. 38-68, co. 4 ln. 1-25), a zero most significant bit indicating a first one bit in a first pair of two (co. 4 ln. 19-20 “
A
6
” is 0 ) and a one most significant bit indicating a first one bit in a second pair of two (co. 4 ln. 19-20 “
A
4
” is 1).
Regarding claim 8, the teachings addressed in the claim 7 analysis and rejection are incorporated, and Chung discloses the method wherein
wherein the least significant bits in the second level position output (Fig. 1 “
S
1
” output from level containing “16” co. 3 ln. 10-14, 38-68, co. 4 ln. 1-25) are the position input from the pair of two on which the most significant bit is based (Fig. 1 “
A
0
” co. 4 ln. 5-24).
Regarding claim 9, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Chung discloses the method wherein
a position output is only valid if the corresponding indicator output indicates that a zero is present (co. 3 ln. 15-38 “L”) in the respective bits of the vector (co. 4 ln. 17-25 “
A
0
A
1
” as an example).
Regarding claim 10, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Chung discloses the method further comprising
receiving an index position indicating the starting search position (Fig. 1 starting at “14” MSB “0” of “
A
0
” or “13” LSB “0” of “
A
7
”co. 3 ln. 3-5, 15-30);
switching each pair of two and each group of two into one of three states on the basis of the relative location of the index position and the position of the bits in the vector (Fig. 1 “0” to “7” of “
A
0
-
A
7
” co. 2 ln. 63-67), the three states comprising on (co. 3 ln. 15-38 “F”), off (co. 3 ln. 15-38 “L”) and indexed (co. 3 ln. 15-38 “X”),
wherein the outputting an indicator output based on each pair of two and each group of two (co. 3 ln. 5-9) comprises, if the pair or group of two is in an off state outputting an indicator output indicating that no one bit is present (co. 3 ln. 15-38 “L”), and if the pair or group of two is in an on state outputting an indicator output based on the presence or absence of a one bit (co. 3 ln. 15-38 “F”), and if the pair or group of two is in an indexed state outputting an indicator output based on the presence or absence of a one bit only for positions to be searched (co. 3 ln. 15-38 “X”).
Regarding claim 11, the teachings addressed in the claim 10 analysis and rejection are incorporated, and Chung discloses the method wherein
each pair of two and each group of two at a lower bit position than the index position is switched into an off state (co. 4 ln. 3-25 “
A
2
A
3
” L(0)), each pair of two and each group of two at a higher bit position than the index position is switched into an on state (co. 4 ln. 3-25 “
A
6
A
7
” F(1)), and each pair of two and each group of two including the index position is switched into an indexed state (co. 4 ln. 3-25 “
A
4
A
5
” X(0)).
Regarding claim 12, the teachings addressed in the claim 10 analysis and rejection are incorporated, and Chung discloses the method comprises
n levels of grouping (Fig. 1 3 levels from “14, 13” to “16, 15” to “18” co. 3 ln. 1-9, 62-66) and either identifying or determining the presence of absence of a one bit (Figs. 1-2 “S” co. 3 ln. 15-38) and the index position comprises n bits (co. 4 ln. 3-24 “100”), the first bit (Figs. 1-2 “O” co. 3 ln. 15-38) being applied to the nth level to switch each of the pair of groups or pairs at the (n-1 )th level into an on, off or indexed state (co. 3 ln. 45-65 Table II).
Regarding claim 13, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Chung discloses the method further comprising
identifying, in each pair of two, the presence or absence of a one bit and outputting a first level indicator output indicating whether a one bit is present in the respective bits of the vector (Figs. 1-2 “S” co. 3 ln. 15-38) and a first level position output indicating the position of the first one bit in the respective bits of the vector (Figs. 1-2 “S” co. 3 ln. 15-38);
grouping the first level indicator output and the first level position outputs into mutually exclusive groups of two adjacent first level indicator outputs and first level position outputs (Fig. 1 “
S
1
O
1
”, “
S
2
O
2
” output from level containing “14, 13” co. 3 ln. 38-68, co. 4 ln. 1-25);
determining (i) based on a group of two adjacent first level indicator outputs, the presence or absence of a one bit in the respective bits of the vector (co. 3 ln. 38-68, co. 4 ln. 1-25 example in untitled Table) and outputting a second level indicator output indicating whether a one bit is present in the respective bits of the vector (Fig. 1 “
S
1
O
1
”, “
S
2
O
2
” output from level containing “16, 15” co. 3 ln. 10-14, 38-68, co. 4 ln. 1-25) and (ii) based on a group of two adjacent first level position outputs (Fig. 1 adjacent to “14, 13” co. 3 ln. 38-68, co. 4 ln. 1-25), the position of the first one bit in the respective bits of the vector (Fig. 1 “
S
1
O
1
”, “
S
2
O
2
” output from level containing “14, 13” co. 3 ln. 38-68, co. 4 ln. 1-25) and outputting a second level position output indicating the position of the first one bit in the respective bits of the vector (Fig. 1 “
S
1
O
1
”, “
S
2
O
2
” output from level containing “16, 15” co. 3 ln. 10-14, 38-68, co. 4 ln. 1-25).
Regarding claim 14, the teachings addressed in the claim 13 analysis and rejection are incorporated, and Chung discloses the method wherein
if a one bit is identified (co. 4 ln. 1-24 “
A
7
” is 1) from the processing using an index position (Fig. 1 starting at “14” MSB “0” of “
A
0
” or “13” LSB “0” of “
A
7
”co. 3 ln. 3-5, 15-30), the position of the first one bit from the processing using an index is output as a result (co. 4 ln. 1-24 “F(1)”) and if a one bit is not identified (co. 4 ln. 1-24 “
A
6
” is 0) from the processing using an index position the position of the first one bit (co. 4 ln. 1-24 “
A
7
” is 1) from the processing with no index is output as a result (co. 4 ln. 19-20 pair “
A
6
A
7
” represented as “F(1)”).
Regarding claim 17, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Chung discloses
a graphics processing system (co. 1 ln. 64-68, co. 2 ln. 1-18) configured to perform the method as set forth in claim 1 (see claim 1 mapping).
Regarding claim 18, the teachings addressed in the claim 17 analysis and rejection are incorporated, and Chung discloses wherein
the graphics processing system is embodied in hardware on an integrated circuit (co. 3 ln. 1-9 processor with array of processing modules).
Regarding claim 20, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Chung discloses
a non-transitory computer readable storage medium having stored thereon computer executable code configured to cause the method as set forth in claim 1 to be performed when the code is run (co. 2 ln. 20-45; co. 8 ln. 1-12).
Claims 16, 19 are directed to a method that recites similar limitations to claims 1, 17. The claims 1, 17 analysis similarly applies and claims 16, 19 are similarly rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chung as applied to claim 1 above, and further in view of US 6523050 B1 Dhablania et al. (hereinafter “Dhablania”).
Regarding claim 15, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Chung discloses the method further comprising
prior to identifying, in each pair of two, the presence or absence of a one bit (co. 3 ln. 10-14, 38-68, co. 4 ln. 1-25), switching each one bit to a zero bit and each zero bit to a one bit.
Although Chung discloses identifying the presence or absence of a one bit, they appear to be silent to disclosing switching each one bit to a zero bit and each zero bit to a one bit.
Dhablania discloses switching each one bit to a zero bit and each zero bit to a one bit (co. 13 ln. 11-16 one’s complement).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Chung’s identifying a one bit limitation with the switching features as disclosed by Dhablania because they are in the claimed invention’s same field of endeavor of computer arithmetic hardware design (co. 1 ln. 26-28). Modifying with Dhablania’s switching feature would have been obvious to one of ordinary skill in the art as one’s complementing, which turns zeros to ones and ones to zeros, is a common arithmetic function and well known in the art (co. 3 ln. 19-62). Leading one detection circuits are widely used in floating-point adders as the location of the first one bit is required for correct normalization (Chung, co. 1 ln. 15-19). Using Dhablania’s well-known feature to yield a predictable result of switching values (co. 13 ln. 11-16) before the effective filing date would have been obvious since one of ordinary skill in the art would recognize the novel realization that one’s complementing can be allowed to occur before normalization (co. 3 ln. 39-52), yielding the benefit of ensuring the correctness of calculations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARKUS A VILLANUEVA whose telephone number is (703)756-1603. The examiner can normally be reached M - F 8:30 am - 5:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
Prosecution Insights