Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2-3 recite “two types of gate voltage modes” (the remaining claims incorporate the feature by dependency). Although the specification describes two types of confinement (paragraph [0054]), two types of transport (paragraph ]0056]), two types of gate electrodes (paragraph [0063]), two modules (paragraph [0090]), and two voltage control units (paragraph [0093]), it is not clear how “modes” is intended to be interpreted. It is not clear if a mode is related to subject matter of those citations given the common language, or perhaps a mode merely refers to DC and AC, digital or analog (see, for example, paragraph [0064]). Thus, the claims are rejected for being indefinite.
The following rejections are based on the Examiner’s best interpretation of the claims in view of the indefiniteness identified above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Leon et al. [US 2024/0290872 A1].
As per claim 1, a quantum computer of a semiconductor [0002, 0167], the computer comprising:
a semiconductor crystalline substrate [0052, 0055 semiconductor substrate];
a gate electrode array structure formed on a surface of the semiconductor crystalline substrate [0056 arrangement of gate electrodes]; and
a reservoir unit that is a carrier supply unit [0054 from a reservoir, not shown],
wherein a classic potential barrier is formed in the semiconductor crystalline substrate by controlling an applied voltage to the gate electrode array structure [0058 voltage bias applied, combination of voltages applied, 0063control and modify the voltages and/or biases applied to generate a confining electrostatic potential], and
a charge supplied from the reservoir unit is transported into the classic potential barrier [0062 confining electrostatic potential to bind electrons generated by arrangement of electrodes].
2. The quantum computer according to claim 1, wherein the quantum computer has at least two types of gate voltage modes for generating the classic potential barrier, and a quantum potential barrier having a voltage range different from that of the classic potential barrier [0056 arrangement of gate electrodes used to confine electrons, control spin, alter wavefunction, 0052 sufficiently positive voltages applied to gate electrode cause confinement, 0058 a voltage bias is less than a combination of voltages, 0063 one or more controllers may be used, 0109 as a function of the voltage, 0162 range of voltages].
5. The quantum computer according to claim 2, wherein the gate electrode array structure includes a single-electron pump for ejecting a unit charge from the reservoir unit [0048 single electron, 0107 single electron].
6. The quantum computer according to claim 5, wherein the single-electron pump includes a first gate controlling a first classic potential barrier, a second gate controlling a second classic potential barrier, and a third gate controlling a third classic potential barrier [0061 an array provides for first, second and third limitations, 0062 confining electrostatic potential generated by arrangement of gate electrodes, 0063 may further include controllers to control and modify the voltages and/or biases applied to gate electrodes to generate a confining electrostatic potential, 0139 FIG. 11 depicts the array with interaction], in order of proximity to the reservoir unit [0054 reservoir, not shown], and applies an AC voltage to the first gate [0054 AC electric field].
7. The quantum computer according to claim 6, wherein in order to transport the unit charge ejected by the single-electron pump, a gradient is set in the classic potential barrier formed in the semiconductor crystalline substrate [0048 the effect can also be achieved by manipulation of the wavefunction of a single electron, 0078 changing the shape of the confinement potential].
8. The quantum computer according to claim 7, wherein a change rate of a potential when setting the gradient in the classic potential barrier is set slower when transporting the unit charge after a quantum operation with respect to a quantum bit by the unit charge than when transporting the unit charge before the quantum operation with respect to the quantum bit by the unit charge [0021 slow EDSR].
9. The quantum computer according to claim 8, wherein when transporting the unit charge after the quantum operation with respect to the quantum bit, the change rate of the potential when setting the gradient in the classic potential barrier is set such that polarization of a spin of the unit charge is conserved [0023 idle, 0092 polarizability, 0093 spin is considered idle, 0126 FIG. 10C return to idle].
10. The quantum computer according to claim 9, wherein when transporting the unit charge during the quantum operation with respect to the quantum bit, the quantum potential barrier is used such that the polarization and a phase of the spin of the unit charge are conserved [0047, 0078 change the shape of the confinement potential, 0092 polarizability, 0093 spin is considered idle, 0126 FIG. 10C return to idle].
11. The quantum computer according to claim 10, wherein when transporting the unit charge before the quantum operation with respect to the quantum bit, the change rate of the potential when setting the gradient in the classic potential barrier is set regardless of the conservation of the polarization and the phase of the spin of the unit charge [0023 idle, 0047, 0078 change the shape of the confinement potential thereby allowing control over the excitation spectrum, 0092 polarizability, 0093 spin is considered idle, 0126 FIG. 10C return to idle].
12. The quantum computer according to claim 6, wherein a DC voltage applied to each of the first gate, the second gate, and the third gate, and the AC voltage applied to the first gate are calibrated [0095 Calibration Method, 0101 calibration for use in a given application, 0135 gate voltages depend on the context and need to be calibrated].
13. A control method for a quantum computer including a semiconductor, the method executing:
a first step of ejecting a unit charge by using a classic potential barrier from a reservoir unit that is a carrier supply unit [0048 single electron, 0053 from a reservoir, not shown, 0062 confining electrostatic potential to bind electrons generated by arrangement of electrodes, 0107 single electron];
a second step of sending the ejected unit charge to a desired quantum bit position by using a gradient of the classic potential barrier [0048 the effect can also be achieved by manipulation of the wavefunction of a single electron, 0078 changing the shape of the confinement potential]; and
a third step of performing a quantum bit operation with respect to the unit charge sent to the desired quantum bit position [0042, 0049, 0137 leveraged for applications, important for quantum information processing, 0159-0164 shuttling].
14. The control method for a quantum computer according to claim 13, wherein in the third step, when the unit charge is moved while the quantum bit operation is executed, the movement is performed by a manipulation of a quantum potential barrier [0078 changing in the shape of the confinement potential can be used in one of the applications].
15. The control method for a quantum computer according to claim 13, further executing a fourth step of performing a movement of the unit charge when the unit charge is moved in order to read out a quantum bit after the quantum bit operation is ended, by a manipulation of the classic potential barrier, wherein a manipulation speed of the classic potential barrier in the fourth step is set slower than a manipulation speed of the classic potential barrier in the second step [0159-0164 shuttling, 0116 initialising/reading out, 0078 changing the shape of the confinement potential, 0021 slow EDSR].
Claims 1-3, 5-7, 13-14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Künne et al. [US 2022/0335322 A1].
As per claim 1, a quantum computer of a semiconductor [0080], the computer comprising:
a semiconductor crystalline substrate [0078 semiconductor heterostructure, SiGe, substrate];
a gate electrode array structure formed on a surface of the semiconductor crystalline substrate [0082 gate electrode assemblies on a surface of the substrate]; and
a reservoir unit that is a carrier supply unit [unmarked hashed rectangle top left of FIG. 4, 0117 reservoir],
wherein a classic potential barrier is formed in the semiconductor crystalline substrate by controlling an applied voltage to the gate electrode array structure [0028 static and/or moving potential wells and/or potential barriers are generated by gate electrode assemblies, 0084 a potential well is generated in the substrate by applying voltages to the gate electrode assemblies], and
a charge supplied from the reservoir unit is transported into the classic potential barrier [0007 quantum dot, charge carriers, 0084 quantum dot in potential well].
2. The quantum computer according to claim 1, wherein the quantum computer has at least two types of gate voltage modes for generating the classic potential barrier, and a quantum potential barrier having a voltage range different from that of the classic potential barrier [0032 two parallel gate electrodes, 0083 two gate electrodes, 0085 two barrier gate electrodes].
3. The quantum computer according to claim 2, further comprising a switching unit switching the two types of gate voltage modes [0086 switched on, switched off].
5. The quantum computer according to claim 2, wherein the gate electrode array structure includes a single-electron pump for ejecting a unit charge from the reservoir unit [0087 pump gate electrodes, 0092 single qubit operation, 0094 single qubit operation].
6. The quantum computer according to claim 5, wherein the single-electron pump includes a first gate controlling a first classic potential barrier, a second gate controlling a second classic potential barrier, and a third gate controlling a third classic potential barrier, in order of proximity to the reservoir unit, and applies an AC voltage to the first gate [0087 a section through an electronic component is interpreted to be an exemplary first of first, second, and third with A to C in FIG. 4 depicting gates controlling potential barriers, unmarked hashed rectangle at top left of FIG. 4 depicts a reservoir, 0084 sinusoidal voltages].
7. The quantum computer according to claim 6, wherein in order to transport the unit charge ejected by the single-electron pump, a gradient is set in the classic potential barrier formed in the semiconductor crystalline substrate [0084 quantum dot trapped in potential well can be transported, 0086 switched, 0087 FIG. 4, 0092 single qubit operation, 0094 single qubit operation].
13. A control method for a quantum computer including a semiconductor [FIGS. 4, 6-7], the method executing:
a first step of ejecting a unit charge [element 152] by using a classic potential barrier [element 150] from a reservoir unit [unmarked hashed rectangle top left of FIG. 4] that is a carrier supply unit;
a second step of sending the ejected unit charge to a desired quantum bit position by using a gradient of the classic potential barrier [sequence B and C depict changes of the potential well that send element 152 toward the right, ]; and
a third step of performing a quantum bit operation with respect to the unit charge sent to the desired quantum bit position [0092 single qubit operation, 0094 single qubit operations, 0079 read out, 0081 reading out].
14. The control method for a quantum computer according to claim 13, wherein in the third step, when the unit charge is moved while the quantum bit operation is executed, the movement is performed by a manipulation of a quantum potential barrier [0092-0095 manipulation zone].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Leon et al. [US 2024/0290872 A1].
As per claim 4, Leon et al. teach the features from which the claim depends, including voltage range for generating the classic potential barrier, voltage range for generating the quantum potential barrier [0162 particular range of voltages needs to be calibrated on a case-by-case basis]. However, Leon et al. do not teach specific voltage ranges, wherein a voltage of 0.1 to 10 V is used as the voltage range for generating the classic potential barrier, and a voltage of 0.1 to 100 mV is used as the voltage range for generating the quantum potential barrier. Yet, the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because, given that Leon et al. teach that the particular range of voltages is influenced by uncontrollable chemical details of the material stack, a person of ordinary skill in the art would have found it obvious to try a variety of voltage ranges as a design choice dependent on the particular application to result in the claimed ranges.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See, for example, Chida et al. [JP 2017005040 A] at entire document; Leipold et al. [US 2020/0105994 A1] at FIGS. 17A-C, paragraph [0448]; Li et al. [US 2023/0389346 A1] at paragraph [0039]; Digler et al. [US 5,989,947] at FIG. 13, column 4, lines 18-41, column 9, lines 1-20, 43-50; Eriksson et al. [US 2002/0179897 A1] at Abstract, FIGS. 7-8, paragraphs [0045, 0051-0056, 0064-0065, 0081]; Morie et al. [US 6,661,022 B2] at Abstract, FIG. 11, column 10, line 63-column 11, line 23; Mortemosque et al. [US 2023/0194600 A1 at Abstract, FIG. 2, paragraphs [0003, 0180, 0185, 0190, 0195; Mohiyaddin et al. [2023/0196166 A1] at FIGS. 5a-d; George et al. [US 11,990,516 B1] at Abstract; Lampert et al. [US 12,342,733 B1] at Abstract; Van Diepen et al. [US 2022/0351063 A1] at Abstract; J.M. Elzerman et al. disclose "Single-shot read-out of an individual electron spin in a quantum dot;" W.G. van der Wiel et al. disclose "Electron transport through double quantum dots." See, also, Japanese Office Action dated October 7, 2025.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEIGH M GARBOWSKI whose telephone number is (571)272-1893. The examiner can normally be reached M-F 9-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LEIGH M GARBOWSKI/ Primary Examiner, Art Unit 2851